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28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/videodev2.h>
32#include <linux/module.h>
33#include <linux/v4l2-mediabus.h>
34#include <linux/of.h>
35#include <linux/of_graph.h>
36
37#include <media/v4l2-async.h>
38#include <media/v4l2-device.h>
39#include <media/v4l2-common.h>
40#include <media/v4l2-mediabus.h>
41#include <media/v4l2-fwnode.h>
42#include <media/v4l2-ctrls.h>
43#include <media/i2c/tvp514x.h>
44#include <media/media-entity.h>
45
46#include "tvp514x_regs.h"
47
48
49#define I2C_RETRY_COUNT (5)
50#define LOCK_RETRY_COUNT (5)
51#define LOCK_RETRY_DELAY (200)
52
53
54static bool debug;
55module_param(debug, bool, 0644);
56MODULE_PARM_DESC(debug, "Debug level (0-1)");
57
58MODULE_AUTHOR("Texas Instruments");
59MODULE_DESCRIPTION("TVP514X linux decoder driver");
60MODULE_LICENSE("GPL");
61
62
63enum tvp514x_std {
64 STD_NTSC_MJ = 0,
65 STD_PAL_BDGHIN,
66 STD_INVALID
67};
68
69
70
71
72
73
74
75
76struct tvp514x_std_info {
77 unsigned long width;
78 unsigned long height;
79 u8 video_std;
80 struct v4l2_standard standard;
81};
82
83static struct tvp514x_reg tvp514x_reg_list_default[0x40];
84
85static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
86
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104
105
106struct tvp514x_decoder {
107 struct v4l2_subdev sd;
108 struct v4l2_ctrl_handler hdl;
109 struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
110 const struct tvp514x_platform_data *pdata;
111
112 int ver;
113 int streaming;
114
115 struct v4l2_pix_format pix;
116 int num_fmts;
117 const struct v4l2_fmtdesc *fmt_list;
118
119 enum tvp514x_std current_std;
120 int num_stds;
121 const struct tvp514x_std_info *std_list;
122
123 u32 input;
124 u32 output;
125
126
127 struct media_pad pad;
128 struct v4l2_mbus_framefmt format;
129
130 struct tvp514x_reg *int_seq;
131};
132
133
134static struct tvp514x_reg tvp514x_reg_list_default[] = {
135
136 {TOK_WRITE, REG_INPUT_SEL, 0x05},
137 {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
138
139 {TOK_WRITE, REG_VIDEO_STD, 0x00},
140 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
141 {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
142 {TOK_WRITE, REG_COLOR_KILLER, 0x10},
143 {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
144 {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
145 {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
146 {TOK_WRITE, REG_BRIGHTNESS, 0x80},
147 {TOK_WRITE, REG_CONTRAST, 0x80},
148 {TOK_WRITE, REG_SATURATION, 0x80},
149 {TOK_WRITE, REG_HUE, 0x00},
150 {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
151 {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
152
153 {TOK_SKIP, 0x0F, 0x00},
154 {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
155 {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
156 {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
157
158 {TOK_SKIP, 0x13, 0x00},
159 {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
160
161 {TOK_SKIP, 0x15, 0x00},
162
163 {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
164 {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
165 {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
166 {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
167
168 {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
169 {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
170 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
171 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
172
173 {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
174 {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
175 {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
176 {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
177
178 {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
179 {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
180 {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
181 {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
182
183 {TOK_SKIP, 0x26, 0x00},
184
185 {TOK_SKIP, 0x27, 0x00},
186 {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
187
188 {TOK_SKIP, 0x29, 0x00},
189 {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
190
191 {TOK_SKIP, 0x2B, 0x00},
192 {TOK_SKIP, REG_SCART_DELAY, 0x00},
193 {TOK_SKIP, REG_CTI_DELAY, 0x00},
194 {TOK_SKIP, REG_CTI_CONTROL, 0x00},
195
196 {TOK_SKIP, 0x2F, 0x00},
197
198 {TOK_SKIP, 0x30, 0x00},
199
200 {TOK_SKIP, 0x31, 0x00},
201
202 {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
203
204 {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
205
206 {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
207
208 {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
209
210 {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
211 {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
212 {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
213
214 {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
215 {TOK_TERM, 0, 0},
216};
217
218
219
220
221
222
223static const struct v4l2_fmtdesc tvp514x_fmt_list[] = {
224 {
225 .index = 0,
226 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
227 .flags = 0,
228 .description = "8-bit UYVY 4:2:2 Format",
229 .pixelformat = V4L2_PIX_FMT_UYVY,
230 },
231};
232
233
234
235
236
237
238
239static const struct tvp514x_std_info tvp514x_std_list[] = {
240
241 [STD_NTSC_MJ] = {
242 .width = NTSC_NUM_ACTIVE_PIXELS,
243 .height = NTSC_NUM_ACTIVE_LINES,
244 .video_std = VIDEO_STD_NTSC_MJ_BIT,
245 .standard = {
246 .index = 0,
247 .id = V4L2_STD_NTSC,
248 .name = "NTSC",
249 .frameperiod = {1001, 30000},
250 .framelines = 525
251 },
252
253 },
254 [STD_PAL_BDGHIN] = {
255 .width = PAL_NUM_ACTIVE_PIXELS,
256 .height = PAL_NUM_ACTIVE_LINES,
257 .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
258 .standard = {
259 .index = 1,
260 .id = V4L2_STD_PAL,
261 .name = "PAL",
262 .frameperiod = {1, 25},
263 .framelines = 625
264 },
265 },
266
267};
268
269
270static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
271{
272 return container_of(sd, struct tvp514x_decoder, sd);
273}
274
275static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
276{
277 return &container_of(ctrl->handler, struct tvp514x_decoder, hdl)->sd;
278}
279
280
281
282
283
284
285
286
287
288static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
289{
290 int err, retry = 0;
291 struct i2c_client *client = v4l2_get_subdevdata(sd);
292
293read_again:
294
295 err = i2c_smbus_read_byte_data(client, reg);
296 if (err < 0) {
297 if (retry <= I2C_RETRY_COUNT) {
298 v4l2_warn(sd, "Read: retry ... %d\n", retry);
299 retry++;
300 msleep_interruptible(10);
301 goto read_again;
302 }
303 }
304
305 return err;
306}
307
308
309
310
311
312
313static void dump_reg(struct v4l2_subdev *sd, u8 reg)
314{
315 u32 val;
316
317 val = tvp514x_read_reg(sd, reg);
318 v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
319}
320
321
322
323
324
325
326
327
328
329
330static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
331{
332 int err, retry = 0;
333 struct i2c_client *client = v4l2_get_subdevdata(sd);
334
335write_again:
336
337 err = i2c_smbus_write_byte_data(client, reg, val);
338 if (err) {
339 if (retry <= I2C_RETRY_COUNT) {
340 v4l2_warn(sd, "Write: retry ... %d\n", retry);
341 retry++;
342 msleep_interruptible(10);
343 goto write_again;
344 }
345 }
346
347 return err;
348}
349
350
351
352
353
354
355
356
357
358
359
360
361
362static int tvp514x_write_regs(struct v4l2_subdev *sd,
363 const struct tvp514x_reg reglist[])
364{
365 int err;
366 const struct tvp514x_reg *next = reglist;
367
368 for (; next->token != TOK_TERM; next++) {
369 if (next->token == TOK_DELAY) {
370 msleep(next->val);
371 continue;
372 }
373
374 if (next->token == TOK_SKIP)
375 continue;
376
377 err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
378 if (err) {
379 v4l2_err(sd, "Write failed. Err[%d]\n", err);
380 return err;
381 }
382 }
383 return 0;
384}
385
386
387
388
389
390
391
392
393static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
394{
395 u8 std, std_status;
396
397 std = tvp514x_read_reg(sd, REG_VIDEO_STD);
398 if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
399
400 std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
401 else
402
403 std_status = std;
404
405 switch (std_status & VIDEO_STD_MASK) {
406 case VIDEO_STD_NTSC_MJ_BIT:
407 return STD_NTSC_MJ;
408
409 case VIDEO_STD_PAL_BDGHIN_BIT:
410 return STD_PAL_BDGHIN;
411
412 default:
413 return STD_INVALID;
414 }
415
416 return STD_INVALID;
417}
418
419
420static void tvp514x_reg_dump(struct v4l2_subdev *sd)
421{
422 dump_reg(sd, REG_INPUT_SEL);
423 dump_reg(sd, REG_AFE_GAIN_CTRL);
424 dump_reg(sd, REG_VIDEO_STD);
425 dump_reg(sd, REG_OPERATION_MODE);
426 dump_reg(sd, REG_COLOR_KILLER);
427 dump_reg(sd, REG_LUMA_CONTROL1);
428 dump_reg(sd, REG_LUMA_CONTROL2);
429 dump_reg(sd, REG_LUMA_CONTROL3);
430 dump_reg(sd, REG_BRIGHTNESS);
431 dump_reg(sd, REG_CONTRAST);
432 dump_reg(sd, REG_SATURATION);
433 dump_reg(sd, REG_HUE);
434 dump_reg(sd, REG_CHROMA_CONTROL1);
435 dump_reg(sd, REG_CHROMA_CONTROL2);
436 dump_reg(sd, REG_COMP_PR_SATURATION);
437 dump_reg(sd, REG_COMP_Y_CONTRAST);
438 dump_reg(sd, REG_COMP_PB_SATURATION);
439 dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
440 dump_reg(sd, REG_AVID_START_PIXEL_LSB);
441 dump_reg(sd, REG_AVID_START_PIXEL_MSB);
442 dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
443 dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
444 dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
445 dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
446 dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
447 dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
448 dump_reg(sd, REG_VSYNC_START_LINE_LSB);
449 dump_reg(sd, REG_VSYNC_START_LINE_MSB);
450 dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
451 dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
452 dump_reg(sd, REG_VBLK_START_LINE_LSB);
453 dump_reg(sd, REG_VBLK_START_LINE_MSB);
454 dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
455 dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
456 dump_reg(sd, REG_SYNC_CONTROL);
457 dump_reg(sd, REG_OUTPUT_FORMATTER1);
458 dump_reg(sd, REG_OUTPUT_FORMATTER2);
459 dump_reg(sd, REG_OUTPUT_FORMATTER3);
460 dump_reg(sd, REG_OUTPUT_FORMATTER4);
461 dump_reg(sd, REG_OUTPUT_FORMATTER5);
462 dump_reg(sd, REG_OUTPUT_FORMATTER6);
463 dump_reg(sd, REG_CLEAR_LOST_LOCK);
464}
465
466
467
468
469
470
471
472
473static int tvp514x_configure(struct v4l2_subdev *sd,
474 struct tvp514x_decoder *decoder)
475{
476 int err;
477
478
479 err =
480 tvp514x_write_regs(sd, decoder->tvp514x_regs);
481 if (err)
482 return err;
483
484 if (debug)
485 tvp514x_reg_dump(sd);
486
487 return 0;
488}
489
490
491
492
493
494
495
496
497
498
499
500
501static int tvp514x_detect(struct v4l2_subdev *sd,
502 struct tvp514x_decoder *decoder)
503{
504 u8 chip_id_msb, chip_id_lsb, rom_ver;
505 struct i2c_client *client = v4l2_get_subdevdata(sd);
506
507 chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
508 chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
509 rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
510
511 v4l2_dbg(1, debug, sd,
512 "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
513 chip_id_msb, chip_id_lsb, rom_ver);
514 if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
515 || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
516 && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
517
518
519
520 v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
521 chip_id_msb, chip_id_lsb);
522 return -ENODEV;
523 }
524
525 decoder->ver = rom_ver;
526
527 v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
528 client->name, decoder->ver,
529 client->addr << 1, client->adapter->name);
530 return 0;
531}
532
533
534
535
536
537
538
539
540
541static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
542{
543 struct tvp514x_decoder *decoder = to_decoder(sd);
544 enum tvp514x_std current_std;
545 enum tvp514x_input input_sel;
546 u8 sync_lock_status, lock_mask;
547
548 if (std_id == NULL)
549 return -EINVAL;
550
551
552 if (!decoder->streaming) {
553 tvp514x_s_stream(sd, 1);
554 msleep(LOCK_RETRY_DELAY);
555 }
556
557
558 current_std = tvp514x_query_current_std(sd);
559 if (current_std == STD_INVALID) {
560 *std_id = V4L2_STD_UNKNOWN;
561 return 0;
562 }
563
564 input_sel = decoder->input;
565
566 switch (input_sel) {
567 case INPUT_CVBS_VI1A:
568 case INPUT_CVBS_VI1B:
569 case INPUT_CVBS_VI1C:
570 case INPUT_CVBS_VI2A:
571 case INPUT_CVBS_VI2B:
572 case INPUT_CVBS_VI2C:
573 case INPUT_CVBS_VI3A:
574 case INPUT_CVBS_VI3B:
575 case INPUT_CVBS_VI3C:
576 case INPUT_CVBS_VI4A:
577 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
578 STATUS_HORZ_SYNC_LOCK_BIT |
579 STATUS_VIRT_SYNC_LOCK_BIT;
580 break;
581
582 case INPUT_SVIDEO_VI2A_VI1A:
583 case INPUT_SVIDEO_VI2B_VI1B:
584 case INPUT_SVIDEO_VI2C_VI1C:
585 case INPUT_SVIDEO_VI2A_VI3A:
586 case INPUT_SVIDEO_VI2B_VI3B:
587 case INPUT_SVIDEO_VI2C_VI3C:
588 case INPUT_SVIDEO_VI4A_VI1A:
589 case INPUT_SVIDEO_VI4A_VI1B:
590 case INPUT_SVIDEO_VI4A_VI1C:
591 case INPUT_SVIDEO_VI4A_VI3A:
592 case INPUT_SVIDEO_VI4A_VI3B:
593 case INPUT_SVIDEO_VI4A_VI3C:
594 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
595 STATUS_VIRT_SYNC_LOCK_BIT;
596 break;
597
598 default:
599 return -EINVAL;
600 }
601
602 sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
603 if (lock_mask != (sync_lock_status & lock_mask)) {
604 *std_id = V4L2_STD_UNKNOWN;
605 return 0;
606 }
607
608 *std_id &= decoder->std_list[current_std].standard.id;
609
610 v4l2_dbg(1, debug, sd, "Current STD: %s\n",
611 decoder->std_list[current_std].standard.name);
612 return 0;
613}
614
615
616
617
618
619
620
621
622
623static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
624{
625 struct tvp514x_decoder *decoder = to_decoder(sd);
626 int err, i;
627
628 for (i = 0; i < decoder->num_stds; i++)
629 if (std_id & decoder->std_list[i].standard.id)
630 break;
631
632 if ((i == decoder->num_stds) || (i == STD_INVALID))
633 return -EINVAL;
634
635 err = tvp514x_write_reg(sd, REG_VIDEO_STD,
636 decoder->std_list[i].video_std);
637 if (err)
638 return err;
639
640 decoder->current_std = i;
641 decoder->tvp514x_regs[REG_VIDEO_STD].val =
642 decoder->std_list[i].video_std;
643
644 v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
645 decoder->std_list[i].standard.name);
646 return 0;
647}
648
649
650
651
652
653
654
655
656
657
658
659
660static int tvp514x_s_routing(struct v4l2_subdev *sd,
661 u32 input, u32 output, u32 config)
662{
663 struct tvp514x_decoder *decoder = to_decoder(sd);
664 int err;
665 enum tvp514x_input input_sel;
666 enum tvp514x_output output_sel;
667
668 if ((input >= INPUT_INVALID) ||
669 (output >= OUTPUT_INVALID))
670
671 return -EINVAL;
672
673 input_sel = input;
674 output_sel = output;
675
676 err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
677 if (err)
678 return err;
679
680 output_sel |= tvp514x_read_reg(sd,
681 REG_OUTPUT_FORMATTER1) & 0x7;
682 err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
683 output_sel);
684 if (err)
685 return err;
686
687 decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
688 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
689 decoder->input = input;
690 decoder->output = output;
691
692 v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
693
694 return 0;
695}
696
697
698
699
700
701
702
703
704static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)
705{
706 struct v4l2_subdev *sd = to_sd(ctrl);
707 struct tvp514x_decoder *decoder = to_decoder(sd);
708 int err = -EINVAL, value;
709
710 value = ctrl->val;
711
712 switch (ctrl->id) {
713 case V4L2_CID_BRIGHTNESS:
714 err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value);
715 if (!err)
716 decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
717 break;
718 case V4L2_CID_CONTRAST:
719 err = tvp514x_write_reg(sd, REG_CONTRAST, value);
720 if (!err)
721 decoder->tvp514x_regs[REG_CONTRAST].val = value;
722 break;
723 case V4L2_CID_SATURATION:
724 err = tvp514x_write_reg(sd, REG_SATURATION, value);
725 if (!err)
726 decoder->tvp514x_regs[REG_SATURATION].val = value;
727 break;
728 case V4L2_CID_HUE:
729 if (value == 180)
730 value = 0x7F;
731 else if (value == -180)
732 value = 0x80;
733 err = tvp514x_write_reg(sd, REG_HUE, value);
734 if (!err)
735 decoder->tvp514x_regs[REG_HUE].val = value;
736 break;
737 case V4L2_CID_AUTOGAIN:
738 err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value ? 0x0f : 0x0c);
739 if (!err)
740 decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
741 break;
742 }
743
744 v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
745 ctrl->id, ctrl->val);
746 return err;
747}
748
749
750
751
752
753
754
755
756static int
757tvp514x_g_frame_interval(struct v4l2_subdev *sd,
758 struct v4l2_subdev_frame_interval *ival)
759{
760 struct tvp514x_decoder *decoder = to_decoder(sd);
761 enum tvp514x_std current_std;
762
763
764
765 current_std = decoder->current_std;
766
767 ival->interval =
768 decoder->std_list[current_std].standard.frameperiod;
769
770 return 0;
771}
772
773
774
775
776
777
778
779
780
781static int
782tvp514x_s_frame_interval(struct v4l2_subdev *sd,
783 struct v4l2_subdev_frame_interval *ival)
784{
785 struct tvp514x_decoder *decoder = to_decoder(sd);
786 struct v4l2_fract *timeperframe;
787 enum tvp514x_std current_std;
788
789
790 timeperframe = &ival->interval;
791
792
793 current_std = decoder->current_std;
794
795 *timeperframe =
796 decoder->std_list[current_std].standard.frameperiod;
797
798 return 0;
799}
800
801
802
803
804
805
806
807
808static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
809{
810 int err = 0;
811 struct tvp514x_decoder *decoder = to_decoder(sd);
812
813 if (decoder->streaming == enable)
814 return 0;
815
816 switch (enable) {
817 case 0:
818 {
819
820 err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
821 if (err) {
822 v4l2_err(sd, "Unable to turn off decoder\n");
823 return err;
824 }
825 decoder->streaming = enable;
826 break;
827 }
828 case 1:
829 {
830
831 err = tvp514x_write_regs(sd, decoder->int_seq);
832 if (err) {
833 v4l2_err(sd, "Unable to turn on decoder\n");
834 return err;
835 }
836
837 err = tvp514x_detect(sd, decoder);
838 if (err) {
839 v4l2_err(sd, "Unable to detect decoder\n");
840 return err;
841 }
842 err = tvp514x_configure(sd, decoder);
843 if (err) {
844 v4l2_err(sd, "Unable to configure decoder\n");
845 return err;
846 }
847 decoder->streaming = enable;
848 break;
849 }
850 default:
851 err = -ENODEV;
852 break;
853 }
854
855 return err;
856}
857
858static const struct v4l2_ctrl_ops tvp514x_ctrl_ops = {
859 .s_ctrl = tvp514x_s_ctrl,
860};
861
862
863
864
865
866
867
868
869
870static int tvp514x_enum_mbus_code(struct v4l2_subdev *sd,
871 struct v4l2_subdev_pad_config *cfg,
872 struct v4l2_subdev_mbus_code_enum *code)
873{
874 u32 pad = code->pad;
875 u32 index = code->index;
876
877 memset(code, 0, sizeof(*code));
878 code->index = index;
879 code->pad = pad;
880
881 if (index != 0)
882 return -EINVAL;
883
884 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
885
886 return 0;
887}
888
889
890
891
892
893
894
895
896
897static int tvp514x_get_pad_format(struct v4l2_subdev *sd,
898 struct v4l2_subdev_pad_config *cfg,
899 struct v4l2_subdev_format *format)
900{
901 struct tvp514x_decoder *decoder = to_decoder(sd);
902 __u32 which = format->which;
903
904 if (format->pad)
905 return -EINVAL;
906
907 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
908 format->format = decoder->format;
909 return 0;
910 }
911
912 format->format.code = MEDIA_BUS_FMT_UYVY8_2X8;
913 format->format.width = tvp514x_std_list[decoder->current_std].width;
914 format->format.height = tvp514x_std_list[decoder->current_std].height;
915 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
916 format->format.field = V4L2_FIELD_INTERLACED;
917
918 return 0;
919}
920
921
922
923
924
925
926
927
928
929static int tvp514x_set_pad_format(struct v4l2_subdev *sd,
930 struct v4l2_subdev_pad_config *cfg,
931 struct v4l2_subdev_format *fmt)
932{
933 struct tvp514x_decoder *decoder = to_decoder(sd);
934
935 if (fmt->format.field != V4L2_FIELD_INTERLACED ||
936 fmt->format.code != MEDIA_BUS_FMT_UYVY8_2X8 ||
937 fmt->format.colorspace != V4L2_COLORSPACE_SMPTE170M ||
938 fmt->format.width != tvp514x_std_list[decoder->current_std].width ||
939 fmt->format.height != tvp514x_std_list[decoder->current_std].height)
940 return -EINVAL;
941
942 decoder->format = fmt->format;
943
944 return 0;
945}
946
947static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
948 .s_std = tvp514x_s_std,
949 .s_routing = tvp514x_s_routing,
950 .querystd = tvp514x_querystd,
951 .g_frame_interval = tvp514x_g_frame_interval,
952 .s_frame_interval = tvp514x_s_frame_interval,
953 .s_stream = tvp514x_s_stream,
954};
955
956static const struct v4l2_subdev_pad_ops tvp514x_pad_ops = {
957 .enum_mbus_code = tvp514x_enum_mbus_code,
958 .get_fmt = tvp514x_get_pad_format,
959 .set_fmt = tvp514x_set_pad_format,
960};
961
962static const struct v4l2_subdev_ops tvp514x_ops = {
963 .video = &tvp514x_video_ops,
964 .pad = &tvp514x_pad_ops,
965};
966
967static const struct tvp514x_decoder tvp514x_dev = {
968 .streaming = 0,
969 .fmt_list = tvp514x_fmt_list,
970 .num_fmts = ARRAY_SIZE(tvp514x_fmt_list),
971 .pix = {
972
973 .width = NTSC_NUM_ACTIVE_PIXELS,
974 .height = NTSC_NUM_ACTIVE_LINES,
975 .pixelformat = V4L2_PIX_FMT_UYVY,
976 .field = V4L2_FIELD_INTERLACED,
977 .bytesperline = NTSC_NUM_ACTIVE_PIXELS * 2,
978 .sizeimage = NTSC_NUM_ACTIVE_PIXELS * 2 *
979 NTSC_NUM_ACTIVE_LINES,
980 .colorspace = V4L2_COLORSPACE_SMPTE170M,
981 },
982 .current_std = STD_NTSC_MJ,
983 .std_list = tvp514x_std_list,
984 .num_stds = ARRAY_SIZE(tvp514x_std_list),
985
986};
987
988static struct tvp514x_platform_data *
989tvp514x_get_pdata(struct i2c_client *client)
990{
991 struct tvp514x_platform_data *pdata = NULL;
992 struct v4l2_fwnode_endpoint bus_cfg;
993 struct device_node *endpoint;
994 unsigned int flags;
995
996 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
997 return client->dev.platform_data;
998
999 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1000 if (!endpoint)
1001 return NULL;
1002
1003 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
1004 goto done;
1005
1006 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1007 if (!pdata)
1008 goto done;
1009
1010 flags = bus_cfg.bus.parallel.flags;
1011
1012 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1013 pdata->hs_polarity = 1;
1014
1015 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1016 pdata->vs_polarity = 1;
1017
1018 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1019 pdata->clk_polarity = 1;
1020
1021done:
1022 of_node_put(endpoint);
1023 return pdata;
1024}
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034static int
1035tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1036{
1037 struct tvp514x_platform_data *pdata = tvp514x_get_pdata(client);
1038 struct tvp514x_decoder *decoder;
1039 struct v4l2_subdev *sd;
1040 int ret;
1041
1042 if (pdata == NULL) {
1043 dev_err(&client->dev, "No platform data\n");
1044 return -EINVAL;
1045 }
1046
1047
1048 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1049 return -EIO;
1050
1051 decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
1052 if (!decoder)
1053 return -ENOMEM;
1054
1055
1056 *decoder = tvp514x_dev;
1057
1058 memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1059 sizeof(tvp514x_reg_list_default));
1060
1061 decoder->int_seq = (struct tvp514x_reg *)id->driver_data;
1062
1063
1064 decoder->pdata = pdata;
1065
1066
1067
1068
1069
1070
1071 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
1072 (decoder->pdata->clk_polarity << 1);
1073 decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
1074 ((decoder->pdata->hs_polarity << 2) |
1075 (decoder->pdata->vs_polarity << 3));
1076
1077 decoder->tvp514x_regs[REG_VIDEO_STD].val =
1078 VIDEO_STD_AUTO_SWITCH_BIT;
1079
1080
1081 sd = &decoder->sd;
1082 v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
1083
1084#if defined(CONFIG_MEDIA_CONTROLLER)
1085 decoder->pad.flags = MEDIA_PAD_FL_SOURCE;
1086 decoder->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1087 decoder->sd.entity.flags |= MEDIA_ENT_F_ATV_DECODER;
1088
1089 ret = media_entity_pads_init(&decoder->sd.entity, 1, &decoder->pad);
1090 if (ret < 0) {
1091 v4l2_err(sd, "%s decoder driver failed to register !!\n",
1092 sd->name);
1093 return ret;
1094 }
1095#endif
1096 v4l2_ctrl_handler_init(&decoder->hdl, 5);
1097 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1098 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1099 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1100 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1101 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1102 V4L2_CID_SATURATION, 0, 255, 1, 128);
1103 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1104 V4L2_CID_HUE, -180, 180, 180, 0);
1105 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1106 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1107 sd->ctrl_handler = &decoder->hdl;
1108 if (decoder->hdl.error) {
1109 ret = decoder->hdl.error;
1110 goto done;
1111 }
1112 v4l2_ctrl_handler_setup(&decoder->hdl);
1113
1114 ret = v4l2_async_register_subdev(&decoder->sd);
1115 if (!ret)
1116 v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
1117
1118done:
1119 if (ret < 0) {
1120 v4l2_ctrl_handler_free(&decoder->hdl);
1121 media_entity_cleanup(&decoder->sd.entity);
1122 }
1123 return ret;
1124}
1125
1126
1127
1128
1129
1130
1131
1132
1133static int tvp514x_remove(struct i2c_client *client)
1134{
1135 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1136 struct tvp514x_decoder *decoder = to_decoder(sd);
1137
1138 v4l2_async_unregister_subdev(&decoder->sd);
1139 media_entity_cleanup(&decoder->sd.entity);
1140 v4l2_ctrl_handler_free(&decoder->hdl);
1141 return 0;
1142}
1143
1144static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1145 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1146 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1147 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1148 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1149 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1150 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1151 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1152 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1153 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1154 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1155 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1156 {TOK_TERM, 0, 0},
1157};
1158
1159
1160static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1161 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1162 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1163 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1164 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1165 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1166 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1167 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1168 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1169 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1170 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1171 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1172 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1173 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1174 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1175 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1176 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1177 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1178 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1179 {TOK_TERM, 0, 0},
1180};
1181
1182
1183static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1184 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1185 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1186 {TOK_TERM, 0, 0},
1187};
1188
1189
1190
1191
1192
1193
1194
1195static const struct i2c_device_id tvp514x_id[] = {
1196 {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1197 {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1198 {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1199 {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
1200 {},
1201};
1202
1203MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1204
1205#if IS_ENABLED(CONFIG_OF)
1206static const struct of_device_id tvp514x_of_match[] = {
1207 { .compatible = "ti,tvp5146", },
1208 { .compatible = "ti,tvp5146m2", },
1209 { .compatible = "ti,tvp5147", },
1210 { .compatible = "ti,tvp5147m1", },
1211 { },
1212};
1213MODULE_DEVICE_TABLE(of, tvp514x_of_match);
1214#endif
1215
1216static struct i2c_driver tvp514x_driver = {
1217 .driver = {
1218 .of_match_table = of_match_ptr(tvp514x_of_match),
1219 .name = TVP514X_MODULE_NAME,
1220 },
1221 .probe = tvp514x_probe,
1222 .remove = tvp514x_remove,
1223 .id_table = tvp514x_id,
1224};
1225
1226module_i2c_driver(tvp514x_driver);
1227