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19#ifndef __BNAD_H__
20#define __BNAD_H__
21
22#include <linux/rtnetlink.h>
23#include <linux/workqueue.h>
24#include <linux/ipv6.h>
25#include <linux/etherdevice.h>
26#include <linux/mutex.h>
27#include <linux/firmware.h>
28#include <linux/if_vlan.h>
29
30
31#include <asm/checksum.h>
32#include <net/ip6_checksum.h>
33
34#include <net/ip.h>
35#include <net/tcp.h>
36
37#include "bna.h"
38
39#define BNAD_TXQ_DEPTH 2048
40#define BNAD_RXQ_DEPTH 2048
41
42#define BNAD_MAX_TX 1
43#define BNAD_MAX_TXQ_PER_TX 8
44#define BNAD_TXQ_NUM 1
45
46#define BNAD_MAX_RX 1
47#define BNAD_MAX_RXP_PER_RX 16
48#define BNAD_MAX_RXQ_PER_RXP 2
49
50
51
52
53
54
55struct bnad_rx_ctrl {
56 struct bna_ccb *ccb;
57 struct bnad *bnad;
58 unsigned long flags;
59 struct napi_struct napi;
60 u64 rx_intr_ctr;
61 u64 rx_poll_ctr;
62 u64 rx_schedule;
63 u64 rx_keep_poll;
64 u64 rx_complete;
65};
66
67#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
68
69
70
71
72#define BNAD_NAME "bna"
73#define BNAD_NAME_LEN 64
74
75#define BNAD_VERSION "3.2.25.1"
76
77#define BNAD_MAILBOX_MSIX_INDEX 0
78#define BNAD_MAILBOX_MSIX_VECTORS 1
79#define BNAD_INTX_TX_IB_BITMASK 0x1
80#define BNAD_INTX_RX_IB_BITMASK 0x2
81
82#define BNAD_STATS_TIMER_FREQ 1000
83#define BNAD_DIM_TIMER_FREQ 1000
84
85#define BNAD_IOCETH_TIMEOUT 10000
86
87#define BNAD_MIN_Q_DEPTH 512
88#define BNAD_MAX_RXQ_DEPTH 16384
89#define BNAD_MAX_TXQ_DEPTH 2048
90
91#define BNAD_JUMBO_MTU 9000
92
93#define BNAD_NETIF_WAKE_THRESHOLD 8
94
95#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
96
97
98#define BNAD_TXQ_FREE_SENT 0
99#define BNAD_TXQ_TX_STARTED 1
100
101
102#define BNAD_RXQ_STARTED 0
103#define BNAD_RXQ_POST_OK 1
104
105
106#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
107#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
108
109#define BNAD_FRAME_SIZE(_mtu) \
110 (ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN)
111
112
113
114
115
116
117enum bnad_intr_source {
118 BNAD_INTR_TX = 1,
119 BNAD_INTR_RX = 2
120};
121
122enum bnad_link_state {
123 BNAD_LS_DOWN = 0,
124 BNAD_LS_UP = 1
125};
126
127struct bnad_iocmd_comp {
128 struct bnad *bnad;
129 struct completion comp;
130 int comp_status;
131};
132
133struct bnad_completion {
134 struct completion ioc_comp;
135 struct completion ucast_comp;
136 struct completion mcast_comp;
137 struct completion tx_comp;
138 struct completion rx_comp;
139 struct completion stats_comp;
140 struct completion enet_comp;
141 struct completion mtu_comp;
142
143 u8 ioc_comp_status;
144 u8 ucast_comp_status;
145 u8 mcast_comp_status;
146 u8 tx_comp_status;
147 u8 rx_comp_status;
148 u8 stats_comp_status;
149 u8 port_comp_status;
150 u8 mtu_comp_status;
151};
152
153
154struct bnad_drv_stats {
155 u64 netif_queue_stop;
156 u64 netif_queue_wakeup;
157 u64 netif_queue_stopped;
158 u64 tso4;
159 u64 tso6;
160 u64 tso_err;
161 u64 tcpcsum_offload;
162 u64 udpcsum_offload;
163 u64 csum_help;
164 u64 tx_skb_too_short;
165 u64 tx_skb_stopping;
166 u64 tx_skb_max_vectors;
167 u64 tx_skb_mss_too_long;
168 u64 tx_skb_tso_too_short;
169 u64 tx_skb_tso_prepare;
170 u64 tx_skb_non_tso_too_long;
171 u64 tx_skb_tcp_hdr;
172 u64 tx_skb_udp_hdr;
173 u64 tx_skb_csum_err;
174 u64 tx_skb_headlen_too_long;
175 u64 tx_skb_headlen_zero;
176 u64 tx_skb_frag_zero;
177 u64 tx_skb_len_mismatch;
178 u64 tx_skb_map_failed;
179
180 u64 hw_stats_updates;
181 u64 netif_rx_dropped;
182
183 u64 link_toggle;
184 u64 cee_toggle;
185
186 u64 rxp_info_alloc_failed;
187 u64 mbox_intr_disabled;
188 u64 mbox_intr_enabled;
189 u64 tx_unmap_q_alloc_failed;
190 u64 rx_unmap_q_alloc_failed;
191
192 u64 rxbuf_alloc_failed;
193 u64 rxbuf_map_failed;
194};
195
196
197struct bnad_stats {
198 struct bnad_drv_stats drv_stats;
199 struct bna_stats *bna_stats;
200};
201
202
203struct bnad_tx_res_info {
204 struct bna_res_info res_info[BNA_TX_RES_T_MAX];
205};
206
207struct bnad_rx_res_info {
208 struct bna_res_info res_info[BNA_RX_RES_T_MAX];
209};
210
211struct bnad_tx_info {
212 struct bna_tx *tx;
213 struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
214 u32 tx_id;
215 struct delayed_work tx_cleanup_work;
216} ____cacheline_aligned;
217
218struct bnad_rx_info {
219 struct bna_rx *rx;
220
221 struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
222 u32 rx_id;
223 struct work_struct rx_cleanup_work;
224} ____cacheline_aligned;
225
226struct bnad_tx_vector {
227 DEFINE_DMA_UNMAP_ADDR(dma_addr);
228 DEFINE_DMA_UNMAP_LEN(dma_len);
229};
230
231struct bnad_tx_unmap {
232 struct sk_buff *skb;
233 u32 nvecs;
234 struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI];
235};
236
237struct bnad_rx_vector {
238 DEFINE_DMA_UNMAP_ADDR(dma_addr);
239 u32 len;
240};
241
242struct bnad_rx_unmap {
243 struct page *page;
244 struct sk_buff *skb;
245 struct bnad_rx_vector vector;
246 u32 page_offset;
247};
248
249enum bnad_rxbuf_type {
250 BNAD_RXBUF_NONE = 0,
251 BNAD_RXBUF_SK_BUFF = 1,
252 BNAD_RXBUF_PAGE = 2,
253 BNAD_RXBUF_MULTI_BUFF = 3
254};
255
256#define BNAD_RXBUF_IS_SK_BUFF(_type) ((_type) == BNAD_RXBUF_SK_BUFF)
257#define BNAD_RXBUF_IS_MULTI_BUFF(_type) ((_type) == BNAD_RXBUF_MULTI_BUFF)
258
259struct bnad_rx_unmap_q {
260 int reuse_pi;
261 int alloc_order;
262 u32 map_size;
263 enum bnad_rxbuf_type type;
264 struct bnad_rx_unmap unmap[0] ____cacheline_aligned;
265};
266
267#define BNAD_PCI_DEV_IS_CAT2(_bnad) \
268 ((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2)
269
270
271#define BNAD_CF_DIM_ENABLED 0x01
272#define BNAD_CF_PROMISC 0x02
273#define BNAD_CF_ALLMULTI 0x04
274#define BNAD_CF_DEFAULT 0x08
275#define BNAD_CF_MSIX 0x10
276
277
278
279
280#define BNAD_RF_CEE_RUNNING 0
281#define BNAD_RF_MTU_SET 1
282#define BNAD_RF_MBOX_IRQ_DISABLED 2
283#define BNAD_RF_NETDEV_REGISTERED 3
284#define BNAD_RF_DIM_TIMER_RUNNING 4
285#define BNAD_RF_STATS_TIMER_RUNNING 5
286#define BNAD_RF_TX_PRIO_SET 6
287
288struct bnad {
289 struct net_device *netdev;
290 u32 id;
291
292
293 struct bnad_tx_info tx_info[BNAD_MAX_TX];
294 struct bnad_rx_info rx_info[BNAD_MAX_RX];
295
296 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
297
298
299
300
301
302
303 u32 num_tx;
304 u32 num_rx;
305 u32 num_txq_per_tx;
306 u32 num_rxp_per_rx;
307
308 u32 txq_depth;
309 u32 rxq_depth;
310
311 u8 tx_coalescing_timeo;
312 u8 rx_coalescing_timeo;
313
314 struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
315 struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;
316
317 void __iomem *bar0;
318
319 struct bna bna;
320
321 u32 cfg_flags;
322 unsigned long run_flags;
323
324 struct pci_dev *pcidev;
325 u64 mmio_start;
326 u64 mmio_len;
327
328 u32 msix_num;
329 struct msix_entry *msix_table;
330
331 struct mutex conf_mutex;
332 spinlock_t bna_lock ____cacheline_aligned;
333
334
335 struct timer_list ioc_timer;
336 struct timer_list dim_timer;
337 struct timer_list stats_timer;
338
339
340 struct bna_res_info res_info[BNA_RES_T_MAX];
341 struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
342 struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
343 struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
344
345 struct bnad_completion bnad_completions;
346
347
348 u8 perm_addr[ETH_ALEN];
349
350 struct workqueue_struct *work_q;
351
352
353 struct bnad_stats stats;
354
355 struct bnad_diag *diag;
356
357 char adapter_name[BNAD_NAME_LEN];
358 char port_name[BNAD_NAME_LEN];
359 char mbox_irq_name[BNAD_NAME_LEN];
360 char wq_name[BNAD_NAME_LEN];
361
362
363 char *regdata;
364 u32 reglen;
365 struct dentry *bnad_dentry_files[5];
366 struct dentry *port_debugfs_root;
367};
368
369struct bnad_drvinfo {
370 struct bfa_ioc_attr ioc_attr;
371 struct bfa_cee_attr cee_attr;
372 struct bfa_flash_attr flash_attr;
373 u32 cee_status;
374 u32 flash_status;
375};
376
377
378
379
380extern const struct firmware *bfi_fw;
381
382
383
384
385u32 *cna_get_firmware_buf(struct pci_dev *pdev);
386
387void bnad_set_rx_mode(struct net_device *netdev);
388struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev);
389int bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr);
390int bnad_enable_default_bcast(struct bnad *bnad);
391void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
392void bnad_set_ethtool_ops(struct net_device *netdev);
393void bnad_cb_completion(void *arg, enum bfa_status status);
394
395
396void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
397void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
398
399int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
400int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
401void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
402void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);
403
404
405void bnad_dim_timer_start(struct bnad *bnad);
406
407
408void bnad_netdev_qstats_fill(struct bnad *bnad,
409 struct rtnl_link_stats64 *stats);
410void bnad_netdev_hwstats_fill(struct bnad *bnad,
411 struct rtnl_link_stats64 *stats);
412
413
414void bnad_debugfs_init(struct bnad *bnad);
415void bnad_debugfs_uninit(struct bnad *bnad);
416
417
418
419#define BNAD_UPDATE_CTR(_bnad, _ctr) \
420 (((_bnad)->stats.drv_stats._ctr)++)
421
422#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
423
424#define bnad_enable_rx_irq_unsafe(_ccb) \
425{ \
426 if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
427 bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
428 (_ccb)->rx_coalescing_timeo); \
429 bna_ib_ack((_ccb)->i_dbell, 0); \
430 } \
431}
432
433#endif
434
