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16#ifndef HINIC_HW_WQE_H
17#define HINIC_HW_WQE_H
18
19#include "hinic_common.h"
20
21#define HINIC_CMDQ_CTRL_PI_SHIFT 0
22#define HINIC_CMDQ_CTRL_CMD_SHIFT 16
23#define HINIC_CMDQ_CTRL_MOD_SHIFT 24
24#define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29
25#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31
26
27#define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF
28#define HINIC_CMDQ_CTRL_CMD_MASK 0xFF
29#define HINIC_CMDQ_CTRL_MOD_MASK 0x1F
30#define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3
31#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1
32
33#define HINIC_CMDQ_CTRL_SET(val, member) \
34 (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \
35 << HINIC_CMDQ_CTRL_##member##_SHIFT)
36
37#define HINIC_CMDQ_CTRL_GET(val, member) \
38 (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \
39 & HINIC_CMDQ_CTRL_##member##_MASK)
40
41#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0
42#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15
43#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT 22
44#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT 23
45#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT 27
46#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT 29
47#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT 31
48
49#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF
50#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1
51#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1
52#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1
53#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3
54#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3
55#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1
56
57#define HINIC_CMDQ_WQE_HEADER_SET(val, member) \
58 (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \
59 << HINIC_CMDQ_WQE_HEADER_##member##_SHIFT)
60
61#define HINIC_CMDQ_WQE_HEADER_GET(val, member) \
62 (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \
63 & HINIC_CMDQ_WQE_HEADER_##member##_MASK)
64
65#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
66#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16
67#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22
68#define HINIC_SQ_CTRL_LEN_SHIFT 29
69
70#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
71#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F
72#define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1
73#define HINIC_SQ_CTRL_LEN_MASK 0x3
74
75#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2
76#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10
77#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11
78#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12
79#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13
80#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27
81#define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT 28
82#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29
83
84#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF
85#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1
86#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1
87#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1
88#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF
89#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1
90#define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1
91#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7
92
93#define HINIC_SQ_CTRL_SET(val, member) \
94 (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \
95 << HINIC_SQ_CTRL_##member##_SHIFT)
96
97#define HINIC_SQ_CTRL_GET(val, member) \
98 (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \
99 & HINIC_SQ_CTRL_##member##_MASK)
100
101#define HINIC_SQ_CTRL_CLEAR(val, member) \
102 ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \
103 << HINIC_SQ_CTRL_##member##_SHIFT)))
104
105#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
106#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8
107#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10
108#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12
109#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13
110
111#define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15
112#define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16
113
114#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF
115#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3
116#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3
117#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1
118#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1
119
120#define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1
121#define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF
122
123#define HINIC_SQ_TASK_INFO0_SET(val, member) \
124 (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \
125 HINIC_SQ_TASK_INFO0_##member##_SHIFT)
126
127
128#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8
129#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16
130#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24
131
132
133#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF
134#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF
135#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF
136
137#define HINIC_SQ_TASK_INFO1_SET(val, member) \
138 (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \
139 HINIC_SQ_TASK_INFO1_##member##_SHIFT)
140
141#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0
142#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8
143#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16
144
145#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24
146
147
148#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF
149#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF
150#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7
151
152#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3
153
154
155#define HINIC_SQ_TASK_INFO2_SET(val, member) \
156 (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \
157 HINIC_SQ_TASK_INFO2_##member##_SHIFT)
158
159
160#define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31
161
162
163#define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1
164
165#define HINIC_SQ_TASK_INFO4_SET(val, member) \
166 (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \
167 HINIC_SQ_TASK_INFO4_##member##_SHIFT)
168
169#define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31
170
171#define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1
172
173#define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT 0
174
175#define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK 0xFFFFU
176
177#define HINIC_RQ_CQE_STATUS_GET(val, member) \
178 (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \
179 HINIC_RQ_CQE_STATUS_##member##_MASK)
180
181#define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \
182 ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \
183 HINIC_RQ_CQE_STATUS_##member##_SHIFT)))
184
185#define HINIC_RQ_CQE_SGE_LEN_SHIFT 16
186
187#define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF
188
189#define HINIC_RQ_CQE_SGE_GET(val, member) \
190 (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \
191 HINIC_RQ_CQE_SGE_##member##_MASK)
192
193#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
194#define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15
195#define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27
196#define HINIC_RQ_CTRL_LEN_SHIFT 29
197
198#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
199#define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1
200#define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3
201#define HINIC_RQ_CTRL_LEN_MASK 0x3
202
203#define HINIC_RQ_CTRL_SET(val, member) \
204 (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \
205 HINIC_RQ_CTRL_##member##_SHIFT)
206
207#define HINIC_SQ_WQE_SIZE(nr_sges) \
208 (sizeof(struct hinic_sq_ctrl) + \
209 sizeof(struct hinic_sq_task) + \
210 (nr_sges) * sizeof(struct hinic_sq_bufdesc))
211
212#define HINIC_SCMD_DATA_LEN 16
213
214#define HINIC_MAX_SQ_BUFDESCS 17
215
216#define HINIC_SQ_WQE_MAX_SIZE 320
217#define HINIC_RQ_WQE_SIZE 32
218
219#define HINIC_MSS_DEFAULT 0x3E00
220#define HINIC_MSS_MIN 0x50
221
222enum hinic_l4offload_type {
223 HINIC_L4_OFF_DISABLE = 0,
224 HINIC_TCP_OFFLOAD_ENABLE = 1,
225 HINIC_SCTP_OFFLOAD_ENABLE = 2,
226 HINIC_UDP_OFFLOAD_ENABLE = 3,
227};
228
229enum hinic_vlan_offload {
230 HINIC_VLAN_OFF_DISABLE = 0,
231 HINIC_VLAN_OFF_ENABLE = 1,
232};
233
234enum hinic_pkt_parsed {
235 HINIC_PKT_NOT_PARSED = 0,
236 HINIC_PKT_PARSED = 1,
237};
238
239enum hinic_l3_offload_type {
240 L3TYPE_UNKNOWN = 0,
241 IPV6_PKT = 1,
242 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
243 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
244};
245
246enum hinic_l4_offload_type {
247 OFFLOAD_DISABLE = 0,
248 TCP_OFFLOAD_ENABLE = 1,
249 SCTP_OFFLOAD_ENABLE = 2,
250 UDP_OFFLOAD_ENABLE = 3,
251};
252
253enum hinic_l4_tunnel_type {
254 NOT_TUNNEL,
255 TUNNEL_UDP_NO_CSUM,
256 TUNNEL_UDP_CSUM,
257};
258
259enum hinic_outer_l3type {
260 HINIC_OUTER_L3TYPE_UNKNOWN = 0,
261 HINIC_OUTER_L3TYPE_IPV6 = 1,
262 HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2,
263 HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3,
264};
265
266enum hinic_media_type {
267 HINIC_MEDIA_UNKNOWN = 0,
268};
269
270enum hinic_l2type {
271 HINIC_L2TYPE_ETH = 0,
272};
273
274enum hinc_tunnel_l4type {
275 HINIC_TUNNEL_L4TYPE_UNKNOWN = 0,
276};
277
278struct hinic_cmdq_header {
279 u32 header_info;
280 u32 saved_data;
281};
282
283struct hinic_status {
284 u32 status_info;
285};
286
287struct hinic_ctrl {
288 u32 ctrl_info;
289};
290
291struct hinic_sge_resp {
292 struct hinic_sge sge;
293 u32 rsvd;
294};
295
296struct hinic_cmdq_completion {
297
298 union {
299 struct hinic_sge_resp sge_resp;
300 u64 direct_resp;
301 };
302};
303
304struct hinic_scmd_bufdesc {
305 u32 buf_len;
306 u32 rsvd;
307 u8 data[HINIC_SCMD_DATA_LEN];
308};
309
310struct hinic_lcmd_bufdesc {
311 struct hinic_sge sge;
312 u32 rsvd1;
313 u64 rsvd2;
314 u64 rsvd3;
315};
316
317struct hinic_cmdq_wqe_scmd {
318 struct hinic_cmdq_header header;
319 u64 rsvd;
320 struct hinic_status status;
321 struct hinic_ctrl ctrl;
322 struct hinic_cmdq_completion completion;
323 struct hinic_scmd_bufdesc buf_desc;
324};
325
326struct hinic_cmdq_wqe_lcmd {
327 struct hinic_cmdq_header header;
328 struct hinic_status status;
329 struct hinic_ctrl ctrl;
330 struct hinic_cmdq_completion completion;
331 struct hinic_lcmd_bufdesc buf_desc;
332};
333
334struct hinic_cmdq_direct_wqe {
335 struct hinic_cmdq_wqe_scmd wqe_scmd;
336};
337
338struct hinic_cmdq_wqe {
339
340 union {
341 struct hinic_cmdq_direct_wqe direct_wqe;
342 struct hinic_cmdq_wqe_lcmd wqe_lcmd;
343 };
344};
345
346struct hinic_sq_ctrl {
347 u32 ctrl_info;
348 u32 queue_info;
349};
350
351struct hinic_sq_task {
352 u32 pkt_info0;
353 u32 pkt_info1;
354 u32 pkt_info2;
355 u32 ufo_v6_identify;
356 u32 pkt_info4;
357 u32 zero_pad;
358};
359
360struct hinic_sq_bufdesc {
361 struct hinic_sge sge;
362 u32 rsvd;
363};
364
365struct hinic_sq_wqe {
366 struct hinic_sq_ctrl ctrl;
367 struct hinic_sq_task task;
368 struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS];
369};
370
371struct hinic_rq_cqe {
372 u32 status;
373 u32 len;
374
375 u32 rsvd2;
376 u32 rsvd3;
377 u32 rsvd4;
378 u32 rsvd5;
379 u32 rsvd6;
380 u32 rsvd7;
381};
382
383struct hinic_rq_ctrl {
384 u32 ctrl_info;
385};
386
387struct hinic_rq_cqe_sect {
388 struct hinic_sge sge;
389 u32 rsvd;
390};
391
392struct hinic_rq_bufdesc {
393 u32 hi_addr;
394 u32 lo_addr;
395};
396
397struct hinic_rq_wqe {
398 struct hinic_rq_ctrl ctrl;
399 u32 rsvd;
400 struct hinic_rq_cqe_sect cqe_sect;
401 struct hinic_rq_bufdesc buf_desc;
402};
403
404struct hinic_hw_wqe {
405
406 union {
407 struct hinic_cmdq_wqe cmdq_wqe;
408 struct hinic_sq_wqe sq_wqe;
409 struct hinic_rq_wqe rq_wqe;
410 };
411};
412
413#endif
414
