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7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/crc32.h>
11#include <linux/ethtool.h>
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/module.h>
16#include <linux/net_tstamp.h>
17#include <linux/netdevice.h>
18#include <linux/if_vlan.h>
19#include <linux/phy.h>
20#include <linux/ptp_classify.h>
21#include <linux/ptp_clock_kernel.h>
22
23#include "dp83640_reg.h"
24
25#define DP83640_PHY_ID 0x20005ce1
26#define PAGESEL 0x13
27#define MAX_RXTS 64
28#define N_EXT_TS 6
29#define N_PER_OUT 7
30#define PSF_PTPVER 2
31#define PSF_EVNT 0x4000
32#define PSF_RX 0x2000
33#define PSF_TX 0x1000
34#define EXT_EVENT 1
35#define CAL_EVENT 7
36#define CAL_TRIGGER 1
37#define DP83640_N_PINS 12
38
39#define MII_DP83640_MICR 0x11
40#define MII_DP83640_MISR 0x12
41
42#define MII_DP83640_MICR_OE 0x1
43#define MII_DP83640_MICR_IE 0x2
44
45#define MII_DP83640_MISR_RHF_INT_EN 0x01
46#define MII_DP83640_MISR_FHF_INT_EN 0x02
47#define MII_DP83640_MISR_ANC_INT_EN 0x04
48#define MII_DP83640_MISR_DUP_INT_EN 0x08
49#define MII_DP83640_MISR_SPD_INT_EN 0x10
50#define MII_DP83640_MISR_LINK_INT_EN 0x20
51#define MII_DP83640_MISR_ED_INT_EN 0x40
52#define MII_DP83640_MISR_LQ_INT_EN 0x80
53#define MII_DP83640_MISR_ANC_INT 0x400
54#define MII_DP83640_MISR_DUP_INT 0x800
55#define MII_DP83640_MISR_SPD_INT 0x1000
56#define MII_DP83640_MISR_LINK_INT 0x2000
57#define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\
58 MII_DP83640_MISR_DUP_INT |\
59 MII_DP83640_MISR_SPD_INT |\
60 MII_DP83640_MISR_LINK_INT)
61
62
63#define ADJTIME_FIX 16
64
65#define SKB_TIMESTAMP_TIMEOUT 2
66
67#if defined(__BIG_ENDIAN)
68#define ENDIAN_FLAG 0
69#elif defined(__LITTLE_ENDIAN)
70#define ENDIAN_FLAG PSF_ENDIAN
71#endif
72
73struct dp83640_skb_info {
74 int ptp_type;
75 unsigned long tmo;
76};
77
78struct phy_rxts {
79 u16 ns_lo;
80 u16 ns_hi;
81 u16 sec_lo;
82 u16 sec_hi;
83 u16 seqid;
84 u16 msgtype;
85};
86
87struct phy_txts {
88 u16 ns_lo;
89 u16 ns_hi;
90 u16 sec_lo;
91 u16 sec_hi;
92};
93
94struct rxts {
95 struct list_head list;
96 unsigned long tmo;
97 u64 ns;
98 u16 seqid;
99 u8 msgtype;
100 u16 hash;
101};
102
103struct dp83640_clock;
104
105struct dp83640_private {
106 struct list_head list;
107 struct dp83640_clock *clock;
108 struct phy_device *phydev;
109 struct mii_timestamper mii_ts;
110 struct delayed_work ts_work;
111 int hwts_tx_en;
112 int hwts_rx_en;
113 int layer;
114 int version;
115
116 int cfg0;
117
118 struct phy_txts edata;
119
120 struct list_head rxts;
121 struct list_head rxpool;
122 struct rxts rx_pool_data[MAX_RXTS];
123
124 spinlock_t rx_lock;
125
126 struct sk_buff_head rx_queue;
127 struct sk_buff_head tx_queue;
128};
129
130struct dp83640_clock {
131
132 struct list_head list;
133
134 struct mii_bus *bus;
135
136 struct mutex extreg_lock;
137
138 int page;
139
140 struct ptp_clock_info caps;
141
142 struct mutex clock_lock;
143
144 struct dp83640_private *chosen;
145
146 struct list_head phylist;
147
148 struct ptp_clock *ptp_clock;
149};
150
151
152
153enum {
154 CALIBRATE_GPIO,
155 PEROUT_GPIO,
156 EXTTS0_GPIO,
157 EXTTS1_GPIO,
158 EXTTS2_GPIO,
159 EXTTS3_GPIO,
160 EXTTS4_GPIO,
161 EXTTS5_GPIO,
162 GPIO_TABLE_SIZE
163};
164
165static int chosen_phy = -1;
166static ushort gpio_tab[GPIO_TABLE_SIZE] = {
167 1, 2, 3, 4, 8, 9, 10, 11
168};
169
170module_param(chosen_phy, int, 0444);
171module_param_array(gpio_tab, ushort, NULL, 0444);
172
173MODULE_PARM_DESC(chosen_phy, \
174 "The address of the PHY to use for the ancillary clock features");
175MODULE_PARM_DESC(gpio_tab, \
176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
177
178static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
179{
180 int i, index;
181
182 for (i = 0; i < DP83640_N_PINS; i++) {
183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
184 pd[i].index = i;
185 }
186
187 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
190 return;
191 }
192 }
193
194 index = gpio_tab[CALIBRATE_GPIO] - 1;
195 pd[index].func = PTP_PF_PHYSYNC;
196 pd[index].chan = 0;
197
198 index = gpio_tab[PEROUT_GPIO] - 1;
199 pd[index].func = PTP_PF_PEROUT;
200 pd[index].chan = 0;
201
202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
203 index = gpio_tab[i] - 1;
204 pd[index].func = PTP_PF_EXTTS;
205 pd[index].chan = i - EXTTS0_GPIO;
206 }
207}
208
209
210static LIST_HEAD(phyter_clocks);
211static DEFINE_MUTEX(phyter_clocks_lock);
212
213static void rx_timestamp_work(struct work_struct *work);
214
215
216
217#define BROADCAST_ADDR 31
218
219static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
220 u16 val)
221{
222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
223}
224
225
226static int ext_read(struct phy_device *phydev, int page, u32 regnum)
227{
228 struct dp83640_private *dp83640 = phydev->priv;
229 int val;
230
231 if (dp83640->clock->page != page) {
232 broadcast_write(phydev, PAGESEL, page);
233 dp83640->clock->page = page;
234 }
235 val = phy_read(phydev, regnum);
236
237 return val;
238}
239
240
241static void ext_write(int broadcast, struct phy_device *phydev,
242 int page, u32 regnum, u16 val)
243{
244 struct dp83640_private *dp83640 = phydev->priv;
245
246 if (dp83640->clock->page != page) {
247 broadcast_write(phydev, PAGESEL, page);
248 dp83640->clock->page = page;
249 }
250 if (broadcast)
251 broadcast_write(phydev, regnum, val);
252 else
253 phy_write(phydev, regnum, val);
254}
255
256
257static int tdr_write(int bc, struct phy_device *dev,
258 const struct timespec64 *ts, u16 cmd)
259{
260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);
261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);
262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff);
263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);
264
265 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
266
267 return 0;
268}
269
270
271
272static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
273{
274 u32 sec;
275
276 sec = p->sec_lo;
277 sec |= p->sec_hi << 16;
278
279 rxts->ns = p->ns_lo;
280 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
281 rxts->ns += ((u64)sec) * 1000000000ULL;
282 rxts->seqid = p->seqid;
283 rxts->msgtype = (p->msgtype >> 12) & 0xf;
284 rxts->hash = p->msgtype & 0x0fff;
285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
286}
287
288static u64 phy2txts(struct phy_txts *p)
289{
290 u64 ns;
291 u32 sec;
292
293 sec = p->sec_lo;
294 sec |= p->sec_hi << 16;
295
296 ns = p->ns_lo;
297 ns |= (p->ns_hi & 0x3fff) << 16;
298 ns += ((u64)sec) * 1000000000ULL;
299
300 return ns;
301}
302
303static int periodic_output(struct dp83640_clock *clock,
304 struct ptp_clock_request *clkreq, bool on,
305 int trigger)
306{
307 struct dp83640_private *dp83640 = clock->chosen;
308 struct phy_device *phydev = dp83640->phydev;
309 u32 sec, nsec, pwidth;
310 u16 gpio, ptp_trig, val;
311
312 if (on) {
313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
314 trigger);
315 if (gpio < 1)
316 return -EINVAL;
317 } else {
318 gpio = 0;
319 }
320
321 ptp_trig = TRIG_WR |
322 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
323 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
324 TRIG_PER |
325 TRIG_PULSE;
326
327 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
328
329 if (!on) {
330 val |= TRIG_DIS;
331 mutex_lock(&clock->extreg_lock);
332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
333 ext_write(0, phydev, PAGE4, PTP_CTL, val);
334 mutex_unlock(&clock->extreg_lock);
335 return 0;
336 }
337
338 sec = clkreq->perout.start.sec;
339 nsec = clkreq->perout.start.nsec;
340 pwidth = clkreq->perout.period.sec * 1000000000UL;
341 pwidth += clkreq->perout.period.nsec;
342 pwidth /= 2;
343
344 mutex_lock(&clock->extreg_lock);
345
346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
347
348
349 val |= TRIG_LOAD;
350 ext_write(0, phydev, PAGE4, PTP_CTL, val);
351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);
352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);
353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);
354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);
355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
357
358 if (trigger < 2) {
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
361 }
362
363
364 val &= ~TRIG_LOAD;
365 val |= TRIG_EN;
366 ext_write(0, phydev, PAGE4, PTP_CTL, val);
367
368 mutex_unlock(&clock->extreg_lock);
369 return 0;
370}
371
372
373
374static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
375{
376 struct dp83640_clock *clock =
377 container_of(ptp, struct dp83640_clock, caps);
378 struct phy_device *phydev = clock->chosen->phydev;
379 u64 rate;
380 int neg_adj = 0;
381 u16 hi, lo;
382
383 if (scaled_ppm < 0) {
384 neg_adj = 1;
385 scaled_ppm = -scaled_ppm;
386 }
387 rate = scaled_ppm;
388 rate <<= 13;
389 rate = div_u64(rate, 15625);
390
391 hi = (rate >> 16) & PTP_RATE_HI_MASK;
392 if (neg_adj)
393 hi |= PTP_RATE_DIR;
394
395 lo = rate & 0xffff;
396
397 mutex_lock(&clock->extreg_lock);
398
399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
401
402 mutex_unlock(&clock->extreg_lock);
403
404 return 0;
405}
406
407static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
408{
409 struct dp83640_clock *clock =
410 container_of(ptp, struct dp83640_clock, caps);
411 struct phy_device *phydev = clock->chosen->phydev;
412 struct timespec64 ts;
413 int err;
414
415 delta += ADJTIME_FIX;
416
417 ts = ns_to_timespec64(delta);
418
419 mutex_lock(&clock->extreg_lock);
420
421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
422
423 mutex_unlock(&clock->extreg_lock);
424
425 return err;
426}
427
428static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
429 struct timespec64 *ts)
430{
431 struct dp83640_clock *clock =
432 container_of(ptp, struct dp83640_clock, caps);
433 struct phy_device *phydev = clock->chosen->phydev;
434 unsigned int val[4];
435
436 mutex_lock(&clock->extreg_lock);
437
438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
439
440 val[0] = ext_read(phydev, PAGE4, PTP_TDR);
441 val[1] = ext_read(phydev, PAGE4, PTP_TDR);
442 val[2] = ext_read(phydev, PAGE4, PTP_TDR);
443 val[3] = ext_read(phydev, PAGE4, PTP_TDR);
444
445 mutex_unlock(&clock->extreg_lock);
446
447 ts->tv_nsec = val[0] | (val[1] << 16);
448 ts->tv_sec = val[2] | (val[3] << 16);
449
450 return 0;
451}
452
453static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
454 const struct timespec64 *ts)
455{
456 struct dp83640_clock *clock =
457 container_of(ptp, struct dp83640_clock, caps);
458 struct phy_device *phydev = clock->chosen->phydev;
459 int err;
460
461 mutex_lock(&clock->extreg_lock);
462
463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
464
465 mutex_unlock(&clock->extreg_lock);
466
467 return err;
468}
469
470static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
471 struct ptp_clock_request *rq, int on)
472{
473 struct dp83640_clock *clock =
474 container_of(ptp, struct dp83640_clock, caps);
475 struct phy_device *phydev = clock->chosen->phydev;
476 unsigned int index;
477 u16 evnt, event_num, gpio_num;
478
479 switch (rq->type) {
480 case PTP_CLK_REQ_EXTTS:
481
482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
483 PTP_RISING_EDGE |
484 PTP_FALLING_EDGE |
485 PTP_STRICT_FLAGS))
486 return -EOPNOTSUPP;
487
488
489 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
490 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
492 return -EOPNOTSUPP;
493
494 index = rq->extts.index;
495 if (index >= N_EXT_TS)
496 return -EINVAL;
497 event_num = EXT_EVENT + index;
498 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
499 if (on) {
500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
501 PTP_PF_EXTTS, index);
502 if (gpio_num < 1)
503 return -EINVAL;
504 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
505 if (rq->extts.flags & PTP_FALLING_EDGE)
506 evnt |= EVNT_FALL;
507 else
508 evnt |= EVNT_RISE;
509 }
510 mutex_lock(&clock->extreg_lock);
511 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
512 mutex_unlock(&clock->extreg_lock);
513 return 0;
514
515 case PTP_CLK_REQ_PEROUT:
516
517 if (rq->perout.flags)
518 return -EOPNOTSUPP;
519 if (rq->perout.index >= N_PER_OUT)
520 return -EINVAL;
521 return periodic_output(clock, rq, on, rq->perout.index);
522
523 default:
524 break;
525 }
526
527 return -EOPNOTSUPP;
528}
529
530static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
531 enum ptp_pin_function func, unsigned int chan)
532{
533 struct dp83640_clock *clock =
534 container_of(ptp, struct dp83640_clock, caps);
535
536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
537 !list_empty(&clock->phylist))
538 return 1;
539
540 if (func == PTP_PF_PHYSYNC)
541 return 1;
542
543 return 0;
544}
545
546static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
547static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
548
549static void enable_status_frames(struct phy_device *phydev, bool on)
550{
551 struct dp83640_private *dp83640 = phydev->priv;
552 struct dp83640_clock *clock = dp83640->clock;
553 u16 cfg0 = 0, ver;
554
555 if (on)
556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
557
558 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
559
560 mutex_lock(&clock->extreg_lock);
561
562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
563 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
564
565 mutex_unlock(&clock->extreg_lock);
566
567 if (!phydev->attached_dev) {
568 phydev_warn(phydev,
569 "expected to find an attached netdevice\n");
570 return;
571 }
572
573 if (on) {
574 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
575 phydev_warn(phydev, "failed to add mc address\n");
576 } else {
577 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
578 phydev_warn(phydev, "failed to delete mc address\n");
579 }
580}
581
582static bool is_status_frame(struct sk_buff *skb, int type)
583{
584 struct ethhdr *h = eth_hdr(skb);
585
586 if (PTP_CLASS_V2_L2 == type &&
587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
588 return true;
589 else
590 return false;
591}
592
593static int expired(struct rxts *rxts)
594{
595 return time_after(jiffies, rxts->tmo);
596}
597
598
599static void prune_rx_ts(struct dp83640_private *dp83640)
600{
601 struct list_head *this, *next;
602 struct rxts *rxts;
603
604 list_for_each_safe(this, next, &dp83640->rxts) {
605 rxts = list_entry(this, struct rxts, list);
606 if (expired(rxts)) {
607 list_del_init(&rxts->list);
608 list_add(&rxts->list, &dp83640->rxpool);
609 }
610 }
611}
612
613
614
615static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
616{
617 int val;
618 phy_write(phydev, PAGESEL, 0);
619 val = phy_read(phydev, PHYCR2);
620 if (on)
621 val |= BC_WRITE;
622 else
623 val &= ~BC_WRITE;
624 phy_write(phydev, PHYCR2, val);
625 phy_write(phydev, PAGESEL, init_page);
626}
627
628static void recalibrate(struct dp83640_clock *clock)
629{
630 s64 now, diff;
631 struct phy_txts event_ts;
632 struct timespec64 ts;
633 struct list_head *this;
634 struct dp83640_private *tmp;
635 struct phy_device *master = clock->chosen->phydev;
636 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
637
638 trigger = CAL_TRIGGER;
639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
640 if (cal_gpio < 1) {
641 pr_err("PHY calibration pin not available - PHY is not calibrated.");
642 return;
643 }
644
645 mutex_lock(&clock->extreg_lock);
646
647
648
649
650 list_for_each(this, &clock->phylist) {
651 tmp = list_entry(this, struct dp83640_private, list);
652 enable_broadcast(tmp->phydev, clock->page, 1);
653 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
654 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
655 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
656 }
657 enable_broadcast(master, clock->page, 1);
658 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
659 ext_write(0, master, PAGE5, PSF_CFG0, 0);
660 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
661
662
663
664
665 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
666 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
667 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
668
669 list_for_each(this, &clock->phylist) {
670 tmp = list_entry(this, struct dp83640_private, list);
671 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
672 }
673 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
674
675
676
677
678 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
679 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
680 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
681 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
682
683
684 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
685 val |= TRIG_LOAD;
686 ext_write(0, master, PAGE4, PTP_CTL, val);
687
688
689 val &= ~TRIG_LOAD;
690 val |= TRIG_EN;
691 ext_write(0, master, PAGE4, PTP_CTL, val);
692
693
694 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
695 val |= TRIG_DIS;
696 ext_write(0, master, PAGE4, PTP_CTL, val);
697
698
699
700
701 val = ext_read(master, PAGE4, PTP_STS);
702 phydev_info(master, "master PTP_STS 0x%04hx\n", val);
703 val = ext_read(master, PAGE4, PTP_ESTS);
704 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
705 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
706 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
707 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
708 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
709 now = phy2txts(&event_ts);
710
711 list_for_each(this, &clock->phylist) {
712 tmp = list_entry(this, struct dp83640_private, list);
713 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
714 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
715 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
716 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
717 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
718 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
719 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
720 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
721 diff = now - (s64) phy2txts(&event_ts);
722 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
723 diff);
724 diff += ADJTIME_FIX;
725 ts = ns_to_timespec64(diff);
726 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
727 }
728
729
730
731
732 list_for_each(this, &clock->phylist) {
733 tmp = list_entry(this, struct dp83640_private, list);
734 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
735 }
736 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
737
738 mutex_unlock(&clock->extreg_lock);
739}
740
741
742
743static inline u16 exts_chan_to_edata(int ch)
744{
745 return 1 << ((ch + EXT_EVENT) * 2);
746}
747
748static int decode_evnt(struct dp83640_private *dp83640,
749 void *data, int len, u16 ests)
750{
751 struct phy_txts *phy_txts;
752 struct ptp_clock_event event;
753 int i, parsed;
754 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
755 u16 ext_status = 0;
756
757
758 if (ests & MULT_EVNT)
759 parsed = (words + 2) * sizeof(u16);
760 else
761 parsed = (words + 1) * sizeof(u16);
762
763
764 if (len < parsed)
765 return len;
766
767 if (ests & MULT_EVNT) {
768 ext_status = *(u16 *) data;
769 data += sizeof(ext_status);
770 }
771
772 phy_txts = data;
773
774 switch (words) {
775 case 3:
776 dp83640->edata.sec_hi = phy_txts->sec_hi;
777
778 case 2:
779 dp83640->edata.sec_lo = phy_txts->sec_lo;
780
781 case 1:
782 dp83640->edata.ns_hi = phy_txts->ns_hi;
783
784 case 0:
785 dp83640->edata.ns_lo = phy_txts->ns_lo;
786 }
787
788 if (!ext_status) {
789 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
790 ext_status = exts_chan_to_edata(i);
791 }
792
793 event.type = PTP_CLOCK_EXTTS;
794 event.timestamp = phy2txts(&dp83640->edata);
795
796
797 event.timestamp -= 35;
798
799 for (i = 0; i < N_EXT_TS; i++) {
800 if (ext_status & exts_chan_to_edata(i)) {
801 event.index = i;
802 ptp_clock_event(dp83640->clock->ptp_clock, &event);
803 }
804 }
805
806 return parsed;
807}
808
809#define DP83640_PACKET_HASH_OFFSET 20
810#define DP83640_PACKET_HASH_LEN 10
811
812static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
813{
814 unsigned int offset = 0;
815 u8 *msgtype, *data = skb_mac_header(skb);
816 __be16 *seqid;
817 u16 hash;
818
819
820
821 if (type & PTP_CLASS_VLAN)
822 offset += VLAN_HLEN;
823
824 switch (type & PTP_CLASS_PMASK) {
825 case PTP_CLASS_IPV4:
826 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
827 break;
828 case PTP_CLASS_IPV6:
829 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
830 break;
831 case PTP_CLASS_L2:
832 offset += ETH_HLEN;
833 break;
834 default:
835 return 0;
836 }
837
838 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
839 return 0;
840
841 if (unlikely(type & PTP_CLASS_V1))
842 msgtype = data + offset + OFF_PTP_CONTROL;
843 else
844 msgtype = data + offset;
845 if (rxts->msgtype != (*msgtype & 0xf))
846 return 0;
847
848 seqid = (__be16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
849 if (rxts->seqid != ntohs(*seqid))
850 return 0;
851
852 hash = ether_crc(DP83640_PACKET_HASH_LEN,
853 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
854 if (rxts->hash != hash)
855 return 0;
856
857 return 1;
858}
859
860static void decode_rxts(struct dp83640_private *dp83640,
861 struct phy_rxts *phy_rxts)
862{
863 struct rxts *rxts;
864 struct skb_shared_hwtstamps *shhwtstamps = NULL;
865 struct sk_buff *skb;
866 unsigned long flags;
867 u8 overflow;
868
869 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
870 if (overflow)
871 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
872
873 spin_lock_irqsave(&dp83640->rx_lock, flags);
874
875 prune_rx_ts(dp83640);
876
877 if (list_empty(&dp83640->rxpool)) {
878 pr_debug("rx timestamp pool is empty\n");
879 goto out;
880 }
881 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
882 list_del_init(&rxts->list);
883 phy2rxts(phy_rxts, rxts);
884
885 spin_lock(&dp83640->rx_queue.lock);
886 skb_queue_walk(&dp83640->rx_queue, skb) {
887 struct dp83640_skb_info *skb_info;
888
889 skb_info = (struct dp83640_skb_info *)skb->cb;
890 if (match(skb, skb_info->ptp_type, rxts)) {
891 __skb_unlink(skb, &dp83640->rx_queue);
892 shhwtstamps = skb_hwtstamps(skb);
893 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
894 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
895 list_add(&rxts->list, &dp83640->rxpool);
896 break;
897 }
898 }
899 spin_unlock(&dp83640->rx_queue.lock);
900
901 if (!shhwtstamps)
902 list_add_tail(&rxts->list, &dp83640->rxts);
903out:
904 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
905
906 if (shhwtstamps)
907 netif_rx_ni(skb);
908}
909
910static void decode_txts(struct dp83640_private *dp83640,
911 struct phy_txts *phy_txts)
912{
913 struct skb_shared_hwtstamps shhwtstamps;
914 struct dp83640_skb_info *skb_info;
915 struct sk_buff *skb;
916 u8 overflow;
917 u64 ns;
918
919
920again:
921 skb = skb_dequeue(&dp83640->tx_queue);
922 if (!skb) {
923 pr_debug("have timestamp but tx_queue empty\n");
924 return;
925 }
926
927 overflow = (phy_txts->ns_hi >> 14) & 0x3;
928 if (overflow) {
929 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
930 while (skb) {
931 kfree_skb(skb);
932 skb = skb_dequeue(&dp83640->tx_queue);
933 }
934 return;
935 }
936 skb_info = (struct dp83640_skb_info *)skb->cb;
937 if (time_after(jiffies, skb_info->tmo)) {
938 kfree_skb(skb);
939 goto again;
940 }
941
942 ns = phy2txts(phy_txts);
943 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
944 shhwtstamps.hwtstamp = ns_to_ktime(ns);
945 skb_complete_tx_timestamp(skb, &shhwtstamps);
946}
947
948static void decode_status_frame(struct dp83640_private *dp83640,
949 struct sk_buff *skb)
950{
951 struct phy_rxts *phy_rxts;
952 struct phy_txts *phy_txts;
953 u8 *ptr;
954 int len, size;
955 u16 ests, type;
956
957 ptr = skb->data + 2;
958
959 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
960
961 type = *(u16 *)ptr;
962 ests = type & 0x0fff;
963 type = type & 0xf000;
964 len -= sizeof(type);
965 ptr += sizeof(type);
966
967 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
968
969 phy_rxts = (struct phy_rxts *) ptr;
970 decode_rxts(dp83640, phy_rxts);
971 size = sizeof(*phy_rxts);
972
973 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
974
975 phy_txts = (struct phy_txts *) ptr;
976 decode_txts(dp83640, phy_txts);
977 size = sizeof(*phy_txts);
978
979 } else if (PSF_EVNT == type) {
980
981 size = decode_evnt(dp83640, ptr, len, ests);
982
983 } else {
984 size = 0;
985 break;
986 }
987 ptr += size;
988 }
989}
990
991static int is_sync(struct sk_buff *skb, int type)
992{
993 u8 *data = skb->data, *msgtype;
994 unsigned int offset = 0;
995
996 if (type & PTP_CLASS_VLAN)
997 offset += VLAN_HLEN;
998
999 switch (type & PTP_CLASS_PMASK) {
1000 case PTP_CLASS_IPV4:
1001 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
1002 break;
1003 case PTP_CLASS_IPV6:
1004 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
1005 break;
1006 case PTP_CLASS_L2:
1007 offset += ETH_HLEN;
1008 break;
1009 default:
1010 return 0;
1011 }
1012
1013 if (type & PTP_CLASS_V1)
1014 offset += OFF_PTP_CONTROL;
1015
1016 if (skb->len < offset + 1)
1017 return 0;
1018
1019 msgtype = data + offset;
1020
1021 return (*msgtype & 0xf) == 0;
1022}
1023
1024static void dp83640_free_clocks(void)
1025{
1026 struct dp83640_clock *clock;
1027 struct list_head *this, *next;
1028
1029 mutex_lock(&phyter_clocks_lock);
1030
1031 list_for_each_safe(this, next, &phyter_clocks) {
1032 clock = list_entry(this, struct dp83640_clock, list);
1033 if (!list_empty(&clock->phylist)) {
1034 pr_warn("phy list non-empty while unloading\n");
1035 BUG();
1036 }
1037 list_del(&clock->list);
1038 mutex_destroy(&clock->extreg_lock);
1039 mutex_destroy(&clock->clock_lock);
1040 put_device(&clock->bus->dev);
1041 kfree(clock->caps.pin_config);
1042 kfree(clock);
1043 }
1044
1045 mutex_unlock(&phyter_clocks_lock);
1046}
1047
1048static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1049{
1050 INIT_LIST_HEAD(&clock->list);
1051 clock->bus = bus;
1052 mutex_init(&clock->extreg_lock);
1053 mutex_init(&clock->clock_lock);
1054 INIT_LIST_HEAD(&clock->phylist);
1055 clock->caps.owner = THIS_MODULE;
1056 sprintf(clock->caps.name, "dp83640 timer");
1057 clock->caps.max_adj = 1953124;
1058 clock->caps.n_alarm = 0;
1059 clock->caps.n_ext_ts = N_EXT_TS;
1060 clock->caps.n_per_out = N_PER_OUT;
1061 clock->caps.n_pins = DP83640_N_PINS;
1062 clock->caps.pps = 0;
1063 clock->caps.adjfine = ptp_dp83640_adjfine;
1064 clock->caps.adjtime = ptp_dp83640_adjtime;
1065 clock->caps.gettime64 = ptp_dp83640_gettime;
1066 clock->caps.settime64 = ptp_dp83640_settime;
1067 clock->caps.enable = ptp_dp83640_enable;
1068 clock->caps.verify = ptp_dp83640_verify;
1069
1070
1071
1072 dp83640_gpio_defaults(clock->caps.pin_config);
1073
1074
1075
1076 get_device(&bus->dev);
1077}
1078
1079static int choose_this_phy(struct dp83640_clock *clock,
1080 struct phy_device *phydev)
1081{
1082 if (chosen_phy == -1 && !clock->chosen)
1083 return 1;
1084
1085 if (chosen_phy == phydev->mdio.addr)
1086 return 1;
1087
1088 return 0;
1089}
1090
1091static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1092{
1093 if (clock)
1094 mutex_lock(&clock->clock_lock);
1095 return clock;
1096}
1097
1098
1099
1100
1101
1102static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1103{
1104 struct dp83640_clock *clock = NULL, *tmp;
1105 struct list_head *this;
1106
1107 mutex_lock(&phyter_clocks_lock);
1108
1109 list_for_each(this, &phyter_clocks) {
1110 tmp = list_entry(this, struct dp83640_clock, list);
1111 if (tmp->bus == bus) {
1112 clock = tmp;
1113 break;
1114 }
1115 }
1116 if (clock)
1117 goto out;
1118
1119 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1120 if (!clock)
1121 goto out;
1122
1123 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1124 sizeof(struct ptp_pin_desc),
1125 GFP_KERNEL);
1126 if (!clock->caps.pin_config) {
1127 kfree(clock);
1128 clock = NULL;
1129 goto out;
1130 }
1131 dp83640_clock_init(clock, bus);
1132 list_add_tail(&clock->list, &phyter_clocks);
1133out:
1134 mutex_unlock(&phyter_clocks_lock);
1135
1136 return dp83640_clock_get(clock);
1137}
1138
1139static void dp83640_clock_put(struct dp83640_clock *clock)
1140{
1141 mutex_unlock(&clock->clock_lock);
1142}
1143
1144static int dp83640_soft_reset(struct phy_device *phydev)
1145{
1146 int ret;
1147
1148 ret = genphy_soft_reset(phydev);
1149 if (ret < 0)
1150 return ret;
1151
1152
1153
1154
1155
1156 udelay(10);
1157
1158 return 0;
1159}
1160
1161static int dp83640_config_init(struct phy_device *phydev)
1162{
1163 struct dp83640_private *dp83640 = phydev->priv;
1164 struct dp83640_clock *clock = dp83640->clock;
1165
1166 if (clock->chosen && !list_empty(&clock->phylist))
1167 recalibrate(clock);
1168 else {
1169 mutex_lock(&clock->extreg_lock);
1170 enable_broadcast(phydev, clock->page, 1);
1171 mutex_unlock(&clock->extreg_lock);
1172 }
1173
1174 enable_status_frames(phydev, true);
1175
1176 mutex_lock(&clock->extreg_lock);
1177 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1178 mutex_unlock(&clock->extreg_lock);
1179
1180 return 0;
1181}
1182
1183static int dp83640_ack_interrupt(struct phy_device *phydev)
1184{
1185 int err = phy_read(phydev, MII_DP83640_MISR);
1186
1187 if (err < 0)
1188 return err;
1189
1190 return 0;
1191}
1192
1193static int dp83640_config_intr(struct phy_device *phydev)
1194{
1195 int micr;
1196 int misr;
1197 int err;
1198
1199 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1200 err = dp83640_ack_interrupt(phydev);
1201 if (err)
1202 return err;
1203
1204 misr = phy_read(phydev, MII_DP83640_MISR);
1205 if (misr < 0)
1206 return misr;
1207 misr |=
1208 (MII_DP83640_MISR_ANC_INT_EN |
1209 MII_DP83640_MISR_DUP_INT_EN |
1210 MII_DP83640_MISR_SPD_INT_EN |
1211 MII_DP83640_MISR_LINK_INT_EN);
1212 err = phy_write(phydev, MII_DP83640_MISR, misr);
1213 if (err < 0)
1214 return err;
1215
1216 micr = phy_read(phydev, MII_DP83640_MICR);
1217 if (micr < 0)
1218 return micr;
1219 micr |=
1220 (MII_DP83640_MICR_OE |
1221 MII_DP83640_MICR_IE);
1222 return phy_write(phydev, MII_DP83640_MICR, micr);
1223 } else {
1224 micr = phy_read(phydev, MII_DP83640_MICR);
1225 if (micr < 0)
1226 return micr;
1227 micr &=
1228 ~(MII_DP83640_MICR_OE |
1229 MII_DP83640_MICR_IE);
1230 err = phy_write(phydev, MII_DP83640_MICR, micr);
1231 if (err < 0)
1232 return err;
1233
1234 misr = phy_read(phydev, MII_DP83640_MISR);
1235 if (misr < 0)
1236 return misr;
1237 misr &=
1238 ~(MII_DP83640_MISR_ANC_INT_EN |
1239 MII_DP83640_MISR_DUP_INT_EN |
1240 MII_DP83640_MISR_SPD_INT_EN |
1241 MII_DP83640_MISR_LINK_INT_EN);
1242 err = phy_write(phydev, MII_DP83640_MISR, misr);
1243 if (err)
1244 return err;
1245
1246 return dp83640_ack_interrupt(phydev);
1247 }
1248}
1249
1250static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)
1251{
1252 int irq_status;
1253
1254 irq_status = phy_read(phydev, MII_DP83640_MISR);
1255 if (irq_status < 0) {
1256 phy_error(phydev);
1257 return IRQ_NONE;
1258 }
1259
1260 if (!(irq_status & MII_DP83640_MISR_INT_MASK))
1261 return IRQ_NONE;
1262
1263 phy_trigger_machine(phydev);
1264
1265 return IRQ_HANDLED;
1266}
1267
1268static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1269{
1270 struct dp83640_private *dp83640 =
1271 container_of(mii_ts, struct dp83640_private, mii_ts);
1272 struct hwtstamp_config cfg;
1273 u16 txcfg0, rxcfg0;
1274
1275 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1276 return -EFAULT;
1277
1278 if (cfg.flags)
1279 return -EINVAL;
1280
1281 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1282 return -ERANGE;
1283
1284 dp83640->hwts_tx_en = cfg.tx_type;
1285
1286 switch (cfg.rx_filter) {
1287 case HWTSTAMP_FILTER_NONE:
1288 dp83640->hwts_rx_en = 0;
1289 dp83640->layer = 0;
1290 dp83640->version = 0;
1291 break;
1292 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1293 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1294 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1295 dp83640->hwts_rx_en = 1;
1296 dp83640->layer = PTP_CLASS_L4;
1297 dp83640->version = PTP_CLASS_V1;
1298 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1299 break;
1300 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1301 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1302 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1303 dp83640->hwts_rx_en = 1;
1304 dp83640->layer = PTP_CLASS_L4;
1305 dp83640->version = PTP_CLASS_V2;
1306 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1307 break;
1308 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1309 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1310 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1311 dp83640->hwts_rx_en = 1;
1312 dp83640->layer = PTP_CLASS_L2;
1313 dp83640->version = PTP_CLASS_V2;
1314 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1315 break;
1316 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1317 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1318 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1319 dp83640->hwts_rx_en = 1;
1320 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1321 dp83640->version = PTP_CLASS_V2;
1322 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1323 break;
1324 default:
1325 return -ERANGE;
1326 }
1327
1328 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1329 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1330
1331 if (dp83640->layer & PTP_CLASS_L2) {
1332 txcfg0 |= TX_L2_EN;
1333 rxcfg0 |= RX_L2_EN;
1334 }
1335 if (dp83640->layer & PTP_CLASS_L4) {
1336 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1337 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1338 }
1339
1340 if (dp83640->hwts_tx_en)
1341 txcfg0 |= TX_TS_EN;
1342
1343 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1344 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1345
1346 if (dp83640->hwts_rx_en)
1347 rxcfg0 |= RX_TS_EN;
1348
1349 mutex_lock(&dp83640->clock->extreg_lock);
1350
1351 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1352 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1353
1354 mutex_unlock(&dp83640->clock->extreg_lock);
1355
1356 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1357}
1358
1359static void rx_timestamp_work(struct work_struct *work)
1360{
1361 struct dp83640_private *dp83640 =
1362 container_of(work, struct dp83640_private, ts_work.work);
1363 struct sk_buff *skb;
1364
1365
1366 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1367 struct dp83640_skb_info *skb_info;
1368
1369 skb_info = (struct dp83640_skb_info *)skb->cb;
1370 if (!time_after(jiffies, skb_info->tmo)) {
1371 skb_queue_head(&dp83640->rx_queue, skb);
1372 break;
1373 }
1374
1375 netif_rx_ni(skb);
1376 }
1377
1378 if (!skb_queue_empty(&dp83640->rx_queue))
1379 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1380}
1381
1382static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,
1383 struct sk_buff *skb, int type)
1384{
1385 struct dp83640_private *dp83640 =
1386 container_of(mii_ts, struct dp83640_private, mii_ts);
1387 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1388 struct list_head *this, *next;
1389 struct rxts *rxts;
1390 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1391 unsigned long flags;
1392
1393 if (is_status_frame(skb, type)) {
1394 decode_status_frame(dp83640, skb);
1395 kfree_skb(skb);
1396 return true;
1397 }
1398
1399 if (!dp83640->hwts_rx_en)
1400 return false;
1401
1402 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1403 return false;
1404
1405 spin_lock_irqsave(&dp83640->rx_lock, flags);
1406 prune_rx_ts(dp83640);
1407 list_for_each_safe(this, next, &dp83640->rxts) {
1408 rxts = list_entry(this, struct rxts, list);
1409 if (match(skb, type, rxts)) {
1410 shhwtstamps = skb_hwtstamps(skb);
1411 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1412 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1413 list_del_init(&rxts->list);
1414 list_add(&rxts->list, &dp83640->rxpool);
1415 break;
1416 }
1417 }
1418 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1419
1420 if (!shhwtstamps) {
1421 skb_info->ptp_type = type;
1422 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1423 skb_queue_tail(&dp83640->rx_queue, skb);
1424 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1425 } else {
1426 netif_rx_ni(skb);
1427 }
1428
1429 return true;
1430}
1431
1432static void dp83640_txtstamp(struct mii_timestamper *mii_ts,
1433 struct sk_buff *skb, int type)
1434{
1435 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1436 struct dp83640_private *dp83640 =
1437 container_of(mii_ts, struct dp83640_private, mii_ts);
1438
1439 switch (dp83640->hwts_tx_en) {
1440
1441 case HWTSTAMP_TX_ONESTEP_SYNC:
1442 if (is_sync(skb, type)) {
1443 kfree_skb(skb);
1444 return;
1445 }
1446
1447 case HWTSTAMP_TX_ON:
1448 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1449 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1450 skb_queue_tail(&dp83640->tx_queue, skb);
1451 break;
1452
1453 case HWTSTAMP_TX_OFF:
1454 default:
1455 kfree_skb(skb);
1456 break;
1457 }
1458}
1459
1460static int dp83640_ts_info(struct mii_timestamper *mii_ts,
1461 struct ethtool_ts_info *info)
1462{
1463 struct dp83640_private *dp83640 =
1464 container_of(mii_ts, struct dp83640_private, mii_ts);
1465
1466 info->so_timestamping =
1467 SOF_TIMESTAMPING_TX_HARDWARE |
1468 SOF_TIMESTAMPING_RX_HARDWARE |
1469 SOF_TIMESTAMPING_RAW_HARDWARE;
1470 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1471 info->tx_types =
1472 (1 << HWTSTAMP_TX_OFF) |
1473 (1 << HWTSTAMP_TX_ON) |
1474 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1475 info->rx_filters =
1476 (1 << HWTSTAMP_FILTER_NONE) |
1477 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1478 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1479 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1480 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1481 return 0;
1482}
1483
1484static int dp83640_probe(struct phy_device *phydev)
1485{
1486 struct dp83640_clock *clock;
1487 struct dp83640_private *dp83640;
1488 int err = -ENOMEM, i;
1489
1490 if (phydev->mdio.addr == BROADCAST_ADDR)
1491 return 0;
1492
1493 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1494 if (!clock)
1495 goto no_clock;
1496
1497 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1498 if (!dp83640)
1499 goto no_memory;
1500
1501 dp83640->phydev = phydev;
1502 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
1503 dp83640->mii_ts.txtstamp = dp83640_txtstamp;
1504 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
1505 dp83640->mii_ts.ts_info = dp83640_ts_info;
1506
1507 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1508 INIT_LIST_HEAD(&dp83640->rxts);
1509 INIT_LIST_HEAD(&dp83640->rxpool);
1510 for (i = 0; i < MAX_RXTS; i++)
1511 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1512
1513 phydev->mii_ts = &dp83640->mii_ts;
1514 phydev->priv = dp83640;
1515
1516 spin_lock_init(&dp83640->rx_lock);
1517 skb_queue_head_init(&dp83640->rx_queue);
1518 skb_queue_head_init(&dp83640->tx_queue);
1519
1520 dp83640->clock = clock;
1521
1522 if (choose_this_phy(clock, phydev)) {
1523 clock->chosen = dp83640;
1524 clock->ptp_clock = ptp_clock_register(&clock->caps,
1525 &phydev->mdio.dev);
1526 if (IS_ERR(clock->ptp_clock)) {
1527 err = PTR_ERR(clock->ptp_clock);
1528 goto no_register;
1529 }
1530 } else
1531 list_add_tail(&dp83640->list, &clock->phylist);
1532
1533 dp83640_clock_put(clock);
1534 return 0;
1535
1536no_register:
1537 clock->chosen = NULL;
1538 kfree(dp83640);
1539no_memory:
1540 dp83640_clock_put(clock);
1541no_clock:
1542 return err;
1543}
1544
1545static void dp83640_remove(struct phy_device *phydev)
1546{
1547 struct dp83640_clock *clock;
1548 struct list_head *this, *next;
1549 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1550
1551 if (phydev->mdio.addr == BROADCAST_ADDR)
1552 return;
1553
1554 phydev->mii_ts = NULL;
1555
1556 enable_status_frames(phydev, false);
1557 cancel_delayed_work_sync(&dp83640->ts_work);
1558
1559 skb_queue_purge(&dp83640->rx_queue);
1560 skb_queue_purge(&dp83640->tx_queue);
1561
1562 clock = dp83640_clock_get(dp83640->clock);
1563
1564 if (dp83640 == clock->chosen) {
1565 ptp_clock_unregister(clock->ptp_clock);
1566 clock->chosen = NULL;
1567 } else {
1568 list_for_each_safe(this, next, &clock->phylist) {
1569 tmp = list_entry(this, struct dp83640_private, list);
1570 if (tmp == dp83640) {
1571 list_del_init(&tmp->list);
1572 break;
1573 }
1574 }
1575 }
1576
1577 dp83640_clock_put(clock);
1578 kfree(dp83640);
1579}
1580
1581static struct phy_driver dp83640_driver = {
1582 .phy_id = DP83640_PHY_ID,
1583 .phy_id_mask = 0xfffffff0,
1584 .name = "NatSemi DP83640",
1585
1586 .probe = dp83640_probe,
1587 .remove = dp83640_remove,
1588 .soft_reset = dp83640_soft_reset,
1589 .config_init = dp83640_config_init,
1590 .config_intr = dp83640_config_intr,
1591 .handle_interrupt = dp83640_handle_interrupt,
1592};
1593
1594static int __init dp83640_init(void)
1595{
1596 return phy_driver_register(&dp83640_driver, THIS_MODULE);
1597}
1598
1599static void __exit dp83640_exit(void)
1600{
1601 dp83640_free_clocks();
1602 phy_driver_unregister(&dp83640_driver);
1603}
1604
1605MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1606MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1607MODULE_LICENSE("GPL");
1608
1609module_init(dp83640_init);
1610module_exit(dp83640_exit);
1611
1612static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1613 { DP83640_PHY_ID, 0xfffffff0 },
1614 { }
1615};
1616
1617MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
1618
