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30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/slab.h>
37#include <linux/dma-mapping.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/skbuff.h>
41#include <linux/netdevice.h>
42#include <linux/firmware.h>
43#include <linux/etherdevice.h>
44#include <linux/if_arp.h>
45
46#include <net/ieee80211_radiotap.h>
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl3945"
52
53#include "commands.h"
54#include "common.h"
55#include "3945.h"
56#include "iwl-spectrum.h"
57
58
59
60
61
62#define DRV_DESCRIPTION \
63"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
64
65#ifdef CONFIG_IWLEGACY_DEBUG
66#define VD "d"
67#else
68#define VD
69#endif
70
71
72
73
74
75
76#define DRV_VERSION IWLWIFI_VERSION VD "s"
77#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
78#define DRV_AUTHOR "<ilw@linux.intel.com>"
79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_VERSION(DRV_VERSION);
82MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
83MODULE_LICENSE("GPL");
84
85
86struct il_mod_params il3945_mod_params = {
87 .sw_crypto = 1,
88 .restart_fw = 1,
89 .disable_hw_scan = 1,
90
91};
92
93
94
95
96
97
98
99
100
101
102
103
104__le32
105il3945_get_antenna_flags(const struct il_priv *il)
106{
107 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
108
109 switch (il3945_mod_params.antenna) {
110 case IL_ANTENNA_DIVERSITY:
111 return 0;
112
113 case IL_ANTENNA_MAIN:
114 if (eeprom->antenna_switch_type)
115 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
117
118 case IL_ANTENNA_AUX:
119 if (eeprom->antenna_switch_type)
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
122 }
123
124
125 IL_ERR("Bad antenna selector value (0x%x)\n",
126 il3945_mod_params.antenna);
127
128 return 0;
129}
130
131static int
132il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
133 struct ieee80211_key_conf *keyconf, u8 sta_id)
134{
135 unsigned long flags;
136 __le16 key_flags = 0;
137 int ret;
138
139 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
140 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
141
142 if (sta_id == il->hw_params.bcast_id)
143 key_flags |= STA_KEY_MULTICAST_MSK;
144
145 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
146 keyconf->hw_key_idx = keyconf->keyidx;
147 key_flags &= ~STA_KEY_FLG_INVALID;
148
149 spin_lock_irqsave(&il->sta_lock, flags);
150 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
151 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
152 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
153
154 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
155
156 if ((il->stations[sta_id].sta.key.
157 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
158 il->stations[sta_id].sta.key.key_offset =
159 il_get_free_ucode_key_idx(il);
160
161
162
163 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
164 "no space for a new key");
165
166 il->stations[sta_id].sta.key.key_flags = key_flags;
167 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
168 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
169
170 D_INFO("hwcrypto: modify ucode station key info\n");
171
172 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
173
174 spin_unlock_irqrestore(&il->sta_lock, flags);
175
176 return ret;
177}
178
179static int
180il3945_set_tkip_dynamic_key_info(struct il_priv *il,
181 struct ieee80211_key_conf *keyconf, u8 sta_id)
182{
183 return -EOPNOTSUPP;
184}
185
186static int
187il3945_set_wep_dynamic_key_info(struct il_priv *il,
188 struct ieee80211_key_conf *keyconf, u8 sta_id)
189{
190 return -EOPNOTSUPP;
191}
192
193static int
194il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
195{
196 unsigned long flags;
197 struct il_addsta_cmd sta_cmd;
198
199 spin_lock_irqsave(&il->sta_lock, flags);
200 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
201 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
202 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
203 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
204 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
205 memcpy(&sta_cmd, &il->stations[sta_id].sta,
206 sizeof(struct il_addsta_cmd));
207 spin_unlock_irqrestore(&il->sta_lock, flags);
208
209 D_INFO("hwcrypto: clear ucode station key info\n");
210 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
211}
212
213static int
214il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
215 u8 sta_id)
216{
217 int ret = 0;
218
219 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
220
221 switch (keyconf->cipher) {
222 case WLAN_CIPHER_SUITE_CCMP:
223 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
224 break;
225 case WLAN_CIPHER_SUITE_TKIP:
226 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
227 break;
228 case WLAN_CIPHER_SUITE_WEP40:
229 case WLAN_CIPHER_SUITE_WEP104:
230 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
231 break;
232 default:
233 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
234 ret = -EINVAL;
235 }
236
237 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
238 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
239
240 return ret;
241}
242
243static int
244il3945_remove_static_key(struct il_priv *il)
245{
246 int ret = -EOPNOTSUPP;
247
248 return ret;
249}
250
251static int
252il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
253{
254 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
255 key->cipher == WLAN_CIPHER_SUITE_WEP104)
256 return -EOPNOTSUPP;
257
258 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
259 return -EINVAL;
260}
261
262static void
263il3945_clear_free_frames(struct il_priv *il)
264{
265 struct list_head *element;
266
267 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
268
269 while (!list_empty(&il->free_frames)) {
270 element = il->free_frames.next;
271 list_del(element);
272 kfree(list_entry(element, struct il3945_frame, list));
273 il->frames_count--;
274 }
275
276 if (il->frames_count) {
277 IL_WARN("%d frames still in use. Did we lose one?\n",
278 il->frames_count);
279 il->frames_count = 0;
280 }
281}
282
283static struct il3945_frame *
284il3945_get_free_frame(struct il_priv *il)
285{
286 struct il3945_frame *frame;
287 struct list_head *element;
288 if (list_empty(&il->free_frames)) {
289 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
290 if (!frame) {
291 IL_ERR("Could not allocate frame!\n");
292 return NULL;
293 }
294
295 il->frames_count++;
296 return frame;
297 }
298
299 element = il->free_frames.next;
300 list_del(element);
301 return list_entry(element, struct il3945_frame, list);
302}
303
304static void
305il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
306{
307 memset(frame, 0, sizeof(*frame));
308 list_add(&frame->list, &il->free_frames);
309}
310
311unsigned int
312il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
313 int left)
314{
315
316 if (!il_is_associated(il) || !il->beacon_skb)
317 return 0;
318
319 if (il->beacon_skb->len > left)
320 return 0;
321
322 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
323
324 return il->beacon_skb->len;
325}
326
327static int
328il3945_send_beacon_cmd(struct il_priv *il)
329{
330 struct il3945_frame *frame;
331 unsigned int frame_size;
332 int rc;
333 u8 rate;
334
335 frame = il3945_get_free_frame(il);
336
337 if (!frame) {
338 IL_ERR("Could not obtain free frame buffer for beacon "
339 "command.\n");
340 return -ENOMEM;
341 }
342
343 rate = il_get_lowest_plcp(il);
344
345 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
346
347 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
348
349 il3945_free_frame(il, frame);
350
351 return rc;
352}
353
354static void
355il3945_unset_hw_params(struct il_priv *il)
356{
357 if (il->_3945.shared_virt)
358 dma_free_coherent(&il->pci_dev->dev,
359 sizeof(struct il3945_shared),
360 il->_3945.shared_virt, il->_3945.shared_phys);
361}
362
363static void
364il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
365 struct il_device_cmd *cmd,
366 struct sk_buff *skb_frag, int sta_id)
367{
368 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
369 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
370
371 tx_cmd->sec_ctl = 0;
372
373 switch (keyinfo->cipher) {
374 case WLAN_CIPHER_SUITE_CCMP:
375 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
376 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
377 D_TX("tx_cmd with AES hwcrypto\n");
378 break;
379
380 case WLAN_CIPHER_SUITE_TKIP:
381 break;
382
383 case WLAN_CIPHER_SUITE_WEP104:
384 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
385
386 case WLAN_CIPHER_SUITE_WEP40:
387 tx_cmd->sec_ctl |=
388 TX_CMD_SEC_WEP | (info->control.hw_key->
389 hw_key_idx & TX_CMD_SEC_MSK) <<
390 TX_CMD_SEC_SHIFT;
391
392 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
393
394 D_TX("Configuring packet for WEP encryption " "with key %d\n",
395 info->control.hw_key->hw_key_idx);
396 break;
397
398 default:
399 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
400 break;
401 }
402}
403
404
405
406
407static void
408il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
409 struct ieee80211_tx_info *info,
410 struct ieee80211_hdr *hdr, u8 std_id)
411{
412 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
413 __le32 tx_flags = tx_cmd->tx_flags;
414 __le16 fc = hdr->frame_control;
415
416 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
417 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
418 tx_flags |= TX_CMD_FLG_ACK_MSK;
419 if (ieee80211_is_mgmt(fc))
420 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
421 if (ieee80211_is_probe_resp(fc) &&
422 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
423 tx_flags |= TX_CMD_FLG_TSF_MSK;
424 } else {
425 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
426 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
427 }
428
429 tx_cmd->sta_id = std_id;
430 if (ieee80211_has_morefrags(fc))
431 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
432
433 if (ieee80211_is_data_qos(fc)) {
434 u8 *qc = ieee80211_get_qos_ctl(hdr);
435 tx_cmd->tid_tspec = qc[0] & 0xf;
436 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
437 } else {
438 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
439 }
440
441 il_tx_cmd_protection(il, info, fc, &tx_flags);
442
443 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
444 if (ieee80211_is_mgmt(fc)) {
445 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
446 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
447 else
448 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
449 } else {
450 tx_cmd->timeout.pm_frame_timeout = 0;
451 }
452
453 tx_cmd->driver_txop = 0;
454 tx_cmd->tx_flags = tx_flags;
455 tx_cmd->next_frame_len = 0;
456}
457
458
459
460
461static int
462il3945_tx_skb(struct il_priv *il,
463 struct ieee80211_sta *sta,
464 struct sk_buff *skb)
465{
466 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
467 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
468 struct il3945_tx_cmd *tx_cmd;
469 struct il_tx_queue *txq = NULL;
470 struct il_queue *q = NULL;
471 struct il_device_cmd *out_cmd;
472 struct il_cmd_meta *out_meta;
473 dma_addr_t phys_addr;
474 dma_addr_t txcmd_phys;
475 int txq_id = skb_get_queue_mapping(skb);
476 u16 len, idx, hdr_len;
477 u16 firstlen, secondlen;
478 u8 id;
479 u8 unicast;
480 u8 sta_id;
481 u8 tid = 0;
482 __le16 fc;
483 u8 wait_write_ptr = 0;
484 unsigned long flags;
485
486 spin_lock_irqsave(&il->lock, flags);
487 if (il_is_rfkill(il)) {
488 D_DROP("Dropping - RF KILL\n");
489 goto drop_unlock;
490 }
491
492 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
493 IL_INVALID_RATE) {
494 IL_ERR("ERROR: No TX rate available.\n");
495 goto drop_unlock;
496 }
497
498 unicast = !is_multicast_ether_addr(hdr->addr1);
499 id = 0;
500
501 fc = hdr->frame_control;
502
503#ifdef CONFIG_IWLEGACY_DEBUG
504 if (ieee80211_is_auth(fc))
505 D_TX("Sending AUTH frame\n");
506 else if (ieee80211_is_assoc_req(fc))
507 D_TX("Sending ASSOC frame\n");
508 else if (ieee80211_is_reassoc_req(fc))
509 D_TX("Sending REASSOC frame\n");
510#endif
511
512 spin_unlock_irqrestore(&il->lock, flags);
513
514 hdr_len = ieee80211_hdrlen(fc);
515
516
517 sta_id = il_sta_id_or_broadcast(il, sta);
518 if (sta_id == IL_INVALID_STATION) {
519 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
520 goto drop;
521 }
522
523 D_RATE("station Id %d\n", sta_id);
524
525 if (ieee80211_is_data_qos(fc)) {
526 u8 *qc = ieee80211_get_qos_ctl(hdr);
527 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
528 if (unlikely(tid >= MAX_TID_COUNT))
529 goto drop;
530 }
531
532
533 txq = &il->txq[txq_id];
534 q = &txq->q;
535
536 if ((il_queue_space(q) < q->high_mark))
537 goto drop;
538
539 spin_lock_irqsave(&il->lock, flags);
540
541 idx = il_get_cmd_idx(q, q->write_ptr, 0);
542
543 txq->skbs[q->write_ptr] = skb;
544
545
546 out_cmd = txq->cmd[idx];
547 out_meta = &txq->meta[idx];
548 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
549 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
550 memset(tx_cmd, 0, sizeof(*tx_cmd));
551
552
553
554
555
556
557
558 out_cmd->hdr.cmd = C_TX;
559 out_cmd->hdr.sequence =
560 cpu_to_le16((u16)
561 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
562
563
564 memcpy(tx_cmd->hdr, hdr, hdr_len);
565
566 if (info->control.hw_key)
567 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
568
569
570 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
571
572 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
573
574
575 tx_cmd->len = cpu_to_le16((u16) skb->len);
576
577 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
578 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
579
580
581
582
583
584
585
586
587
588
589 len =
590 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
591 hdr_len;
592 firstlen = (len + 3) & ~3;
593
594
595
596 txcmd_phys =
597 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
598 PCI_DMA_TODEVICE);
599 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
600 goto drop_unlock;
601
602
603
604 secondlen = skb->len - hdr_len;
605 if (secondlen > 0) {
606 phys_addr =
607 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
608 PCI_DMA_TODEVICE);
609 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
610 goto drop_unlock;
611 }
612
613
614
615 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
616 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
617 dma_unmap_len_set(out_meta, len, firstlen);
618 if (secondlen > 0)
619 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
620 U32_PAD(secondlen));
621
622 if (!ieee80211_has_morefrags(hdr->frame_control)) {
623 txq->need_update = 1;
624 } else {
625 wait_write_ptr = 1;
626 txq->need_update = 0;
627 }
628
629 il_update_stats(il, true, fc, skb->len);
630
631 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
632 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
633 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
634 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
635 ieee80211_hdrlen(fc));
636
637
638 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
639 il_txq_update_write_ptr(il, txq);
640 spin_unlock_irqrestore(&il->lock, flags);
641
642 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
643 if (wait_write_ptr) {
644 spin_lock_irqsave(&il->lock, flags);
645 txq->need_update = 1;
646 il_txq_update_write_ptr(il, txq);
647 spin_unlock_irqrestore(&il->lock, flags);
648 }
649
650 il_stop_queue(il, txq);
651 }
652
653 return 0;
654
655drop_unlock:
656 spin_unlock_irqrestore(&il->lock, flags);
657drop:
658 return -1;
659}
660
661static int
662il3945_get_measurement(struct il_priv *il,
663 struct ieee80211_measurement_params *params, u8 type)
664{
665 struct il_spectrum_cmd spectrum;
666 struct il_rx_pkt *pkt;
667 struct il_host_cmd cmd = {
668 .id = C_SPECTRUM_MEASUREMENT,
669 .data = (void *)&spectrum,
670 .flags = CMD_WANT_SKB,
671 };
672 u32 add_time = le64_to_cpu(params->start_time);
673 int rc;
674 int spectrum_resp_status;
675 int duration = le16_to_cpu(params->duration);
676
677 if (il_is_associated(il))
678 add_time =
679 il_usecs_to_beacons(il,
680 le64_to_cpu(params->start_time) -
681 il->_3945.last_tsf,
682 le16_to_cpu(il->timing.beacon_interval));
683
684 memset(&spectrum, 0, sizeof(spectrum));
685
686 spectrum.channel_count = cpu_to_le16(1);
687 spectrum.flags =
688 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
689 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
690 cmd.len = sizeof(spectrum);
691 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
692
693 if (il_is_associated(il))
694 spectrum.start_time =
695 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
696 le16_to_cpu(il->timing.beacon_interval));
697 else
698 spectrum.start_time = 0;
699
700 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
701 spectrum.channels[0].channel = params->channel;
702 spectrum.channels[0].type = type;
703 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
704 spectrum.flags |=
705 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
706 RXON_FLG_TGG_PROTECT_MSK;
707
708 rc = il_send_cmd_sync(il, &cmd);
709 if (rc)
710 return rc;
711
712 pkt = (struct il_rx_pkt *)cmd.reply_page;
713 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
714 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
715 rc = -EIO;
716 }
717
718 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
719 switch (spectrum_resp_status) {
720 case 0:
721 if (pkt->u.spectrum.id != 0xff) {
722 D_INFO("Replaced existing measurement: %d\n",
723 pkt->u.spectrum.id);
724 il->measurement_status &= ~MEASUREMENT_READY;
725 }
726 il->measurement_status |= MEASUREMENT_ACTIVE;
727 rc = 0;
728 break;
729
730 case 1:
731 rc = -EAGAIN;
732 break;
733 }
734
735 il_free_pages(il, cmd.reply_page);
736
737 return rc;
738}
739
740static void
741il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
742{
743 struct il_rx_pkt *pkt = rxb_addr(rxb);
744 struct il_alive_resp *palive;
745 struct delayed_work *pwork;
746
747 palive = &pkt->u.alive_frame;
748
749 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
750 palive->is_valid, palive->ver_type, palive->ver_subtype);
751
752 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
753 D_INFO("Initialization Alive received.\n");
754 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
755 sizeof(struct il_alive_resp));
756 pwork = &il->init_alive_start;
757 } else {
758 D_INFO("Runtime Alive received.\n");
759 memcpy(&il->card_alive, &pkt->u.alive_frame,
760 sizeof(struct il_alive_resp));
761 pwork = &il->alive_start;
762 il3945_disable_events(il);
763 }
764
765
766
767 if (palive->is_valid == UCODE_VALID_OK)
768 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
769 else
770 IL_WARN("uCode did not respond OK.\n");
771}
772
773static void
774il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
775{
776#ifdef CONFIG_IWLEGACY_DEBUG
777 struct il_rx_pkt *pkt = rxb_addr(rxb);
778#endif
779
780 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
781}
782
783static void
784il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
785{
786 struct il_rx_pkt *pkt = rxb_addr(rxb);
787 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
788#ifdef CONFIG_IWLEGACY_DEBUG
789 u8 rate = beacon->beacon_notify_hdr.rate;
790
791 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
792 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
793 beacon->beacon_notify_hdr.failure_frame,
794 le32_to_cpu(beacon->ibss_mgr_status),
795 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
796#endif
797
798 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
799
800}
801
802
803
804static void
805il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
806{
807 struct il_rx_pkt *pkt = rxb_addr(rxb);
808 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
809 unsigned long status = il->status;
810
811 IL_WARN("Card state received: HW:%s SW:%s\n",
812 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
813 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
814
815 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
816
817 if (flags & HW_CARD_DISABLED)
818 set_bit(S_RFKILL, &il->status);
819 else
820 clear_bit(S_RFKILL, &il->status);
821
822 il_scan_cancel(il);
823
824 if ((test_bit(S_RFKILL, &status) !=
825 test_bit(S_RFKILL, &il->status)))
826 wiphy_rfkill_set_hw_state(il->hw->wiphy,
827 test_bit(S_RFKILL, &il->status));
828 else
829 wake_up(&il->wait_command_queue);
830}
831
832
833
834
835
836
837
838
839
840
841static void
842il3945_setup_handlers(struct il_priv *il)
843{
844 il->handlers[N_ALIVE] = il3945_hdl_alive;
845 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
846 il->handlers[N_ERROR] = il_hdl_error;
847 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
848 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
849 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
850 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
851 il->handlers[N_BEACON] = il3945_hdl_beacon;
852
853
854
855
856
857
858 il->handlers[C_STATS] = il3945_hdl_c_stats;
859 il->handlers[N_STATS] = il3945_hdl_stats;
860
861 il_setup_rx_scan_handlers(il);
862 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
863
864
865 il3945_hw_handler_setup(il);
866}
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935static inline __le32
936il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
937{
938 return cpu_to_le32((u32) dma_addr);
939}
940
941
942
943
944
945
946
947
948
949
950
951
952static void
953il3945_rx_queue_restock(struct il_priv *il)
954{
955 struct il_rx_queue *rxq = &il->rxq;
956 struct list_head *element;
957 struct il_rx_buf *rxb;
958 unsigned long flags;
959 int write;
960
961 spin_lock_irqsave(&rxq->lock, flags);
962 write = rxq->write & ~0x7;
963 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
964
965 element = rxq->rx_free.next;
966 rxb = list_entry(element, struct il_rx_buf, list);
967 list_del(element);
968
969
970 rxq->bd[rxq->write] =
971 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
972 rxq->queue[rxq->write] = rxb;
973 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
974 rxq->free_count--;
975 }
976 spin_unlock_irqrestore(&rxq->lock, flags);
977
978
979 if (rxq->free_count <= RX_LOW_WATERMARK)
980 queue_work(il->workqueue, &il->rx_replenish);
981
982
983
984 if (rxq->write_actual != (rxq->write & ~0x7) ||
985 abs(rxq->write - rxq->read) > 7) {
986 spin_lock_irqsave(&rxq->lock, flags);
987 rxq->need_update = 1;
988 spin_unlock_irqrestore(&rxq->lock, flags);
989 il_rx_queue_update_write_ptr(il, rxq);
990 }
991}
992
993
994
995
996
997
998
999
1000
1001static void
1002il3945_rx_allocate(struct il_priv *il, gfp_t priority)
1003{
1004 struct il_rx_queue *rxq = &il->rxq;
1005 struct list_head *element;
1006 struct il_rx_buf *rxb;
1007 struct page *page;
1008 dma_addr_t page_dma;
1009 unsigned long flags;
1010 gfp_t gfp_mask = priority;
1011
1012 while (1) {
1013 spin_lock_irqsave(&rxq->lock, flags);
1014 if (list_empty(&rxq->rx_used)) {
1015 spin_unlock_irqrestore(&rxq->lock, flags);
1016 return;
1017 }
1018 spin_unlock_irqrestore(&rxq->lock, flags);
1019
1020 if (rxq->free_count > RX_LOW_WATERMARK)
1021 gfp_mask |= __GFP_NOWARN;
1022
1023 if (il->hw_params.rx_page_order > 0)
1024 gfp_mask |= __GFP_COMP;
1025
1026
1027 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1028 if (!page) {
1029 if (net_ratelimit())
1030 D_INFO("Failed to allocate SKB buffer.\n");
1031 if (rxq->free_count <= RX_LOW_WATERMARK &&
1032 net_ratelimit())
1033 IL_ERR("Failed to allocate SKB buffer with %0x."
1034 "Only %u free buffers remaining.\n",
1035 priority, rxq->free_count);
1036
1037
1038
1039 break;
1040 }
1041
1042
1043 page_dma =
1044 pci_map_page(il->pci_dev, page, 0,
1045 PAGE_SIZE << il->hw_params.rx_page_order,
1046 PCI_DMA_FROMDEVICE);
1047
1048 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1049 __free_pages(page, il->hw_params.rx_page_order);
1050 break;
1051 }
1052
1053 spin_lock_irqsave(&rxq->lock, flags);
1054
1055 if (list_empty(&rxq->rx_used)) {
1056 spin_unlock_irqrestore(&rxq->lock, flags);
1057 pci_unmap_page(il->pci_dev, page_dma,
1058 PAGE_SIZE << il->hw_params.rx_page_order,
1059 PCI_DMA_FROMDEVICE);
1060 __free_pages(page, il->hw_params.rx_page_order);
1061 return;
1062 }
1063
1064 element = rxq->rx_used.next;
1065 rxb = list_entry(element, struct il_rx_buf, list);
1066 list_del(element);
1067
1068 rxb->page = page;
1069 rxb->page_dma = page_dma;
1070 list_add_tail(&rxb->list, &rxq->rx_free);
1071 rxq->free_count++;
1072 il->alloc_rxb_page++;
1073
1074 spin_unlock_irqrestore(&rxq->lock, flags);
1075 }
1076}
1077
1078void
1079il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1080{
1081 unsigned long flags;
1082 int i;
1083 spin_lock_irqsave(&rxq->lock, flags);
1084 INIT_LIST_HEAD(&rxq->rx_free);
1085 INIT_LIST_HEAD(&rxq->rx_used);
1086
1087 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1088
1089
1090 if (rxq->pool[i].page != NULL) {
1091 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1092 PAGE_SIZE << il->hw_params.rx_page_order,
1093 PCI_DMA_FROMDEVICE);
1094 __il_free_pages(il, rxq->pool[i].page);
1095 rxq->pool[i].page = NULL;
1096 }
1097 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1098 }
1099
1100
1101
1102 rxq->read = rxq->write = 0;
1103 rxq->write_actual = 0;
1104 rxq->free_count = 0;
1105 spin_unlock_irqrestore(&rxq->lock, flags);
1106}
1107
1108void
1109il3945_rx_replenish(void *data)
1110{
1111 struct il_priv *il = data;
1112 unsigned long flags;
1113
1114 il3945_rx_allocate(il, GFP_KERNEL);
1115
1116 spin_lock_irqsave(&il->lock, flags);
1117 il3945_rx_queue_restock(il);
1118 spin_unlock_irqrestore(&il->lock, flags);
1119}
1120
1121static void
1122il3945_rx_replenish_now(struct il_priv *il)
1123{
1124 il3945_rx_allocate(il, GFP_ATOMIC);
1125
1126 il3945_rx_queue_restock(il);
1127}
1128
1129
1130
1131
1132
1133
1134static void
1135il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1136{
1137 int i;
1138 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1139 if (rxq->pool[i].page != NULL) {
1140 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1141 PAGE_SIZE << il->hw_params.rx_page_order,
1142 PCI_DMA_FROMDEVICE);
1143 __il_free_pages(il, rxq->pool[i].page);
1144 rxq->pool[i].page = NULL;
1145 }
1146 }
1147
1148 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1149 rxq->bd_dma);
1150 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1151 rxq->rb_stts, rxq->rb_stts_dma);
1152 rxq->bd = NULL;
1153 rxq->rb_stts = NULL;
1154}
1155
1156
1157static u8 ratio2dB[100] = {
1158
1159 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
1160 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
1161 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
1162 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
1163 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
1164 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
1165 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
1166 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
1167 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
1168 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
1169};
1170
1171
1172
1173
1174int
1175il3945_calc_db_from_ratio(int sig_ratio)
1176{
1177
1178 if (sig_ratio >= 1000)
1179 return 60;
1180
1181
1182
1183 if (sig_ratio >= 100)
1184 return 20 + (int)ratio2dB[sig_ratio / 10];
1185
1186
1187 if (sig_ratio < 1)
1188 return 0;
1189
1190
1191 return (int)ratio2dB[sig_ratio];
1192}
1193
1194
1195
1196
1197
1198
1199
1200
1201static void
1202il3945_rx_handle(struct il_priv *il)
1203{
1204 struct il_rx_buf *rxb;
1205 struct il_rx_pkt *pkt;
1206 struct il_rx_queue *rxq = &il->rxq;
1207 u32 r, i;
1208 int reclaim;
1209 unsigned long flags;
1210 u8 fill_rx = 0;
1211 u32 count = 8;
1212 int total_empty = 0;
1213
1214
1215
1216 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1217 i = rxq->read;
1218
1219
1220 total_empty = r - rxq->write_actual;
1221 if (total_empty < 0)
1222 total_empty += RX_QUEUE_SIZE;
1223
1224 if (total_empty > (RX_QUEUE_SIZE / 2))
1225 fill_rx = 1;
1226
1227 if (i == r)
1228 D_RX("r = %d, i = %d\n", r, i);
1229
1230 while (i != r) {
1231 int len;
1232
1233 rxb = rxq->queue[i];
1234
1235
1236
1237
1238 BUG_ON(rxb == NULL);
1239
1240 rxq->queue[i] = NULL;
1241
1242 pci_unmap_page(il->pci_dev, rxb->page_dma,
1243 PAGE_SIZE << il->hw_params.rx_page_order,
1244 PCI_DMA_FROMDEVICE);
1245 pkt = rxb_addr(rxb);
1246
1247 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
1248 len += sizeof(u32);
1249
1250 reclaim = il_need_reclaim(il, pkt);
1251
1252
1253
1254
1255 if (il->handlers[pkt->hdr.cmd]) {
1256 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
1257 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1258 il->isr_stats.handlers[pkt->hdr.cmd]++;
1259 il->handlers[pkt->hdr.cmd] (il, rxb);
1260 } else {
1261
1262 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1263 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1264 }
1265
1266
1267
1268
1269
1270
1271
1272
1273 if (reclaim) {
1274
1275
1276
1277 if (rxb->page)
1278 il_tx_cmd_complete(il, rxb);
1279 else
1280 IL_WARN("Claim null rxb?\n");
1281 }
1282
1283
1284
1285
1286 spin_lock_irqsave(&rxq->lock, flags);
1287 if (rxb->page != NULL) {
1288 rxb->page_dma =
1289 pci_map_page(il->pci_dev, rxb->page, 0,
1290 PAGE_SIZE << il->hw_params.
1291 rx_page_order, PCI_DMA_FROMDEVICE);
1292 if (unlikely(pci_dma_mapping_error(il->pci_dev,
1293 rxb->page_dma))) {
1294 __il_free_pages(il, rxb->page);
1295 rxb->page = NULL;
1296 list_add_tail(&rxb->list, &rxq->rx_used);
1297 } else {
1298 list_add_tail(&rxb->list, &rxq->rx_free);
1299 rxq->free_count++;
1300 }
1301 } else
1302 list_add_tail(&rxb->list, &rxq->rx_used);
1303
1304 spin_unlock_irqrestore(&rxq->lock, flags);
1305
1306 i = (i + 1) & RX_QUEUE_MASK;
1307
1308
1309 if (fill_rx) {
1310 count++;
1311 if (count >= 8) {
1312 rxq->read = i;
1313 il3945_rx_replenish_now(il);
1314 count = 0;
1315 }
1316 }
1317 }
1318
1319
1320 rxq->read = i;
1321 if (fill_rx)
1322 il3945_rx_replenish_now(il);
1323 else
1324 il3945_rx_queue_restock(il);
1325}
1326
1327
1328static inline void
1329il3945_synchronize_irq(struct il_priv *il)
1330{
1331
1332 synchronize_irq(il->pci_dev->irq);
1333 tasklet_kill(&il->irq_tasklet);
1334}
1335
1336static const char *
1337il3945_desc_lookup(int i)
1338{
1339 switch (i) {
1340 case 1:
1341 return "FAIL";
1342 case 2:
1343 return "BAD_PARAM";
1344 case 3:
1345 return "BAD_CHECKSUM";
1346 case 4:
1347 return "NMI_INTERRUPT";
1348 case 5:
1349 return "SYSASSERT";
1350 case 6:
1351 return "FATAL_ERROR";
1352 }
1353
1354 return "UNKNOWN";
1355}
1356
1357#define ERROR_START_OFFSET (1 * sizeof(u32))
1358#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1359
1360void
1361il3945_dump_nic_error_log(struct il_priv *il)
1362{
1363 u32 i;
1364 u32 desc, time, count, base, data1;
1365 u32 blink1, blink2, ilink1, ilink2;
1366
1367 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1368
1369 if (!il3945_hw_valid_rtc_data_addr(base)) {
1370 IL_ERR("Not valid error log pointer 0x%08X\n", base);
1371 return;
1372 }
1373
1374 count = il_read_targ_mem(il, base);
1375
1376 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1377 IL_ERR("Start IWL Error Log Dump:\n");
1378 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1379 }
1380
1381 IL_ERR("Desc Time asrtPC blink2 "
1382 "ilink1 nmiPC Line\n");
1383 for (i = ERROR_START_OFFSET;
1384 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1385 i += ERROR_ELEM_SIZE) {
1386 desc = il_read_targ_mem(il, base + i);
1387 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1388 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1389 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1390 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1391 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1392 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1393
1394 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1395 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1396 ilink1, ilink2, data1);
1397 }
1398}
1399
1400static void
1401il3945_irq_tasklet(struct il_priv *il)
1402{
1403 u32 inta, handled = 0;
1404 u32 inta_fh;
1405 unsigned long flags;
1406#ifdef CONFIG_IWLEGACY_DEBUG
1407 u32 inta_mask;
1408#endif
1409
1410 spin_lock_irqsave(&il->lock, flags);
1411
1412
1413
1414
1415 inta = _il_rd(il, CSR_INT);
1416 _il_wr(il, CSR_INT, inta);
1417
1418
1419
1420
1421 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1422 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1423
1424#ifdef CONFIG_IWLEGACY_DEBUG
1425 if (il_get_debug_level(il) & IL_DL_ISR) {
1426
1427 inta_mask = _il_rd(il, CSR_INT_MASK);
1428 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1429 inta_mask, inta_fh);
1430 }
1431#endif
1432
1433 spin_unlock_irqrestore(&il->lock, flags);
1434
1435
1436
1437
1438
1439 if (inta_fh & CSR39_FH_INT_RX_MASK)
1440 inta |= CSR_INT_BIT_FH_RX;
1441 if (inta_fh & CSR39_FH_INT_TX_MASK)
1442 inta |= CSR_INT_BIT_FH_TX;
1443
1444
1445 if (inta & CSR_INT_BIT_HW_ERR) {
1446 IL_ERR("Hardware error detected. Restarting.\n");
1447
1448
1449 il_disable_interrupts(il);
1450
1451 il->isr_stats.hw++;
1452 il_irq_handle_error(il);
1453
1454 handled |= CSR_INT_BIT_HW_ERR;
1455
1456 return;
1457 }
1458#ifdef CONFIG_IWLEGACY_DEBUG
1459 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1460
1461 if (inta & CSR_INT_BIT_SCD) {
1462 D_ISR("Scheduler finished to transmit "
1463 "the frame/frames.\n");
1464 il->isr_stats.sch++;
1465 }
1466
1467
1468 if (inta & CSR_INT_BIT_ALIVE) {
1469 D_ISR("Alive interrupt\n");
1470 il->isr_stats.alive++;
1471 }
1472 }
1473#endif
1474
1475 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1476
1477
1478 if (inta & CSR_INT_BIT_SW_ERR) {
1479 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1480 inta);
1481 il->isr_stats.sw++;
1482 il_irq_handle_error(il);
1483 handled |= CSR_INT_BIT_SW_ERR;
1484 }
1485
1486
1487 if (inta & CSR_INT_BIT_WAKEUP) {
1488 D_ISR("Wakeup interrupt\n");
1489 il_rx_queue_update_write_ptr(il, &il->rxq);
1490
1491 spin_lock_irqsave(&il->lock, flags);
1492 il_txq_update_write_ptr(il, &il->txq[0]);
1493 il_txq_update_write_ptr(il, &il->txq[1]);
1494 il_txq_update_write_ptr(il, &il->txq[2]);
1495 il_txq_update_write_ptr(il, &il->txq[3]);
1496 il_txq_update_write_ptr(il, &il->txq[4]);
1497 spin_unlock_irqrestore(&il->lock, flags);
1498
1499 il->isr_stats.wakeup++;
1500 handled |= CSR_INT_BIT_WAKEUP;
1501 }
1502
1503
1504
1505
1506 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1507 il3945_rx_handle(il);
1508 il->isr_stats.rx++;
1509 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1510 }
1511
1512 if (inta & CSR_INT_BIT_FH_TX) {
1513 D_ISR("Tx interrupt\n");
1514 il->isr_stats.tx++;
1515
1516 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1517 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1518 handled |= CSR_INT_BIT_FH_TX;
1519 }
1520
1521 if (inta & ~handled) {
1522 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1523 il->isr_stats.unhandled++;
1524 }
1525
1526 if (inta & ~il->inta_mask) {
1527 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
1528 inta & ~il->inta_mask);
1529 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
1530 }
1531
1532
1533
1534 if (test_bit(S_INT_ENABLED, &il->status))
1535 il_enable_interrupts(il);
1536
1537#ifdef CONFIG_IWLEGACY_DEBUG
1538 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1539 inta = _il_rd(il, CSR_INT);
1540 inta_mask = _il_rd(il, CSR_INT_MASK);
1541 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1542 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1543 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1544 }
1545#endif
1546}
1547
1548static int
1549il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1550 u8 is_active, u8 n_probes,
1551 struct il3945_scan_channel *scan_ch,
1552 struct ieee80211_vif *vif)
1553{
1554 struct ieee80211_channel *chan;
1555 const struct ieee80211_supported_band *sband;
1556 const struct il_channel_info *ch_info;
1557 u16 passive_dwell = 0;
1558 u16 active_dwell = 0;
1559 int added, i;
1560
1561 sband = il_get_hw_mode(il, band);
1562 if (!sband)
1563 return 0;
1564
1565 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1566 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1567
1568 if (passive_dwell <= active_dwell)
1569 passive_dwell = active_dwell + 1;
1570
1571 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1572 chan = il->scan_request->channels[i];
1573
1574 if (chan->band != band)
1575 continue;
1576
1577 scan_ch->channel = chan->hw_value;
1578
1579 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1580 if (!il_is_channel_valid(ch_info)) {
1581 D_SCAN("Channel %d is INVALID for this band.\n",
1582 scan_ch->channel);
1583 continue;
1584 }
1585
1586 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1587 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1588
1589
1590
1591 if (!is_active || il_is_channel_passive(ch_info) ||
1592 (chan->flags & IEEE80211_CHAN_NO_IR)) {
1593 scan_ch->type = 0;
1594 if (IL_UCODE_API(il->ucode_ver) == 1)
1595 scan_ch->active_dwell =
1596 cpu_to_le16(passive_dwell - 1);
1597 } else {
1598 scan_ch->type = 1;
1599 }
1600
1601
1602
1603
1604
1605 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1606 if (n_probes)
1607 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1608 } else {
1609
1610
1611 if ((scan_ch->type & 1) && n_probes)
1612 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1613 }
1614
1615
1616 scan_ch->tpc.dsp_atten = 110;
1617
1618
1619
1620 if (band == NL80211_BAND_5GHZ)
1621 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1622 else {
1623 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1624
1625
1626
1627
1628 }
1629
1630 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1631 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1632 (scan_ch->type & 1) ? active_dwell : passive_dwell);
1633
1634 scan_ch++;
1635 added++;
1636 }
1637
1638 D_SCAN("total channels to scan %d\n", added);
1639 return added;
1640}
1641
1642static void
1643il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1644{
1645 int i;
1646
1647 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
1648 rates[i].bitrate = il3945_rates[i].ieee * 5;
1649 rates[i].hw_value = i;
1650 rates[i].hw_value_short = i;
1651 rates[i].flags = 0;
1652 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
1653
1654
1655
1656 rates[i].flags |=
1657 (il3945_rates[i].plcp ==
1658 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1659 }
1660 }
1661}
1662
1663
1664
1665
1666
1667
1668
1669static void
1670il3945_dealloc_ucode_pci(struct il_priv *il)
1671{
1672 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1673 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1674 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1675 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1676 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1677 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1678}
1679
1680
1681
1682
1683
1684static int
1685il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1686{
1687 u32 val;
1688 u32 save_len = len;
1689 int rc = 0;
1690 u32 errcnt;
1691
1692 D_INFO("ucode inst image size is %u\n", len);
1693
1694 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1695
1696 errcnt = 0;
1697 for (; len > 0; len -= sizeof(u32), image++) {
1698
1699
1700
1701 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1702 if (val != le32_to_cpu(*image)) {
1703 IL_ERR("uCode INST section is invalid at "
1704 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1705 save_len - len, val, le32_to_cpu(*image));
1706 rc = -EIO;
1707 errcnt++;
1708 if (errcnt >= 20)
1709 break;
1710 }
1711 }
1712
1713 if (!errcnt)
1714 D_INFO("ucode image in INSTRUCTION memory is good\n");
1715
1716 return rc;
1717}
1718
1719
1720
1721
1722
1723
1724static int
1725il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1726{
1727 u32 val;
1728 int rc = 0;
1729 u32 errcnt = 0;
1730 u32 i;
1731
1732 D_INFO("ucode inst image size is %u\n", len);
1733
1734 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
1735
1736
1737
1738 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1739 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1740 if (val != le32_to_cpu(*image)) {
1741#if 0
1742 IL_ERR("uCode INST section is invalid at "
1743 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1744 *image);
1745#endif
1746 rc = -EIO;
1747 errcnt++;
1748 if (errcnt >= 3)
1749 break;
1750 }
1751 }
1752
1753 return rc;
1754}
1755
1756
1757
1758
1759
1760static int
1761il3945_verify_ucode(struct il_priv *il)
1762{
1763 __le32 *image;
1764 u32 len;
1765 int rc = 0;
1766
1767
1768 image = (__le32 *) il->ucode_boot.v_addr;
1769 len = il->ucode_boot.len;
1770 rc = il3945_verify_inst_sparse(il, image, len);
1771 if (rc == 0) {
1772 D_INFO("Bootstrap uCode is good in inst SRAM\n");
1773 return 0;
1774 }
1775
1776
1777 image = (__le32 *) il->ucode_init.v_addr;
1778 len = il->ucode_init.len;
1779 rc = il3945_verify_inst_sparse(il, image, len);
1780 if (rc == 0) {
1781 D_INFO("Initialize uCode is good in inst SRAM\n");
1782 return 0;
1783 }
1784
1785
1786 image = (__le32 *) il->ucode_code.v_addr;
1787 len = il->ucode_code.len;
1788 rc = il3945_verify_inst_sparse(il, image, len);
1789 if (rc == 0) {
1790 D_INFO("Runtime uCode is good in inst SRAM\n");
1791 return 0;
1792 }
1793
1794 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1795
1796
1797
1798
1799 image = (__le32 *) il->ucode_boot.v_addr;
1800 len = il->ucode_boot.len;
1801 rc = il3945_verify_inst_full(il, image, len);
1802
1803 return rc;
1804}
1805
1806static void
1807il3945_nic_start(struct il_priv *il)
1808{
1809
1810 _il_wr(il, CSR_RESET, 0);
1811}
1812
1813#define IL3945_UCODE_GET(item) \
1814static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
1815{ \
1816 return le32_to_cpu(ucode->v1.item); \
1817}
1818
1819static u32
1820il3945_ucode_get_header_size(u32 api_ver)
1821{
1822 return 24;
1823}
1824
1825static u8 *
1826il3945_ucode_get_data(const struct il_ucode_header *ucode)
1827{
1828 return (u8 *) ucode->v1.data;
1829}
1830
1831IL3945_UCODE_GET(inst_size);
1832IL3945_UCODE_GET(data_size);
1833IL3945_UCODE_GET(init_size);
1834IL3945_UCODE_GET(init_data_size);
1835IL3945_UCODE_GET(boot_size);
1836
1837
1838
1839
1840
1841
1842static int
1843il3945_read_ucode(struct il_priv *il)
1844{
1845 const struct il_ucode_header *ucode;
1846 int ret = -EINVAL, idx;
1847 const struct firmware *ucode_raw;
1848
1849 const char *name_pre = il->cfg->fw_name_pre;
1850 const unsigned int api_max = il->cfg->ucode_api_max;
1851 const unsigned int api_min = il->cfg->ucode_api_min;
1852 char buf[25];
1853 u8 *src;
1854 size_t len;
1855 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1856
1857
1858
1859 for (idx = api_max; idx >= api_min; idx--) {
1860 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
1861 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1862 if (ret < 0) {
1863 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
1864 if (ret == -ENOENT)
1865 continue;
1866 else
1867 goto error;
1868 } else {
1869 if (idx < api_max)
1870 IL_ERR("Loaded firmware %s, "
1871 "which is deprecated. "
1872 " Please use API v%u instead.\n", buf,
1873 api_max);
1874 D_INFO("Got firmware '%s' file "
1875 "(%zd bytes) from disk\n", buf, ucode_raw->size);
1876 break;
1877 }
1878 }
1879
1880 if (ret < 0)
1881 goto error;
1882
1883
1884 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
1885 IL_ERR("File size way too small!\n");
1886 ret = -EINVAL;
1887 goto err_release;
1888 }
1889
1890
1891 ucode = (struct il_ucode_header *)ucode_raw->data;
1892
1893 il->ucode_ver = le32_to_cpu(ucode->ver);
1894 api_ver = IL_UCODE_API(il->ucode_ver);
1895 inst_size = il3945_ucode_get_inst_size(ucode);
1896 data_size = il3945_ucode_get_data_size(ucode);
1897 init_size = il3945_ucode_get_init_size(ucode);
1898 init_data_size = il3945_ucode_get_init_data_size(ucode);
1899 boot_size = il3945_ucode_get_boot_size(ucode);
1900 src = il3945_ucode_get_data(ucode);
1901
1902
1903
1904
1905
1906 if (api_ver < api_min || api_ver > api_max) {
1907 IL_ERR("Driver unable to support your firmware API. "
1908 "Driver supports v%u, firmware is v%u.\n", api_max,
1909 api_ver);
1910 il->ucode_ver = 0;
1911 ret = -EINVAL;
1912 goto err_release;
1913 }
1914 if (api_ver != api_max)
1915 IL_ERR("Firmware has old API version. Expected %u, "
1916 "got %u. New firmware can be obtained "
1917 "from http://www.intellinuxwireless.org.\n", api_max,
1918 api_ver);
1919
1920 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1921 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1922 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1923
1924 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1925 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1926 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1927 IL_UCODE_SERIAL(il->ucode_ver));
1928
1929 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1930 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1931 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1932 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1933 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1934 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
1935
1936
1937 if (ucode_raw->size !=
1938 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1939 init_size + init_data_size + boot_size) {
1940
1941 D_INFO("uCode file size %zd does not match expected size\n",
1942 ucode_raw->size);
1943 ret = -EINVAL;
1944 goto err_release;
1945 }
1946
1947
1948 if (inst_size > IL39_MAX_INST_SIZE) {
1949 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
1950 ret = -EINVAL;
1951 goto err_release;
1952 }
1953
1954 if (data_size > IL39_MAX_DATA_SIZE) {
1955 D_INFO("uCode data len %d too large to fit in\n", data_size);
1956 ret = -EINVAL;
1957 goto err_release;
1958 }
1959 if (init_size > IL39_MAX_INST_SIZE) {
1960 D_INFO("uCode init instr len %d too large to fit in\n",
1961 init_size);
1962 ret = -EINVAL;
1963 goto err_release;
1964 }
1965 if (init_data_size > IL39_MAX_DATA_SIZE) {
1966 D_INFO("uCode init data len %d too large to fit in\n",
1967 init_data_size);
1968 ret = -EINVAL;
1969 goto err_release;
1970 }
1971 if (boot_size > IL39_MAX_BSM_SIZE) {
1972 D_INFO("uCode boot instr len %d too large to fit in\n",
1973 boot_size);
1974 ret = -EINVAL;
1975 goto err_release;
1976 }
1977
1978
1979
1980
1981
1982
1983 il->ucode_code.len = inst_size;
1984 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1985
1986 il->ucode_data.len = data_size;
1987 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1988
1989 il->ucode_data_backup.len = data_size;
1990 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1991
1992 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1993 !il->ucode_data_backup.v_addr)
1994 goto err_pci_alloc;
1995
1996
1997 if (init_size && init_data_size) {
1998 il->ucode_init.len = init_size;
1999 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
2000
2001 il->ucode_init_data.len = init_data_size;
2002 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
2003
2004 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
2005 goto err_pci_alloc;
2006 }
2007
2008
2009 if (boot_size) {
2010 il->ucode_boot.len = boot_size;
2011 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
2012
2013 if (!il->ucode_boot.v_addr)
2014 goto err_pci_alloc;
2015 }
2016
2017
2018
2019
2020 len = inst_size;
2021 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
2022 memcpy(il->ucode_code.v_addr, src, len);
2023 src += len;
2024
2025 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2026 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2027
2028
2029
2030 len = data_size;
2031 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
2032 memcpy(il->ucode_data.v_addr, src, len);
2033 memcpy(il->ucode_data_backup.v_addr, src, len);
2034 src += len;
2035
2036
2037 if (init_size) {
2038 len = init_size;
2039 D_INFO("Copying (but not loading) init instr len %zd\n", len);
2040 memcpy(il->ucode_init.v_addr, src, len);
2041 src += len;
2042 }
2043
2044
2045 if (init_data_size) {
2046 len = init_data_size;
2047 D_INFO("Copying (but not loading) init data len %zd\n", len);
2048 memcpy(il->ucode_init_data.v_addr, src, len);
2049 src += len;
2050 }
2051
2052
2053 len = boot_size;
2054 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
2055 memcpy(il->ucode_boot.v_addr, src, len);
2056
2057
2058 release_firmware(ucode_raw);
2059 return 0;
2060
2061err_pci_alloc:
2062 IL_ERR("failed to allocate pci memory\n");
2063 ret = -ENOMEM;
2064 il3945_dealloc_ucode_pci(il);
2065
2066err_release:
2067 release_firmware(ucode_raw);
2068
2069error:
2070 return ret;
2071}
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082static int
2083il3945_set_ucode_ptrs(struct il_priv *il)
2084{
2085 dma_addr_t pinst;
2086 dma_addr_t pdata;
2087
2088
2089 pinst = il->ucode_code.p_addr;
2090 pdata = il->ucode_data_backup.p_addr;
2091
2092
2093 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2094 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2095 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2096
2097
2098
2099 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2100 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2101
2102 D_INFO("Runtime uCode pointers are set.\n");
2103
2104 return 0;
2105}
2106
2107
2108
2109
2110
2111
2112
2113
2114static void
2115il3945_init_alive_start(struct il_priv *il)
2116{
2117
2118 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2119
2120
2121 D_INFO("Initialize Alive failed.\n");
2122 goto restart;
2123 }
2124
2125
2126
2127
2128 if (il3945_verify_ucode(il)) {
2129
2130
2131 D_INFO("Bad \"initialize\" uCode load.\n");
2132 goto restart;
2133 }
2134
2135
2136
2137
2138 D_INFO("Initialization Alive received.\n");
2139 if (il3945_set_ucode_ptrs(il)) {
2140
2141
2142 D_INFO("Couldn't set up uCode pointers.\n");
2143 goto restart;
2144 }
2145 return;
2146
2147restart:
2148 queue_work(il->workqueue, &il->restart);
2149}
2150
2151
2152
2153
2154
2155
2156static void
2157il3945_alive_start(struct il_priv *il)
2158{
2159 int thermal_spin = 0;
2160 u32 rfkill;
2161
2162 D_INFO("Runtime Alive received.\n");
2163
2164 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2165
2166
2167 D_INFO("Alive failed.\n");
2168 goto restart;
2169 }
2170
2171
2172
2173
2174 if (il3945_verify_ucode(il)) {
2175
2176
2177 D_INFO("Bad runtime uCode load.\n");
2178 goto restart;
2179 }
2180
2181 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2182 D_INFO("RFKILL status: 0x%x\n", rfkill);
2183
2184 if (rfkill & 0x1) {
2185 clear_bit(S_RFKILL, &il->status);
2186
2187
2188 while (il3945_hw_get_temperature(il) == 0) {
2189 thermal_spin++;
2190 udelay(10);
2191 }
2192
2193 if (thermal_spin)
2194 D_INFO("Thermal calibration took %dus\n",
2195 thermal_spin * 10);
2196 } else
2197 set_bit(S_RFKILL, &il->status);
2198
2199
2200 set_bit(S_ALIVE, &il->status);
2201
2202
2203 il_setup_watchdog(il);
2204
2205 if (il_is_rfkill(il))
2206 return;
2207
2208 ieee80211_wake_queues(il->hw);
2209
2210 il->active_rate = RATES_MASK_3945;
2211
2212 il_power_update_mode(il, true);
2213
2214 if (il_is_associated(il)) {
2215 struct il3945_rxon_cmd *active_rxon =
2216 (struct il3945_rxon_cmd *)(&il->active);
2217
2218 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2219 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2220 } else {
2221
2222 il_connection_init_rx_config(il);
2223 }
2224
2225
2226 il_send_bt_config(il);
2227
2228 set_bit(S_READY, &il->status);
2229
2230
2231 il3945_commit_rxon(il);
2232
2233 il3945_reg_txpower_periodic(il);
2234
2235 D_INFO("ALIVE processing complete.\n");
2236 wake_up(&il->wait_command_queue);
2237
2238 return;
2239
2240restart:
2241 queue_work(il->workqueue, &il->restart);
2242}
2243
2244static void il3945_cancel_deferred_work(struct il_priv *il);
2245
2246static void
2247__il3945_down(struct il_priv *il)
2248{
2249 unsigned long flags;
2250 int exit_pending;
2251
2252 D_INFO(DRV_NAME " is going down\n");
2253
2254 il_scan_cancel_timeout(il, 200);
2255
2256 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2257
2258
2259
2260 del_timer_sync(&il->watchdog);
2261
2262
2263 il_clear_ucode_stations(il);
2264 il_dealloc_bcast_stations(il);
2265 il_clear_driver_stations(il);
2266
2267
2268 wake_up_all(&il->wait_command_queue);
2269
2270
2271
2272 if (!exit_pending)
2273 clear_bit(S_EXIT_PENDING, &il->status);
2274
2275
2276 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2277
2278
2279 spin_lock_irqsave(&il->lock, flags);
2280 il_disable_interrupts(il);
2281 spin_unlock_irqrestore(&il->lock, flags);
2282 il3945_synchronize_irq(il);
2283
2284 if (il->mac80211_registered)
2285 ieee80211_stop_queues(il->hw);
2286
2287
2288
2289 if (!il_is_init(il)) {
2290 il->status =
2291 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2292 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2293 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2294 goto exit;
2295 }
2296
2297
2298
2299 il->status &=
2300 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2301 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2302 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2303 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2304
2305
2306
2307
2308
2309
2310 spin_lock_irq(&il->reg_lock);
2311
2312
2313 il3945_hw_txq_ctx_stop(il);
2314 il3945_hw_rxq_stop(il);
2315
2316 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2317 udelay(5);
2318
2319 _il_apm_stop(il);
2320
2321 spin_unlock_irq(&il->reg_lock);
2322
2323 il3945_hw_txq_ctx_free(il);
2324exit:
2325 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2326 dev_kfree_skb(il->beacon_skb);
2327 il->beacon_skb = NULL;
2328
2329
2330 il3945_clear_free_frames(il);
2331}
2332
2333static void
2334il3945_down(struct il_priv *il)
2335{
2336 mutex_lock(&il->mutex);
2337 __il3945_down(il);
2338 mutex_unlock(&il->mutex);
2339
2340 il3945_cancel_deferred_work(il);
2341}
2342
2343#define MAX_HW_RESTARTS 5
2344
2345static int
2346il3945_alloc_bcast_station(struct il_priv *il)
2347{
2348 unsigned long flags;
2349 u8 sta_id;
2350
2351 spin_lock_irqsave(&il->sta_lock, flags);
2352 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2353 if (sta_id == IL_INVALID_STATION) {
2354 IL_ERR("Unable to prepare broadcast station\n");
2355 spin_unlock_irqrestore(&il->sta_lock, flags);
2356
2357 return -EINVAL;
2358 }
2359
2360 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2361 il->stations[sta_id].used |= IL_STA_BCAST;
2362 spin_unlock_irqrestore(&il->sta_lock, flags);
2363
2364 return 0;
2365}
2366
2367static int
2368__il3945_up(struct il_priv *il)
2369{
2370 int rc, i;
2371
2372 rc = il3945_alloc_bcast_station(il);
2373 if (rc)
2374 return rc;
2375
2376 if (test_bit(S_EXIT_PENDING, &il->status)) {
2377 IL_WARN("Exit pending; will not bring the NIC up\n");
2378 return -EIO;
2379 }
2380
2381 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2382 IL_ERR("ucode not available for device bring up\n");
2383 return -EIO;
2384 }
2385
2386
2387 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2388 clear_bit(S_RFKILL, &il->status);
2389 else {
2390 set_bit(S_RFKILL, &il->status);
2391 return -ERFKILL;
2392 }
2393
2394 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2395
2396 rc = il3945_hw_nic_init(il);
2397 if (rc) {
2398 IL_ERR("Unable to int nic\n");
2399 return rc;
2400 }
2401
2402
2403 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2404 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2405
2406
2407 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2408 il_enable_interrupts(il);
2409
2410
2411 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2412 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2413
2414
2415
2416
2417 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2418 il->ucode_data.len);
2419
2420
2421 if (test_bit(S_RFKILL, &il->status))
2422 return 0;
2423
2424 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2425
2426
2427
2428
2429 rc = il->ops->load_ucode(il);
2430
2431 if (rc) {
2432 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
2433 continue;
2434 }
2435
2436
2437 il3945_nic_start(il);
2438
2439 D_INFO(DRV_NAME " is coming up\n");
2440
2441 return 0;
2442 }
2443
2444 set_bit(S_EXIT_PENDING, &il->status);
2445 __il3945_down(il);
2446 clear_bit(S_EXIT_PENDING, &il->status);
2447
2448
2449
2450 IL_ERR("Unable to initialize device after %d attempts.\n", i);
2451 return -EIO;
2452}
2453
2454
2455
2456
2457
2458
2459
2460static void
2461il3945_bg_init_alive_start(struct work_struct *data)
2462{
2463 struct il_priv *il =
2464 container_of(data, struct il_priv, init_alive_start.work);
2465
2466 mutex_lock(&il->mutex);
2467 if (test_bit(S_EXIT_PENDING, &il->status))
2468 goto out;
2469
2470 il3945_init_alive_start(il);
2471out:
2472 mutex_unlock(&il->mutex);
2473}
2474
2475static void
2476il3945_bg_alive_start(struct work_struct *data)
2477{
2478 struct il_priv *il =
2479 container_of(data, struct il_priv, alive_start.work);
2480
2481 mutex_lock(&il->mutex);
2482 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2483 goto out;
2484
2485 il3945_alive_start(il);
2486out:
2487 mutex_unlock(&il->mutex);
2488}
2489
2490
2491
2492
2493
2494
2495
2496static void
2497il3945_rfkill_poll(struct work_struct *data)
2498{
2499 struct il_priv *il =
2500 container_of(data, struct il_priv, _3945.rfkill_poll.work);
2501 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2502 bool new_rfkill =
2503 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2504
2505 if (new_rfkill != old_rfkill) {
2506 if (new_rfkill)
2507 set_bit(S_RFKILL, &il->status);
2508 else
2509 clear_bit(S_RFKILL, &il->status);
2510
2511 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2512
2513 D_RF_KILL("RF_KILL bit toggled to %s.\n",
2514 new_rfkill ? "disable radio" : "enable radio");
2515 }
2516
2517
2518
2519 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2520 round_jiffies_relative(2 * HZ));
2521
2522}
2523
2524int
2525il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2526{
2527 struct il_host_cmd cmd = {
2528 .id = C_SCAN,
2529 .len = sizeof(struct il3945_scan_cmd),
2530 .flags = CMD_SIZE_HUGE,
2531 };
2532 struct il3945_scan_cmd *scan;
2533 u8 n_probes = 0;
2534 enum nl80211_band band;
2535 bool is_active = false;
2536 int ret;
2537 u16 len;
2538
2539 lockdep_assert_held(&il->mutex);
2540
2541 if (!il->scan_cmd) {
2542 il->scan_cmd =
2543 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2544 GFP_KERNEL);
2545 if (!il->scan_cmd) {
2546 D_SCAN("Fail to allocate scan memory\n");
2547 return -ENOMEM;
2548 }
2549 }
2550 scan = il->scan_cmd;
2551 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
2552
2553 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2554 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
2555
2556 if (il_is_associated(il)) {
2557 u16 interval;
2558 u32 extra;
2559 u32 suspend_time = 100;
2560 u32 scan_suspend_time = 100;
2561
2562 D_INFO("Scanning while associated...\n");
2563
2564 interval = vif->bss_conf.beacon_int;
2565
2566 scan->suspend_time = 0;
2567 scan->max_out_time = cpu_to_le32(200 * 1024);
2568 if (!interval)
2569 interval = suspend_time;
2570
2571
2572
2573
2574
2575
2576
2577 extra = (suspend_time / interval) << 24;
2578 scan_suspend_time =
2579 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
2580
2581 scan->suspend_time = cpu_to_le32(scan_suspend_time);
2582 D_SCAN("suspend_time 0x%X beacon interval %d\n",
2583 scan_suspend_time, interval);
2584 }
2585
2586 if (il->scan_request->n_ssids) {
2587 int i, p = 0;
2588 D_SCAN("Kicking off active scan\n");
2589 for (i = 0; i < il->scan_request->n_ssids; i++) {
2590
2591 if (!il->scan_request->ssids[i].ssid_len)
2592 continue;
2593 scan->direct_scan[p].id = WLAN_EID_SSID;
2594 scan->direct_scan[p].len =
2595 il->scan_request->ssids[i].ssid_len;
2596 memcpy(scan->direct_scan[p].ssid,
2597 il->scan_request->ssids[i].ssid,
2598 il->scan_request->ssids[i].ssid_len);
2599 n_probes++;
2600 p++;
2601 }
2602 is_active = true;
2603 } else
2604 D_SCAN("Kicking off passive scan.\n");
2605
2606
2607
2608 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2609 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2610 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2611
2612
2613
2614 switch (il->scan_band) {
2615 case NL80211_BAND_2GHZ:
2616 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2617 scan->tx_cmd.rate = RATE_1M_PLCP;
2618 band = NL80211_BAND_2GHZ;
2619 break;
2620 case NL80211_BAND_5GHZ:
2621 scan->tx_cmd.rate = RATE_6M_PLCP;
2622 band = NL80211_BAND_5GHZ;
2623 break;
2624 default:
2625 IL_WARN("Invalid scan band\n");
2626 return -EIO;
2627 }
2628
2629
2630
2631
2632
2633
2634 scan->good_CRC_th =
2635 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
2636
2637 len =
2638 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2639 vif->addr, il->scan_request->ie,
2640 il->scan_request->ie_len,
2641 IL_MAX_SCAN_SIZE - sizeof(*scan));
2642 scan->tx_cmd.len = cpu_to_le16(len);
2643
2644
2645 scan->flags |= il3945_get_antenna_flags(il);
2646
2647 scan->channel_count =
2648 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2649 (void *)&scan->data[len], vif);
2650 if (scan->channel_count == 0) {
2651 D_SCAN("channel count %d\n", scan->channel_count);
2652 return -EIO;
2653 }
2654
2655 cmd.len +=
2656 le16_to_cpu(scan->tx_cmd.len) +
2657 scan->channel_count * sizeof(struct il3945_scan_channel);
2658 cmd.data = scan;
2659 scan->len = cpu_to_le16(cmd.len);
2660
2661 set_bit(S_SCAN_HW, &il->status);
2662 ret = il_send_cmd_sync(il, &cmd);
2663 if (ret)
2664 clear_bit(S_SCAN_HW, &il->status);
2665 return ret;
2666}
2667
2668void
2669il3945_post_scan(struct il_priv *il)
2670{
2671
2672
2673
2674
2675 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2676 il3945_commit_rxon(il);
2677}
2678
2679static void
2680il3945_bg_restart(struct work_struct *data)
2681{
2682 struct il_priv *il = container_of(data, struct il_priv, restart);
2683
2684 if (test_bit(S_EXIT_PENDING, &il->status))
2685 return;
2686
2687 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2688 mutex_lock(&il->mutex);
2689 il->is_open = 0;
2690 mutex_unlock(&il->mutex);
2691 il3945_down(il);
2692 ieee80211_restart_hw(il->hw);
2693 } else {
2694 il3945_down(il);
2695
2696 mutex_lock(&il->mutex);
2697 if (test_bit(S_EXIT_PENDING, &il->status)) {
2698 mutex_unlock(&il->mutex);
2699 return;
2700 }
2701
2702 __il3945_up(il);
2703 mutex_unlock(&il->mutex);
2704 }
2705}
2706
2707static void
2708il3945_bg_rx_replenish(struct work_struct *data)
2709{
2710 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2711
2712 mutex_lock(&il->mutex);
2713 if (test_bit(S_EXIT_PENDING, &il->status))
2714 goto out;
2715
2716 il3945_rx_replenish(il);
2717out:
2718 mutex_unlock(&il->mutex);
2719}
2720
2721void
2722il3945_post_associate(struct il_priv *il)
2723{
2724 int rc = 0;
2725 struct ieee80211_conf *conf = NULL;
2726
2727 if (!il->vif || !il->is_open)
2728 return;
2729
2730 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
2731 il->active.bssid_addr);
2732
2733 if (test_bit(S_EXIT_PENDING, &il->status))
2734 return;
2735
2736 il_scan_cancel_timeout(il, 200);
2737
2738 conf = &il->hw->conf;
2739
2740 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2741 il3945_commit_rxon(il);
2742
2743 rc = il_send_rxon_timing(il);
2744 if (rc)
2745 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
2746
2747 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2748
2749 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
2750
2751 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2752 il->vif->bss_conf.beacon_int);
2753
2754 if (il->vif->bss_conf.use_short_preamble)
2755 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2756 else
2757 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2758
2759 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2760 if (il->vif->bss_conf.use_short_slot)
2761 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2762 else
2763 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2764 }
2765
2766 il3945_commit_rxon(il);
2767
2768 switch (il->vif->type) {
2769 case NL80211_IFTYPE_STATION:
2770 il3945_rate_scale_init(il->hw, IL_AP_ID);
2771 break;
2772 case NL80211_IFTYPE_ADHOC:
2773 il3945_send_beacon_cmd(il);
2774 break;
2775 default:
2776 IL_ERR("%s Should not be called in %d mode\n", __func__,
2777 il->vif->type);
2778 break;
2779 }
2780}
2781
2782
2783
2784
2785
2786
2787
2788#define UCODE_READY_TIMEOUT (2 * HZ)
2789
2790static int
2791il3945_mac_start(struct ieee80211_hw *hw)
2792{
2793 struct il_priv *il = hw->priv;
2794 int ret;
2795
2796
2797 mutex_lock(&il->mutex);
2798 D_MAC80211("enter\n");
2799
2800
2801
2802
2803 if (!il->ucode_code.len) {
2804 ret = il3945_read_ucode(il);
2805 if (ret) {
2806 IL_ERR("Could not read microcode: %d\n", ret);
2807 mutex_unlock(&il->mutex);
2808 goto out_release_irq;
2809 }
2810 }
2811
2812 ret = __il3945_up(il);
2813
2814 mutex_unlock(&il->mutex);
2815
2816 if (ret)
2817 goto out_release_irq;
2818
2819 D_INFO("Start UP work.\n");
2820
2821
2822
2823 ret = wait_event_timeout(il->wait_command_queue,
2824 test_bit(S_READY, &il->status),
2825 UCODE_READY_TIMEOUT);
2826 if (!ret) {
2827 if (!test_bit(S_READY, &il->status)) {
2828 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2829 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2830 ret = -ETIMEDOUT;
2831 goto out_release_irq;
2832 }
2833 }
2834
2835
2836
2837 cancel_delayed_work(&il->_3945.rfkill_poll);
2838
2839 il->is_open = 1;
2840 D_MAC80211("leave\n");
2841 return 0;
2842
2843out_release_irq:
2844 il->is_open = 0;
2845 D_MAC80211("leave - failed\n");
2846 return ret;
2847}
2848
2849static void
2850il3945_mac_stop(struct ieee80211_hw *hw)
2851{
2852 struct il_priv *il = hw->priv;
2853
2854 D_MAC80211("enter\n");
2855
2856 if (!il->is_open) {
2857 D_MAC80211("leave - skip\n");
2858 return;
2859 }
2860
2861 il->is_open = 0;
2862
2863 il3945_down(il);
2864
2865 flush_workqueue(il->workqueue);
2866
2867
2868 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2869 round_jiffies_relative(2 * HZ));
2870
2871 D_MAC80211("leave\n");
2872}
2873
2874static void
2875il3945_mac_tx(struct ieee80211_hw *hw,
2876 struct ieee80211_tx_control *control,
2877 struct sk_buff *skb)
2878{
2879 struct il_priv *il = hw->priv;
2880
2881 D_MAC80211("enter\n");
2882
2883 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2884 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2885
2886 if (il3945_tx_skb(il, control->sta, skb))
2887 dev_kfree_skb_any(skb);
2888
2889 D_MAC80211("leave\n");
2890}
2891
2892void
2893il3945_config_ap(struct il_priv *il)
2894{
2895 struct ieee80211_vif *vif = il->vif;
2896 int rc = 0;
2897
2898 if (test_bit(S_EXIT_PENDING, &il->status))
2899 return;
2900
2901
2902 if (!(il_is_associated(il))) {
2903
2904
2905 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2906 il3945_commit_rxon(il);
2907
2908
2909 rc = il_send_rxon_timing(il);
2910 if (rc)
2911 IL_WARN("C_RXON_TIMING failed - "
2912 "Attempting to continue.\n");
2913
2914 il->staging.assoc_id = 0;
2915
2916 if (vif->bss_conf.use_short_preamble)
2917 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2918 else
2919 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2920
2921 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2922 if (vif->bss_conf.use_short_slot)
2923 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2924 else
2925 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2926 }
2927
2928 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2929 il3945_commit_rxon(il);
2930 }
2931 il3945_send_beacon_cmd(il);
2932}
2933
2934static int
2935il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2936 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2937 struct ieee80211_key_conf *key)
2938{
2939 struct il_priv *il = hw->priv;
2940 int ret = 0;
2941 u8 sta_id = IL_INVALID_STATION;
2942 u8 static_key;
2943
2944 D_MAC80211("enter\n");
2945
2946 if (il3945_mod_params.sw_crypto) {
2947 D_MAC80211("leave - hwcrypto disabled\n");
2948 return -EOPNOTSUPP;
2949 }
2950
2951
2952
2953
2954
2955 if (vif->type == NL80211_IFTYPE_ADHOC &&
2956 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2957 D_MAC80211("leave - IBSS RSN\n");
2958 return -EOPNOTSUPP;
2959 }
2960
2961 static_key = !il_is_associated(il);
2962
2963 if (!static_key) {
2964 sta_id = il_sta_id_or_broadcast(il, sta);
2965 if (sta_id == IL_INVALID_STATION) {
2966 D_MAC80211("leave - station not found\n");
2967 return -EINVAL;
2968 }
2969 }
2970
2971 mutex_lock(&il->mutex);
2972 il_scan_cancel_timeout(il, 100);
2973
2974 switch (cmd) {
2975 case SET_KEY:
2976 if (static_key)
2977 ret = il3945_set_static_key(il, key);
2978 else
2979 ret = il3945_set_dynamic_key(il, key, sta_id);
2980 D_MAC80211("enable hwcrypto key\n");
2981 break;
2982 case DISABLE_KEY:
2983 if (static_key)
2984 ret = il3945_remove_static_key(il);
2985 else
2986 ret = il3945_clear_sta_key_info(il, sta_id);
2987 D_MAC80211("disable hwcrypto key\n");
2988 break;
2989 default:
2990 ret = -EINVAL;
2991 }
2992
2993 D_MAC80211("leave ret %d\n", ret);
2994 mutex_unlock(&il->mutex);
2995
2996 return ret;
2997}
2998
2999static int
3000il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3001 struct ieee80211_sta *sta)
3002{
3003 struct il_priv *il = hw->priv;
3004 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
3005 int ret;
3006 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3007 u8 sta_id;
3008
3009 mutex_lock(&il->mutex);
3010 D_INFO("station %pM\n", sta->addr);
3011 sta_priv->common.sta_id = IL_INVALID_STATION;
3012
3013 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
3014 if (ret) {
3015 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
3016
3017 mutex_unlock(&il->mutex);
3018 return ret;
3019 }
3020
3021 sta_priv->common.sta_id = sta_id;
3022
3023
3024 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
3025 il3945_rs_rate_init(il, sta, sta_id);
3026 mutex_unlock(&il->mutex);
3027
3028 return 0;
3029}
3030
3031static void
3032il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3033 unsigned int *total_flags, u64 multicast)
3034{
3035 struct il_priv *il = hw->priv;
3036 __le32 filter_or = 0, filter_nand = 0;
3037
3038#define CHK(test, flag) do { \
3039 if (*total_flags & (test)) \
3040 filter_or |= (flag); \
3041 else \
3042 filter_nand |= (flag); \
3043 } while (0)
3044
3045 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3046 *total_flags);
3047
3048 CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
3049 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3050 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3051
3052#undef CHK
3053
3054 mutex_lock(&il->mutex);
3055
3056 il->staging.filter_flags &= ~filter_nand;
3057 il->staging.filter_flags |= filter_or;
3058
3059
3060
3061
3062
3063
3064
3065 mutex_unlock(&il->mutex);
3066
3067
3068
3069
3070
3071
3072
3073 *total_flags &=
3074 FIF_OTHER_BSS | FIF_ALLMULTI |
3075 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3076}
3077
3078
3079
3080
3081
3082
3083
3084#ifdef CONFIG_IWLEGACY_DEBUG
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097static ssize_t
3098il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3099 char *buf)
3100{
3101 struct il_priv *il = dev_get_drvdata(d);
3102 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3103}
3104
3105static ssize_t
3106il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3107 const char *buf, size_t count)
3108{
3109 struct il_priv *il = dev_get_drvdata(d);
3110 unsigned long val;
3111 int ret;
3112
3113 ret = kstrtoul(buf, 0, &val);
3114 if (ret)
3115 IL_INFO("%s is not in hex or decimal form.\n", buf);
3116 else
3117 il->debug_level = val;
3118
3119 return strnlen(buf, count);
3120}
3121
3122static DEVICE_ATTR(debug_level, 0644, il3945_show_debug_level,
3123 il3945_store_debug_level);
3124
3125#endif
3126
3127static ssize_t
3128il3945_show_temperature(struct device *d, struct device_attribute *attr,
3129 char *buf)
3130{
3131 struct il_priv *il = dev_get_drvdata(d);
3132
3133 if (!il_is_alive(il))
3134 return -EAGAIN;
3135
3136 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3137}
3138
3139static DEVICE_ATTR(temperature, 0444, il3945_show_temperature, NULL);
3140
3141static ssize_t
3142il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
3143{
3144 struct il_priv *il = dev_get_drvdata(d);
3145 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3146}
3147
3148static ssize_t
3149il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3150 const char *buf, size_t count)
3151{
3152 struct il_priv *il = dev_get_drvdata(d);
3153 char *p = (char *)buf;
3154 u32 val;
3155
3156 val = simple_strtoul(p, &p, 10);
3157 if (p == buf)
3158 IL_INFO(": %s is not in decimal form.\n", buf);
3159 else
3160 il3945_hw_reg_set_txpower(il, val);
3161
3162 return count;
3163}
3164
3165static DEVICE_ATTR(tx_power, 0644, il3945_show_tx_power, il3945_store_tx_power);
3166
3167static ssize_t
3168il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
3169{
3170 struct il_priv *il = dev_get_drvdata(d);
3171
3172 return sprintf(buf, "0x%04X\n", il->active.flags);
3173}
3174
3175static ssize_t
3176il3945_store_flags(struct device *d, struct device_attribute *attr,
3177 const char *buf, size_t count)
3178{
3179 struct il_priv *il = dev_get_drvdata(d);
3180 u32 flags = simple_strtoul(buf, NULL, 0);
3181
3182 mutex_lock(&il->mutex);
3183 if (le32_to_cpu(il->staging.flags) != flags) {
3184
3185 if (il_scan_cancel_timeout(il, 100))
3186 IL_WARN("Could not cancel scan.\n");
3187 else {
3188 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
3189 il->staging.flags = cpu_to_le32(flags);
3190 il3945_commit_rxon(il);
3191 }
3192 }
3193 mutex_unlock(&il->mutex);
3194
3195 return count;
3196}
3197
3198static DEVICE_ATTR(flags, 0644, il3945_show_flags, il3945_store_flags);
3199
3200static ssize_t
3201il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3202 char *buf)
3203{
3204 struct il_priv *il = dev_get_drvdata(d);
3205
3206 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3207}
3208
3209static ssize_t
3210il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3211 const char *buf, size_t count)
3212{
3213 struct il_priv *il = dev_get_drvdata(d);
3214 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3215
3216 mutex_lock(&il->mutex);
3217 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3218
3219 if (il_scan_cancel_timeout(il, 100))
3220 IL_WARN("Could not cancel scan.\n");
3221 else {
3222 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3223 filter_flags);
3224 il->staging.filter_flags = cpu_to_le32(filter_flags);
3225 il3945_commit_rxon(il);
3226 }
3227 }
3228 mutex_unlock(&il->mutex);
3229
3230 return count;
3231}
3232
3233static DEVICE_ATTR(filter_flags, 0644, il3945_show_filter_flags,
3234 il3945_store_filter_flags);
3235
3236static ssize_t
3237il3945_show_measurement(struct device *d, struct device_attribute *attr,
3238 char *buf)
3239{
3240 struct il_priv *il = dev_get_drvdata(d);
3241 struct il_spectrum_notification measure_report;
3242 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3243 u8 *data = (u8 *) &measure_report;
3244 unsigned long flags;
3245
3246 spin_lock_irqsave(&il->lock, flags);
3247 if (!(il->measurement_status & MEASUREMENT_READY)) {
3248 spin_unlock_irqrestore(&il->lock, flags);
3249 return 0;
3250 }
3251 memcpy(&measure_report, &il->measure_report, size);
3252 il->measurement_status = 0;
3253 spin_unlock_irqrestore(&il->lock, flags);
3254
3255 while (size && PAGE_SIZE - len) {
3256 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3257 PAGE_SIZE - len, true);
3258 len = strlen(buf);
3259 if (PAGE_SIZE - len)
3260 buf[len++] = '\n';
3261
3262 ofs += 16;
3263 size -= min(size, 16U);
3264 }
3265
3266 return len;
3267}
3268
3269static ssize_t
3270il3945_store_measurement(struct device *d, struct device_attribute *attr,
3271 const char *buf, size_t count)
3272{
3273 struct il_priv *il = dev_get_drvdata(d);
3274 struct ieee80211_measurement_params params = {
3275 .channel = le16_to_cpu(il->active.channel),
3276 .start_time = cpu_to_le64(il->_3945.last_tsf),
3277 .duration = cpu_to_le16(1),
3278 };
3279 u8 type = IL_MEASURE_BASIC;
3280 u8 buffer[32];
3281 u8 channel;
3282
3283 if (count) {
3284 char *p = buffer;
3285 strlcpy(buffer, buf, sizeof(buffer));
3286 channel = simple_strtoul(p, NULL, 0);
3287 if (channel)
3288 params.channel = channel;
3289
3290 p = buffer;
3291 while (*p && *p != ' ')
3292 p++;
3293 if (*p)
3294 type = simple_strtoul(p + 1, NULL, 0);
3295 }
3296
3297 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3298 type, params.channel, buf);
3299 il3945_get_measurement(il, ¶ms, type);
3300
3301 return count;
3302}
3303
3304static DEVICE_ATTR(measurement, 0600, il3945_show_measurement,
3305 il3945_store_measurement);
3306
3307static ssize_t
3308il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3309 const char *buf, size_t count)
3310{
3311 struct il_priv *il = dev_get_drvdata(d);
3312
3313 il->retry_rate = simple_strtoul(buf, NULL, 0);
3314 if (il->retry_rate <= 0)
3315 il->retry_rate = 1;
3316
3317 return count;
3318}
3319
3320static ssize_t
3321il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3322 char *buf)
3323{
3324 struct il_priv *il = dev_get_drvdata(d);
3325 return sprintf(buf, "%d", il->retry_rate);
3326}
3327
3328static DEVICE_ATTR(retry_rate, 0600, il3945_show_retry_rate,
3329 il3945_store_retry_rate);
3330
3331static ssize_t
3332il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
3333{
3334
3335 return 0;
3336}
3337
3338static DEVICE_ATTR(channels, 0400, il3945_show_channels, NULL);
3339
3340static ssize_t
3341il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
3342{
3343 struct il_priv *il = dev_get_drvdata(d);
3344
3345 if (!il_is_alive(il))
3346 return -EAGAIN;
3347
3348 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
3349}
3350
3351static ssize_t
3352il3945_store_antenna(struct device *d, struct device_attribute *attr,
3353 const char *buf, size_t count)
3354{
3355 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3356 int ant;
3357
3358 if (count == 0)
3359 return 0;
3360
3361 if (sscanf(buf, "%1i", &ant) != 1) {
3362 D_INFO("not in hex or decimal form.\n");
3363 return count;
3364 }
3365
3366 if (ant >= 0 && ant <= 2) {
3367 D_INFO("Setting antenna select to %d.\n", ant);
3368 il3945_mod_params.antenna = (enum il3945_antenna)ant;
3369 } else
3370 D_INFO("Bad antenna select value %d.\n", ant);
3371
3372 return count;
3373}
3374
3375static DEVICE_ATTR(antenna, 0644, il3945_show_antenna, il3945_store_antenna);
3376
3377static ssize_t
3378il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
3379{
3380 struct il_priv *il = dev_get_drvdata(d);
3381 if (!il_is_alive(il))
3382 return -EAGAIN;
3383 return sprintf(buf, "0x%08x\n", (int)il->status);
3384}
3385
3386static DEVICE_ATTR(status, 0444, il3945_show_status, NULL);
3387
3388static ssize_t
3389il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3390 const char *buf, size_t count)
3391{
3392 struct il_priv *il = dev_get_drvdata(d);
3393 char *p = (char *)buf;
3394
3395 if (p[0] == '1')
3396 il3945_dump_nic_error_log(il);
3397
3398 return strnlen(buf, count);
3399}
3400
3401static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log);
3402
3403
3404
3405
3406
3407
3408
3409static void
3410il3945_setup_deferred_work(struct il_priv *il)
3411{
3412 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3413
3414 init_waitqueue_head(&il->wait_command_queue);
3415
3416 INIT_WORK(&il->restart, il3945_bg_restart);
3417 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3418 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3419 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3420 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3421
3422 il_setup_scan_deferred_work(il);
3423
3424 il3945_hw_setup_deferred_work(il);
3425
3426 timer_setup(&il->watchdog, il_bg_watchdog, 0);
3427
3428 tasklet_init(&il->irq_tasklet,
3429 (void (*)(unsigned long))il3945_irq_tasklet,
3430 (unsigned long)il);
3431}
3432
3433static void
3434il3945_cancel_deferred_work(struct il_priv *il)
3435{
3436 il3945_hw_cancel_deferred_work(il);
3437
3438 cancel_delayed_work_sync(&il->init_alive_start);
3439 cancel_delayed_work(&il->alive_start);
3440
3441 il_cancel_scan_deferred_work(il);
3442}
3443
3444static struct attribute *il3945_sysfs_entries[] = {
3445 &dev_attr_antenna.attr,
3446 &dev_attr_channels.attr,
3447 &dev_attr_dump_errors.attr,
3448 &dev_attr_flags.attr,
3449 &dev_attr_filter_flags.attr,
3450 &dev_attr_measurement.attr,
3451 &dev_attr_retry_rate.attr,
3452 &dev_attr_status.attr,
3453 &dev_attr_temperature.attr,
3454 &dev_attr_tx_power.attr,
3455#ifdef CONFIG_IWLEGACY_DEBUG
3456 &dev_attr_debug_level.attr,
3457#endif
3458 NULL
3459};
3460
3461static const struct attribute_group il3945_attribute_group = {
3462 .name = NULL,
3463 .attrs = il3945_sysfs_entries,
3464};
3465
3466static struct ieee80211_ops il3945_mac_ops __ro_after_init = {
3467 .tx = il3945_mac_tx,
3468 .start = il3945_mac_start,
3469 .stop = il3945_mac_stop,
3470 .add_interface = il_mac_add_interface,
3471 .remove_interface = il_mac_remove_interface,
3472 .change_interface = il_mac_change_interface,
3473 .config = il_mac_config,
3474 .configure_filter = il3945_configure_filter,
3475 .set_key = il3945_mac_set_key,
3476 .conf_tx = il_mac_conf_tx,
3477 .reset_tsf = il_mac_reset_tsf,
3478 .bss_info_changed = il_mac_bss_info_changed,
3479 .hw_scan = il_mac_hw_scan,
3480 .sta_add = il3945_mac_sta_add,
3481 .sta_remove = il_mac_sta_remove,
3482 .tx_last_beacon = il_mac_tx_last_beacon,
3483 .flush = il_mac_flush,
3484};
3485
3486static int
3487il3945_init_drv(struct il_priv *il)
3488{
3489 int ret;
3490 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3491
3492 il->retry_rate = 1;
3493 il->beacon_skb = NULL;
3494
3495 spin_lock_init(&il->sta_lock);
3496 spin_lock_init(&il->hcmd_lock);
3497
3498 INIT_LIST_HEAD(&il->free_frames);
3499
3500 mutex_init(&il->mutex);
3501
3502 il->ieee_channels = NULL;
3503 il->ieee_rates = NULL;
3504 il->band = NL80211_BAND_2GHZ;
3505
3506 il->iw_mode = NL80211_IFTYPE_STATION;
3507 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3508
3509
3510 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3511
3512 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3513 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
3514 eeprom->version);
3515 ret = -EINVAL;
3516 goto err;
3517 }
3518 ret = il_init_channel_map(il);
3519 if (ret) {
3520 IL_ERR("initializing regulatory failed: %d\n", ret);
3521 goto err;
3522 }
3523
3524
3525 if (il3945_txpower_set_from_eeprom(il)) {
3526 ret = -EIO;
3527 goto err_free_channel_map;
3528 }
3529
3530 ret = il_init_geos(il);
3531 if (ret) {
3532 IL_ERR("initializing geos failed: %d\n", ret);
3533 goto err_free_channel_map;
3534 }
3535 il3945_init_hw_rates(il, il->ieee_rates);
3536
3537 return 0;
3538
3539err_free_channel_map:
3540 il_free_channel_map(il);
3541err:
3542 return ret;
3543}
3544
3545#define IL3945_MAX_PROBE_REQUEST 200
3546
3547static int
3548il3945_setup_mac(struct il_priv *il)
3549{
3550 int ret;
3551 struct ieee80211_hw *hw = il->hw;
3552
3553 hw->rate_control_algorithm = "iwl-3945-rs";
3554 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3555 hw->vif_data_size = sizeof(struct il_vif_priv);
3556
3557
3558 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3559 ieee80211_hw_set(hw, SUPPORTS_PS);
3560 ieee80211_hw_set(hw, SIGNAL_DBM);
3561 ieee80211_hw_set(hw, SPECTRUM_MGMT);
3562
3563 hw->wiphy->interface_modes =
3564 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
3565
3566 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
3567 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
3568 REGULATORY_DISABLE_BEACON_HINTS;
3569
3570 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3571
3572 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3573
3574 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
3575
3576
3577 hw->queues = 4;
3578
3579 if (il->bands[NL80211_BAND_2GHZ].n_channels)
3580 il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3581 &il->bands[NL80211_BAND_2GHZ];
3582
3583 if (il->bands[NL80211_BAND_5GHZ].n_channels)
3584 il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3585 &il->bands[NL80211_BAND_5GHZ];
3586
3587 il_leds_init(il);
3588
3589 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3590
3591 ret = ieee80211_register_hw(il->hw);
3592 if (ret) {
3593 IL_ERR("Failed to register hw (error %d)\n", ret);
3594 return ret;
3595 }
3596 il->mac80211_registered = 1;
3597
3598 return 0;
3599}
3600
3601static int
3602il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3603{
3604 int err = 0;
3605 struct il_priv *il;
3606 struct ieee80211_hw *hw;
3607 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3608 struct il3945_eeprom *eeprom;
3609 unsigned long flags;
3610
3611
3612
3613
3614
3615 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3616 if (!hw) {
3617 err = -ENOMEM;
3618 goto out;
3619 }
3620 il = hw->priv;
3621 il->hw = hw;
3622 SET_IEEE80211_DEV(hw, &pdev->dev);
3623
3624 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3625
3626 D_INFO("*** LOAD DRIVER ***\n");
3627 il->cfg = cfg;
3628 il->ops = &il3945_ops;
3629#ifdef CONFIG_IWLEGACY_DEBUGFS
3630 il->debugfs_ops = &il3945_debugfs_ops;
3631#endif
3632 il->pci_dev = pdev;
3633 il->inta_mask = CSR_INI_SET_MASK;
3634
3635
3636
3637
3638 pci_disable_link_state(pdev,
3639 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3640 PCIE_LINK_STATE_CLKPM);
3641
3642 if (pci_enable_device(pdev)) {
3643 err = -ENODEV;
3644 goto out_ieee80211_free_hw;
3645 }
3646
3647 pci_set_master(pdev);
3648
3649 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3650 if (!err)
3651 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3652 if (err) {
3653 IL_WARN("No suitable DMA available.\n");
3654 goto out_pci_disable_device;
3655 }
3656
3657 pci_set_drvdata(pdev, il);
3658 err = pci_request_regions(pdev, DRV_NAME);
3659 if (err)
3660 goto out_pci_disable_device;
3661
3662
3663
3664
3665 il->hw_base = pci_ioremap_bar(pdev, 0);
3666 if (!il->hw_base) {
3667 err = -ENODEV;
3668 goto out_pci_release_regions;
3669 }
3670
3671 D_INFO("pci_resource_len = 0x%08llx\n",
3672 (unsigned long long)pci_resource_len(pdev, 0));
3673 D_INFO("pci_resource_base = %p\n", il->hw_base);
3674
3675
3676
3677 pci_write_config_byte(pdev, 0x41, 0x00);
3678
3679
3680
3681
3682 spin_lock_init(&il->reg_lock);
3683 spin_lock_init(&il->lock);
3684
3685
3686
3687
3688
3689
3690 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3691
3692
3693
3694
3695
3696
3697 err = il_eeprom_init(il);
3698 if (err) {
3699 IL_ERR("Unable to init EEPROM\n");
3700 goto out_iounmap;
3701 }
3702
3703 eeprom = (struct il3945_eeprom *)il->eeprom;
3704 D_INFO("MAC address: %pM\n", eeprom->mac_address);
3705 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3706
3707
3708
3709
3710
3711 err = il3945_hw_set_hw_params(il);
3712 if (err) {
3713 IL_ERR("failed to set hw settings\n");
3714 goto out_eeprom_free;
3715 }
3716
3717
3718
3719
3720
3721 err = il3945_init_drv(il);
3722 if (err) {
3723 IL_ERR("initializing driver failed\n");
3724 goto out_unset_hw_params;
3725 }
3726
3727 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3728
3729
3730
3731
3732
3733 spin_lock_irqsave(&il->lock, flags);
3734 il_disable_interrupts(il);
3735 spin_unlock_irqrestore(&il->lock, flags);
3736
3737 pci_enable_msi(il->pci_dev);
3738
3739 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3740 if (err) {
3741 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3742 goto out_disable_msi;
3743 }
3744
3745 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
3746 if (err) {
3747 IL_ERR("failed to create sysfs device attributes\n");
3748 goto out_release_irq;
3749 }
3750
3751 il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3752 il3945_setup_deferred_work(il);
3753 il3945_setup_handlers(il);
3754 il_power_initialize(il);
3755
3756
3757
3758
3759
3760 il_enable_interrupts(il);
3761
3762 err = il3945_setup_mac(il);
3763 if (err)
3764 goto out_remove_sysfs;
3765
3766 err = il_dbgfs_register(il, DRV_NAME);
3767 if (err)
3768 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
3769 err);
3770
3771
3772 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3773
3774 return 0;
3775
3776out_remove_sysfs:
3777 destroy_workqueue(il->workqueue);
3778 il->workqueue = NULL;
3779 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3780out_release_irq:
3781 free_irq(il->pci_dev->irq, il);
3782out_disable_msi:
3783 pci_disable_msi(il->pci_dev);
3784 il_free_geos(il);
3785 il_free_channel_map(il);
3786out_unset_hw_params:
3787 il3945_unset_hw_params(il);
3788out_eeprom_free:
3789 il_eeprom_free(il);
3790out_iounmap:
3791 iounmap(il->hw_base);
3792out_pci_release_regions:
3793 pci_release_regions(pdev);
3794out_pci_disable_device:
3795 pci_disable_device(pdev);
3796out_ieee80211_free_hw:
3797 ieee80211_free_hw(il->hw);
3798out:
3799 return err;
3800}
3801
3802static void
3803il3945_pci_remove(struct pci_dev *pdev)
3804{
3805 struct il_priv *il = pci_get_drvdata(pdev);
3806 unsigned long flags;
3807
3808 if (!il)
3809 return;
3810
3811 D_INFO("*** UNLOAD DRIVER ***\n");
3812
3813 il_dbgfs_unregister(il);
3814
3815 set_bit(S_EXIT_PENDING, &il->status);
3816
3817 il_leds_exit(il);
3818
3819 if (il->mac80211_registered) {
3820 ieee80211_unregister_hw(il->hw);
3821 il->mac80211_registered = 0;
3822 } else {
3823 il3945_down(il);
3824 }
3825
3826
3827
3828
3829
3830
3831
3832
3833 il_apm_stop(il);
3834
3835
3836
3837
3838 spin_lock_irqsave(&il->lock, flags);
3839 il_disable_interrupts(il);
3840 spin_unlock_irqrestore(&il->lock, flags);
3841
3842 il3945_synchronize_irq(il);
3843
3844 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3845
3846 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3847
3848 il3945_dealloc_ucode_pci(il);
3849
3850 if (il->rxq.bd)
3851 il3945_rx_queue_free(il, &il->rxq);
3852 il3945_hw_txq_ctx_free(il);
3853
3854 il3945_unset_hw_params(il);
3855
3856
3857 flush_workqueue(il->workqueue);
3858
3859
3860
3861
3862 destroy_workqueue(il->workqueue);
3863 il->workqueue = NULL;
3864
3865 free_irq(pdev->irq, il);
3866 pci_disable_msi(pdev);
3867
3868 iounmap(il->hw_base);
3869 pci_release_regions(pdev);
3870 pci_disable_device(pdev);
3871
3872 il_free_channel_map(il);
3873 il_free_geos(il);
3874 kfree(il->scan_cmd);
3875 dev_kfree_skb(il->beacon_skb);
3876 ieee80211_free_hw(il->hw);
3877}
3878
3879
3880
3881
3882
3883
3884
3885static struct pci_driver il3945_driver = {
3886 .name = DRV_NAME,
3887 .id_table = il3945_hw_card_ids,
3888 .probe = il3945_pci_probe,
3889 .remove = il3945_pci_remove,
3890 .driver.pm = IL_LEGACY_PM_OPS,
3891};
3892
3893static int __init
3894il3945_init(void)
3895{
3896
3897 int ret;
3898 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3899 pr_info(DRV_COPYRIGHT "\n");
3900
3901
3902
3903
3904
3905 if (il3945_mod_params.disable_hw_scan) {
3906 pr_info("hw_scan is disabled\n");
3907 il3945_mac_ops.hw_scan = NULL;
3908 }
3909
3910 ret = il3945_rate_control_register();
3911 if (ret) {
3912 pr_err("Unable to register rate control algorithm: %d\n", ret);
3913 return ret;
3914 }
3915
3916 ret = pci_register_driver(&il3945_driver);
3917 if (ret) {
3918 pr_err("Unable to initialize PCI module\n");
3919 goto error_register;
3920 }
3921
3922 return ret;
3923
3924error_register:
3925 il3945_rate_control_unregister();
3926 return ret;
3927}
3928
3929static void __exit
3930il3945_exit(void)
3931{
3932 pci_unregister_driver(&il3945_driver);
3933 il3945_rate_control_unregister();
3934}
3935
3936MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
3937
3938module_param_named(antenna, il3945_mod_params.antenna, int, 0444);
3939MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3940module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, 0444);
3941MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3942module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3943 0444);
3944MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
3945#ifdef CONFIG_IWLEGACY_DEBUG
3946module_param_named(debug, il_debug_level, uint, 0644);
3947MODULE_PARM_DESC(debug, "debug output mask");
3948#endif
3949module_param_named(fw_restart, il3945_mod_params.restart_fw, int, 0444);
3950MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3951
3952module_exit(il3945_exit);
3953module_init(il3945_init);
3954