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24
25#define pr_fmt(fmt) "intel_mid_thermal: " fmt
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/err.h>
30#include <linux/param.h>
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/slab.h>
34#include <linux/pm.h>
35#include <linux/thermal.h>
36#include <linux/mfd/intel_msic.h>
37
38
39#define MSIC_THERMAL_SENSORS 4
40
41
42#define MSIC_ADC_ENBL 0x10
43#define MSIC_ADC_START 0x08
44
45#define MSIC_ADCTHERM_ENBL 0x04
46#define MSIC_ADCRRDATA_ENBL 0x05
47#define MSIC_CHANL_MASK_VAL 0x0F
48
49#define MSIC_STOPBIT_MASK 16
50#define MSIC_ADCTHERM_MASK 4
51
52#define ADC_CHANLS_MAX 15
53#define ADC_LOOP_MAX (ADC_CHANLS_MAX - MSIC_THERMAL_SENSORS)
54
55
56#define SKIN_SENSOR0_CODE 0x08
57#define SKIN_SENSOR1_CODE 0x09
58#define SYS_SENSOR_CODE 0x0A
59#define MSIC_DIE_SENSOR_CODE 0x03
60
61#define SKIN_THERM_SENSOR0 0
62#define SKIN_THERM_SENSOR1 1
63#define SYS_THERM_SENSOR2 2
64#define MSIC_DIE_THERM_SENSOR3 3
65
66
67#define ADC_MAX 977
68#define ADC_MIN 162
69#define ADC_VAL0C 887
70#define ADC_VAL20C 720
71#define ADC_VAL40C 508
72#define ADC_VAL60C 315
73
74
75#define ADC_CHNL_START_ADDR INTEL_MSIC_ADC1ADDR0
76#define ADC_DATA_START_ADDR INTEL_MSIC_ADC1SNS0H
77
78
79#define MSIC_DIE_ADC_MIN 488
80#define MSIC_DIE_ADC_MAX 1004
81
82
83
84
85static int channel_index;
86
87struct platform_info {
88 struct platform_device *pdev;
89 struct thermal_zone_device *tzd[MSIC_THERMAL_SENSORS];
90};
91
92struct thermal_device_info {
93 unsigned int chnl_addr;
94 int direct;
95
96 long curr_temp;
97};
98
99
100
101
102
103
104
105static int to_msic_die_temp(uint16_t adc_val)
106{
107 return (368 * (adc_val) / 1000) - 220;
108}
109
110
111
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114
115
116
117static int is_valid_adc(uint16_t adc_val, uint16_t min, uint16_t max)
118{
119 return (adc_val >= min) && (adc_val <= max);
120}
121
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133
134
135static int adc_to_temp(int direct, uint16_t adc_val, int *tp)
136{
137 int temp;
138
139
140 if (direct) {
141 if (is_valid_adc(adc_val, MSIC_DIE_ADC_MIN, MSIC_DIE_ADC_MAX)) {
142 *tp = to_msic_die_temp(adc_val) * 1000;
143 return 0;
144 }
145 return -ERANGE;
146 }
147
148 if (!is_valid_adc(adc_val, ADC_MIN, ADC_MAX))
149 return -ERANGE;
150
151
152 if (adc_val > ADC_VAL0C)
153 temp = 177 - (adc_val/5);
154 else if ((adc_val <= ADC_VAL0C) && (adc_val > ADC_VAL20C))
155 temp = 111 - (adc_val/8);
156 else if ((adc_val <= ADC_VAL20C) && (adc_val > ADC_VAL40C))
157 temp = 92 - (adc_val/10);
158 else if ((adc_val <= ADC_VAL40C) && (adc_val > ADC_VAL60C))
159 temp = 91 - (adc_val/10);
160 else
161 temp = 112 - (adc_val/6);
162
163
164 *tp = temp * 1000;
165 return 0;
166}
167
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174
175
176
177static int mid_read_temp(struct thermal_zone_device *tzd, int *temp)
178{
179 struct thermal_device_info *td_info = tzd->devdata;
180 uint16_t adc_val, addr;
181 uint8_t data = 0;
182 int ret;
183 int curr_temp;
184
185 addr = td_info->chnl_addr;
186
187
188 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCRRDATA_ENBL);
189 if (ret)
190 return ret;
191
192
193 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCTHERM_ENBL);
194 if (ret)
195 return ret;
196
197
198 ret = intel_msic_reg_read(addr, &data);
199 if (ret)
200 return ret;
201
202
203 adc_val = (data << 2);
204 addr++;
205
206 ret = intel_msic_reg_read(addr, &data);
207 if (ret)
208 return ret;
209
210
211 data &= 03;
212 adc_val += data;
213
214
215 ret = adc_to_temp(td_info->direct, adc_val, &curr_temp);
216 if (ret == 0)
217 *temp = td_info->curr_temp = curr_temp;
218 return ret;
219}
220
221
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224
225
226
227
228
229static int configure_adc(int val)
230{
231 int ret;
232 uint8_t data;
233
234 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
235 if (ret)
236 return ret;
237
238 if (val) {
239
240 data |= (MSIC_ADC_ENBL | MSIC_ADC_START);
241 } else {
242
243 data &= (~MSIC_ADC_START);
244 }
245 return intel_msic_reg_write(INTEL_MSIC_ADC1CNTL1, data);
246}
247
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252
253
254
255
256static int set_up_therm_channel(u16 base_addr)
257{
258 int ret;
259
260
261 ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE);
262 if (ret)
263 return ret;
264
265 ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE);
266 if (ret)
267 return ret;
268
269 ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE);
270 if (ret)
271 return ret;
272
273
274
275 ret = intel_msic_reg_write(base_addr + 3,
276 (MSIC_DIE_SENSOR_CODE | 0x10));
277 if (ret)
278 return ret;
279
280
281 return configure_adc(1);
282}
283
284
285
286
287
288
289
290static int reset_stopbit(uint16_t addr)
291{
292 int ret;
293 uint8_t data;
294 ret = intel_msic_reg_read(addr, &data);
295 if (ret)
296 return ret;
297
298 return intel_msic_reg_write(addr, (data & 0xEF));
299}
300
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311
312
313
314static int find_free_channel(void)
315{
316 int ret;
317 int i;
318 uint8_t data;
319
320
321 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
322 if (ret)
323 return ret;
324
325 if ((data & MSIC_ADC_ENBL) == 0)
326 return 0;
327
328
329 for (i = 0; i < ADC_CHANLS_MAX; i++) {
330 ret = intel_msic_reg_read(ADC_CHNL_START_ADDR + i, &data);
331 if (ret)
332 return ret;
333
334 if (data & MSIC_STOPBIT_MASK) {
335 ret = i;
336 break;
337 }
338 }
339 return (ret > ADC_LOOP_MAX) ? (-EINVAL) : ret;
340}
341
342
343
344
345
346
347
348static int mid_initialize_adc(struct device *dev)
349{
350 u8 data;
351 u16 base_addr;
352 int ret;
353
354
355
356
357
358 ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL3, &data);
359 if (ret)
360 return ret;
361
362 data &= ~MSIC_ADCTHERM_MASK;
363 ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, data);
364 if (ret)
365 return ret;
366
367
368 channel_index = find_free_channel();
369 if (channel_index < 0) {
370 dev_err(dev, "No free ADC channels");
371 return channel_index;
372 }
373
374 base_addr = ADC_CHNL_START_ADDR + channel_index;
375
376 if (!(channel_index == 0 || channel_index == ADC_LOOP_MAX)) {
377
378 ret = reset_stopbit(base_addr);
379 if (ret)
380 return ret;
381
382
383 base_addr++;
384 channel_index++;
385 }
386
387 ret = set_up_therm_channel(base_addr);
388 if (ret) {
389 dev_err(dev, "unable to enable ADC");
390 return ret;
391 }
392 dev_dbg(dev, "ADC initialization successful");
393 return ret;
394}
395
396
397
398
399
400
401
402static struct thermal_device_info *initialize_sensor(int index)
403{
404 struct thermal_device_info *td_info =
405 kzalloc(sizeof(struct thermal_device_info), GFP_KERNEL);
406
407 if (!td_info)
408 return NULL;
409
410
411 td_info->chnl_addr = ADC_DATA_START_ADDR + 2 * (channel_index + index);
412
413 if (index == 3)
414 td_info->direct = 1;
415 return td_info;
416}
417
418#ifdef CONFIG_PM_SLEEP
419
420
421
422
423
424
425static int mid_thermal_resume(struct device *dev)
426{
427 return mid_initialize_adc(dev);
428}
429
430
431
432
433
434
435
436
437static int mid_thermal_suspend(struct device *dev)
438{
439
440
441
442
443
444 return configure_adc(0);
445}
446#endif
447
448static SIMPLE_DEV_PM_OPS(mid_thermal_pm,
449 mid_thermal_suspend, mid_thermal_resume);
450
451
452
453
454
455
456
457static int read_curr_temp(struct thermal_zone_device *tzd, int *temp)
458{
459 WARN_ON(tzd == NULL);
460 return mid_read_temp(tzd, temp);
461}
462
463
464static struct thermal_zone_device_ops tzd_ops = {
465 .get_temp = read_curr_temp,
466};
467
468
469
470
471
472
473
474
475static int mid_thermal_probe(struct platform_device *pdev)
476{
477 static char *name[MSIC_THERMAL_SENSORS] = {
478 "skin0", "skin1", "sys", "msicdie"
479 };
480
481 int ret;
482 int i;
483 struct platform_info *pinfo;
484
485 pinfo = devm_kzalloc(&pdev->dev, sizeof(struct platform_info),
486 GFP_KERNEL);
487 if (!pinfo)
488 return -ENOMEM;
489
490
491 ret = mid_initialize_adc(&pdev->dev);
492 if (ret) {
493 dev_err(&pdev->dev, "ADC init failed");
494 return ret;
495 }
496
497
498 for (i = 0; i < MSIC_THERMAL_SENSORS; i++) {
499 struct thermal_device_info *td_info = initialize_sensor(i);
500
501 if (!td_info) {
502 ret = -ENOMEM;
503 goto err;
504 }
505 pinfo->tzd[i] = thermal_zone_device_register(name[i],
506 0, 0, td_info, &tzd_ops, NULL, 0, 0);
507 if (IS_ERR(pinfo->tzd[i])) {
508 kfree(td_info);
509 ret = PTR_ERR(pinfo->tzd[i]);
510 goto err;
511 }
512 ret = thermal_zone_device_enable(pinfo->tzd[i]);
513 if (ret) {
514 kfree(td_info);
515 thermal_zone_device_unregister(pinfo->tzd[i]);
516 goto err;
517 }
518 }
519
520 pinfo->pdev = pdev;
521 platform_set_drvdata(pdev, pinfo);
522 return 0;
523
524err:
525 while (--i >= 0) {
526 kfree(pinfo->tzd[i]->devdata);
527 thermal_zone_device_unregister(pinfo->tzd[i]);
528 }
529 configure_adc(0);
530 return ret;
531}
532
533
534
535
536
537
538
539
540static int mid_thermal_remove(struct platform_device *pdev)
541{
542 int i;
543 struct platform_info *pinfo = platform_get_drvdata(pdev);
544
545 for (i = 0; i < MSIC_THERMAL_SENSORS; i++) {
546 kfree(pinfo->tzd[i]->devdata);
547 thermal_zone_device_unregister(pinfo->tzd[i]);
548 }
549
550
551 return configure_adc(0);
552}
553
554#define DRIVER_NAME "msic_thermal"
555
556static const struct platform_device_id therm_id_table[] = {
557 { DRIVER_NAME, 1 },
558 { }
559};
560MODULE_DEVICE_TABLE(platform, therm_id_table);
561
562static struct platform_driver mid_thermal_driver = {
563 .driver = {
564 .name = DRIVER_NAME,
565 .pm = &mid_thermal_pm,
566 },
567 .probe = mid_thermal_probe,
568 .remove = mid_thermal_remove,
569 .id_table = therm_id_table,
570};
571
572module_platform_driver(mid_thermal_driver);
573
574MODULE_AUTHOR("Durgadoss R <durgadoss.r@intel.com>");
575MODULE_DESCRIPTION("Intel Medfield Platform Thermal Driver");
576MODULE_LICENSE("GPL");
577