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33#ifndef _AACRAID_H_
34#define _AACRAID_H_
35#ifndef dprintk
36# define dprintk(x)
37#endif
38
39#define _nblank(x) #x
40#define nblank(x) _nblank(x)[0]
41
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <scsi/scsi_host.h>
45
46
47
48
49
50#define AAC_MAX_MSIX 32
51#define AAC_PCI_MSI_ENABLE 0x8000
52
53enum {
54 AAC_ENABLE_INTERRUPT = 0x0,
55 AAC_DISABLE_INTERRUPT,
56 AAC_ENABLE_MSIX,
57 AAC_DISABLE_MSIX,
58 AAC_CLEAR_AIF_BIT,
59 AAC_CLEAR_SYNC_BIT,
60 AAC_ENABLE_INTX
61};
62
63#define AAC_INT_MODE_INTX (1<<0)
64#define AAC_INT_MODE_MSI (1<<1)
65#define AAC_INT_MODE_AIF (1<<2)
66#define AAC_INT_MODE_SYNC (1<<3)
67#define AAC_INT_MODE_MSIX (1<<16)
68
69#define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
70#define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
71#define AAC_INT_DISABLE_ALL 0xffffffff
72
73
74#define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
75#define PMC_IOARCB_TRANSFER_FAILED (1<<28)
76#define PMC_IOA_UNIT_CHECK (1<<27)
77#define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
78#define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
79#define PMC_IOARRIN_LOST (1<<4)
80#define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
81#define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
82#define PMC_HOST_RRQ_VALID (1<<1)
83#define PMC_OPERATIONAL_STATUS (1<<31)
84#define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
85
86#define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
87 PMC_IOA_UNIT_CHECK | \
88 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
89 PMC_IOARRIN_LOST | \
90 PMC_SYSTEM_BUS_MMIO_ERROR | \
91 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
92
93#define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
94 PMC_HOST_RRQ_VALID | \
95 PMC_TRANSITION_TO_OPERATIONAL | \
96 PMC_ALLOW_MSIX_VECTOR0)
97#define PMC_GLOBAL_INT_BIT2 0x00000004
98#define PMC_GLOBAL_INT_BIT0 0x00000001
99
100#ifndef AAC_DRIVER_BUILD
101# define AAC_DRIVER_BUILD 50877
102# define AAC_DRIVER_BRANCH "-custom"
103#endif
104#define MAXIMUM_NUM_CONTAINERS 32
105
106#define AAC_NUM_MGT_FIB 8
107#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
108#define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
109
110#define AAC_MAX_LUN 256
111
112#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
113#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
114
115#define AAC_DEBUG_INSTRUMENT_AIF_DELETE
116
117#define AAC_MAX_NATIVE_TARGETS 1024
118
119#define AAC_MAX_BUSES 5
120#define AAC_MAX_TARGETS 256
121#define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS)
122#define AAC_MAX_NATIVE_SIZE 2048
123#define FW_ERROR_BUFFER_SIZE 512
124
125#define get_bus_number(x) (x/AAC_MAX_TARGETS)
126#define get_target_number(x) (x%AAC_MAX_TARGETS)
127
128
129#define SA_AIF_HOTPLUG (1<<1)
130#define SA_AIF_HARDWARE (1<<2)
131#define SA_AIF_PDEV_CHANGE (1<<4)
132#define SA_AIF_LDEV_CHANGE (1<<5)
133#define SA_AIF_BPSTAT_CHANGE (1<<30)
134#define SA_AIF_BPCFG_CHANGE (1<<31)
135
136#define HBA_MAX_SG_EMBEDDED 28
137#define HBA_MAX_SG_SEPARATE 90
138#define HBA_SENSE_DATA_LEN_MAX 32
139#define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
140#define HBA_SGL_FLAGS_EXT 0x80000000UL
141
142struct aac_hba_sgl {
143 u32 addr_lo;
144 u32 addr_hi;
145 u32 len;
146 u32 flags;
147};
148
149enum {
150 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
151 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
152 HBA_IU_TYPE_SATA_REQ = 0x42,
153 HBA_IU_TYPE_RESP = 0x60,
154 HBA_IU_TYPE_COALESCED_RESP = 0x61,
155 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
156};
157
158enum {
159 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
160 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
161 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
162 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
163};
164
165enum {
166 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
167 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
168 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
169 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
170};
171
172enum {
173 HBA_RESP_DATAPRES_NO_DATA = 0x0,
174 HBA_RESP_DATAPRES_RESPONSE_DATA,
175 HBA_RESP_DATAPRES_SENSE_DATA
176};
177
178enum {
179 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
180 HBA_RESP_SVCRES_FAILURE,
181 HBA_RESP_SVCRES_TMF_COMPLETE,
182 HBA_RESP_SVCRES_TMF_SUCCEEDED,
183 HBA_RESP_SVCRES_TMF_REJECTED,
184 HBA_RESP_SVCRES_TMF_LUN_INVALID
185};
186
187enum {
188 HBA_RESP_STAT_IO_ERROR = 0x1,
189 HBA_RESP_STAT_IO_ABORTED,
190 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
191 HBA_RESP_STAT_INVALID_DEVICE,
192 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
193 HBA_RESP_STAT_UNDERRUN = 0x51,
194 HBA_RESP_STAT_OVERRUN = 0x75
195};
196
197struct aac_hba_cmd_req {
198 u8 iu_type;
199
200
201
202
203
204
205 u8 byte1;
206 u8 reply_qid;
207 u8 reserved1;
208 __le32 it_nexus;
209 __le32 request_id;
210
211 __le32 tweak_value_lo;
212 u8 cdb[16];
213 u8 lun[8];
214
215
216 __le32 data_length;
217
218
219 u8 attr_prio;
220
221
222 u8 emb_data_desc_count;
223
224 __le16 dek_index;
225
226
227 __le32 error_ptr_lo;
228
229
230 __le32 error_ptr_hi;
231
232
233 __le32 error_length;
234
235
236 __le32 tweak_value_hi;
237
238 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2];
239
240
241
242
243
244};
245
246
247#define HBA_TMF_ABORT_TASK 0x01
248#define HBA_TMF_LUN_RESET 0x08
249
250struct aac_hba_tm_req {
251 u8 iu_type;
252 u8 reply_qid;
253 u8 tmf;
254 u8 reserved1;
255
256 __le32 it_nexus;
257
258 u8 lun[8];
259
260
261 __le32 request_id;
262 __le32 reserved2;
263
264
265 __le32 managed_request_id;
266 __le32 reserved3;
267
268
269 __le32 error_ptr_lo;
270
271 __le32 error_ptr_hi;
272
273 __le32 error_length;
274};
275
276struct aac_hba_reset_req {
277 u8 iu_type;
278
279 u8 reset_type;
280 u8 reply_qid;
281 u8 reserved1;
282
283 __le32 it_nexus;
284 __le32 request_id;
285
286 __le32 error_ptr_lo;
287
288 __le32 error_ptr_hi;
289
290 __le32 error_length;
291};
292
293struct aac_hba_resp {
294 u8 iu_type;
295 u8 reserved1[3];
296 __le32 request_identifier;
297 __le32 reserved2;
298 u8 service_response;
299 u8 status;
300 u8 datapres;
301 u8 sense_response_data_len;
302 __le32 residual_count;
303
304 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
305};
306
307struct aac_native_hba {
308 union {
309 struct aac_hba_cmd_req cmd;
310 struct aac_hba_tm_req tmr;
311 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
312 } cmd;
313 union {
314 struct aac_hba_resp err;
315 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
316 } resp;
317};
318
319#define CISS_REPORT_PHYSICAL_LUNS 0xc3
320#define WRITE_HOST_WELLNESS 0xa5
321#define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
322#define BMIC_IN 0x26
323#define BMIC_OUT 0x27
324
325struct aac_ciss_phys_luns_resp {
326 u8 list_length[4];
327 u8 resp_flag;
328 u8 reserved[3];
329 struct _ciss_lun {
330 u8 tid[3];
331 u8 bus;
332 u8 level3[2];
333 u8 level2[2];
334 u8 node_ident[16];
335 } lun[1];
336};
337
338
339
340
341#define AAC_MAX_HRRQ 64
342
343struct aac_ciss_identify_pd {
344 u8 scsi_bus;
345 u8 scsi_id;
346 u16 block_size;
347 u32 total_blocks;
348 u32 reserved_blocks;
349 u8 model[40];
350 u8 serial_number[40];
351 u8 firmware_revision[8];
352 u8 scsi_inquiry_bits;
353 u8 compaq_drive_stamp;
354 u8 last_failure_reason;
355
356 u8 flags;
357 u8 more_flags;
358 u8 scsi_lun;
359 u8 yet_more_flags;
360 u8 even_more_flags;
361 u32 spi_speed_rules;
362 u8 phys_connector[2];
363 u8 phys_box_on_bus;
364 u8 phys_bay_in_box;
365 u32 rpm;
366 u8 device_type;
367 u8 sata_version;
368 u64 big_total_block_count;
369 u64 ris_starting_lba;
370 u32 ris_size;
371 u8 wwid[20];
372 u8 controller_phy_map[32];
373 u16 phy_count;
374 u8 phy_connected_dev_type[256];
375 u8 phy_to_drive_bay_num[256];
376 u16 phy_to_attached_dev_index[256];
377 u8 box_index;
378 u8 spitfire_support;
379 u16 extra_physical_drive_flags;
380 u8 negotiated_link_rate[256];
381 u8 phy_to_phy_map[256];
382 u8 redundant_path_present_map;
383 u8 redundant_path_failure_map;
384 u8 active_path_number;
385 u16 alternate_paths_phys_connector[8];
386 u8 alternate_paths_phys_box_on_port[8];
387 u8 multi_lun_device_lun_count;
388 u8 minimum_good_fw_revision[8];
389 u8 unique_inquiry_bytes[20];
390 u8 current_temperature_degreesC;
391 u8 temperature_threshold_degreesC;
392 u8 max_temperature_degreesC;
393 u8 logical_blocks_per_phys_block_exp;
394 u16 current_queue_depth_limit;
395 u8 switch_name[10];
396 u16 switch_port;
397 u8 alternate_paths_switch_name[40];
398 u8 alternate_paths_switch_port[8];
399 u16 power_on_hours;
400 u16 percent_endurance_used;
401 u8 drive_authentication;
402 u8 smart_carrier_authentication;
403 u8 smart_carrier_app_fw_version;
404 u8 smart_carrier_bootloader_fw_version;
405 u8 SanitizeSecureEraseSupport;
406 u8 DriveKeyFlags;
407 u8 encryption_key_name[64];
408 u32 misc_drive_flags;
409 u16 dek_index;
410 u16 drive_encryption_flags;
411 u8 sanitize_maximum_time[6];
412 u8 connector_info_mode;
413 u8 connector_info_number[4];
414 u8 long_connector_name[64];
415 u8 device_unique_identifier[16];
416 u8 padto_2K[17];
417} __packed;
418
419
420
421
422#define CONTAINER_CHANNEL (0)
423#define NATIVE_CHANNEL (1)
424#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
425#define CONTAINER_TO_ID(cont) (cont)
426#define CONTAINER_TO_LUN(cont) (0)
427#define ENCLOSURE_CHANNEL (3)
428
429#define PMC_DEVICE_S6 0x28b
430#define PMC_DEVICE_S7 0x28c
431#define PMC_DEVICE_S8 0x28d
432
433#define aac_phys_to_logical(x) ((x)+1)
434#define aac_logical_to_phys(x) ((x)?(x)-1:0)
435
436
437
438
439
440#define AAC_CHARDEV_UNREGISTERED (-1)
441#define AAC_CHARDEV_NEEDS_REINIT (-2)
442
443
444
445struct diskparm
446{
447 int heads;
448 int sectors;
449 int cylinders;
450};
451
452
453
454
455
456
457#define CT_NONE 0
458#define CT_OK 218
459#define FT_FILESYS 8
460#define FT_DRIVE 9
461
462
463
464
465
466
467
468struct sgentry {
469 __le32 addr;
470 __le32 count;
471};
472
473struct user_sgentry {
474 u32 addr;
475 u32 count;
476};
477
478struct sgentry64 {
479 __le32 addr[2];
480 __le32 count;
481};
482
483struct user_sgentry64 {
484 u32 addr[2];
485 u32 count;
486};
487
488struct sgentryraw {
489 __le32 next;
490 __le32 prev;
491 __le32 addr[2];
492 __le32 count;
493 __le32 flags;
494};
495
496struct user_sgentryraw {
497 u32 next;
498 u32 prev;
499 u32 addr[2];
500 u32 count;
501 u32 flags;
502};
503
504struct sge_ieee1212 {
505 u32 addrLow;
506 u32 addrHigh;
507 u32 length;
508 u32 flags;
509};
510
511
512
513
514
515
516
517
518struct sgmap {
519 __le32 count;
520 struct sgentry sg[1];
521};
522
523struct user_sgmap {
524 u32 count;
525 struct user_sgentry sg[1];
526};
527
528struct sgmap64 {
529 __le32 count;
530 struct sgentry64 sg[1];
531};
532
533struct user_sgmap64 {
534 u32 count;
535 struct user_sgentry64 sg[1];
536};
537
538struct sgmapraw {
539 __le32 count;
540 struct sgentryraw sg[1];
541};
542
543struct user_sgmapraw {
544 u32 count;
545 struct user_sgentryraw sg[1];
546};
547
548struct creation_info
549{
550 u8 buildnum;
551 u8 usec;
552 u8 via;
553
554
555 u8 year;
556 __le32 date;
557
558
559
560
561
562
563 __le32 serial[2];
564};
565
566
567
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569
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576
577
578
579#define NUMBER_OF_COMM_QUEUES 8
580#define HOST_HIGH_CMD_ENTRIES 4
581#define HOST_NORM_CMD_ENTRIES 8
582#define ADAP_HIGH_CMD_ENTRIES 4
583#define ADAP_NORM_CMD_ENTRIES 512
584#define HOST_HIGH_RESP_ENTRIES 4
585#define HOST_NORM_RESP_ENTRIES 512
586#define ADAP_HIGH_RESP_ENTRIES 4
587#define ADAP_NORM_RESP_ENTRIES 8
588
589#define TOTAL_QUEUE_ENTRIES \
590 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
591 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
592
593
594
595
596
597
598#define QUEUE_ALIGNMENT 16
599
600
601
602
603
604
605
606
607struct aac_entry {
608 __le32 size;
609 __le32 addr;
610};
611
612
613
614
615
616
617struct aac_qhdr {
618 __le64 header_addr;
619
620 __le32 *producer;
621 __le32 *consumer;
622};
623
624
625
626
627
628
629#define HostNormCmdQue 1
630#define HostHighCmdQue 2
631#define HostNormRespQue 3
632#define HostHighRespQue 4
633#define AdapNormRespNotFull 5
634#define AdapHighRespNotFull 6
635#define AdapNormCmdNotFull 7
636#define AdapHighCmdNotFull 8
637#define SynchCommandComplete 9
638#define AdapInternalError 0xfe
639
640
641
642
643
644
645
646#define AdapNormCmdQue 2
647#define AdapHighCmdQue 3
648#define AdapNormRespQue 6
649#define AdapHighRespQue 7
650#define HostShutdown 8
651#define HostPowerFail 9
652#define FatalCommError 10
653#define HostNormRespNotFull 11
654#define HostHighRespNotFull 12
655#define HostNormCmdNotFull 13
656#define HostHighCmdNotFull 14
657#define FastIo 15
658#define AdapPrintfDone 16
659
660
661
662
663
664
665enum aac_queue_types {
666 HostNormCmdQueue = 0,
667 HostHighCmdQueue,
668 AdapNormCmdQueue,
669 AdapHighCmdQueue,
670 HostNormRespQueue,
671 HostHighRespQueue,
672 AdapNormRespQueue,
673 AdapHighRespQueue
674};
675
676
677
678
679
680#define FIB_MAGIC 0x0001
681#define FIB_MAGIC2 0x0004
682#define FIB_MAGIC2_64 0x0005
683
684
685
686
687
688#define FsaNormal 1
689
690
691struct aac_fib_xporthdr {
692 __le64 HostAddress;
693 __le32 Size;
694 __le32 Handle;
695 __le64 Reserved[2];
696};
697
698#define ALIGN32 32
699
700
701
702
703
704
705struct aac_fibhdr {
706 __le32 XferState;
707 __le16 Command;
708 u8 StructType;
709 u8 Unused;
710 __le16 Size;
711 __le16 SenderSize;
712
713 __le32 SenderFibAddress;
714 union {
715 __le32 ReceiverFibAddress;
716
717 __le32 SenderFibAddressHigh;
718 __le32 TimeStamp;
719 } u;
720 __le32 Handle;
721 u32 Previous;
722 u32 Next;
723};
724
725struct hw_fib {
726 struct aac_fibhdr header;
727 u8 data[512-sizeof(struct aac_fibhdr)];
728};
729
730
731
732
733
734#define TestCommandResponse 1
735#define TestAdapterCommand 2
736
737
738
739#define LastTestCommand 100
740#define ReinitHostNormCommandQueue 101
741#define ReinitHostHighCommandQueue 102
742#define ReinitHostHighRespQueue 103
743#define ReinitHostNormRespQueue 104
744#define ReinitAdapNormCommandQueue 105
745#define ReinitAdapHighCommandQueue 107
746#define ReinitAdapHighRespQueue 108
747#define ReinitAdapNormRespQueue 109
748#define InterfaceShutdown 110
749#define DmaCommandFib 120
750#define StartProfile 121
751#define TermProfile 122
752#define SpeedTest 123
753#define TakeABreakPt 124
754#define RequestPerfData 125
755#define SetInterruptDefTimer 126
756#define SetInterruptDefCount 127
757#define GetInterruptDefStatus 128
758#define LastCommCommand 129
759
760
761
762#define NuFileSystem 300
763#define UFS 301
764#define HostFileSystem 302
765#define LastFileSystemCommand 303
766
767
768
769#define ContainerCommand 500
770#define ContainerCommand64 501
771#define ContainerRawIo 502
772#define ContainerRawIo2 503
773
774
775
776#define ScsiPortCommand 600
777#define ScsiPortCommand64 601
778
779
780
781#define AifRequest 700
782#define CheckRevision 701
783#define FsaHostShutdown 702
784#define RequestAdapterInfo 703
785#define IsAdapterPaused 704
786#define SendHostTime 705
787#define RequestSupplementAdapterInfo 706
788#define LastMiscCommand 707
789
790
791
792
793
794enum fib_xfer_state {
795 HostOwned = (1<<0),
796 AdapterOwned = (1<<1),
797 FibInitialized = (1<<2),
798 FibEmpty = (1<<3),
799 AllocatedFromPool = (1<<4),
800 SentFromHost = (1<<5),
801 SentFromAdapter = (1<<6),
802 ResponseExpected = (1<<7),
803 NoResponseExpected = (1<<8),
804 AdapterProcessed = (1<<9),
805 HostProcessed = (1<<10),
806 HighPriority = (1<<11),
807 NormalPriority = (1<<12),
808 Async = (1<<13),
809 AsyncIo = (1<<13),
810 PageFileIo = (1<<14),
811 ShutdownRequest = (1<<15),
812 LazyWrite = (1<<16),
813 AdapterMicroFib = (1<<17),
814 BIOSFibPath = (1<<18),
815 FastResponseCapable = (1<<19),
816 ApiFib = (1<<20),
817
818 NoMoreAifDataAvailable = (1<<21)
819};
820
821
822
823
824
825
826#define ADAPTER_INIT_STRUCT_REVISION 3
827#define ADAPTER_INIT_STRUCT_REVISION_4 4
828#define ADAPTER_INIT_STRUCT_REVISION_6 6
829#define ADAPTER_INIT_STRUCT_REVISION_7 7
830#define ADAPTER_INIT_STRUCT_REVISION_8 8
831
832union aac_init
833{
834 struct _r7 {
835 __le32 init_struct_revision;
836 __le32 no_of_msix_vectors;
837 __le32 fsrev;
838 __le32 comm_header_address;
839 __le32 fast_io_comm_area_address;
840 __le32 adapter_fibs_physical_address;
841 __le32 adapter_fibs_virtual_address;
842 __le32 adapter_fibs_size;
843 __le32 adapter_fib_align;
844 __le32 printfbuf;
845 __le32 printfbufsiz;
846
847 __le32 host_phys_mem_pages;
848
849 __le32 host_elapsed_seconds;
850
851 __le32 init_flags;
852#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
853#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
854#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
855#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
856#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
857#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
858#define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
859 __le32 max_io_commands;
860 __le32 max_io_size;
861 __le32 max_fib_size;
862
863 __le32 max_num_aif;
864
865
866 __le32 host_rrq_addr_low;
867 __le32 host_rrq_addr_high;
868 } r7;
869 struct _r8 {
870
871 __le32 init_struct_revision;
872 __le32 rr_queue_count;
873 __le32 host_elapsed_seconds;
874 __le32 init_flags;
875 __le32 max_io_size;
876 __le32 max_num_aif;
877 __le32 reserved1;
878 __le32 reserved2;
879 struct _rrq {
880 __le32 host_addr_low;
881 __le32 host_addr_high;
882 __le16 msix_id;
883 __le16 element_count;
884 __le16 comp_thresh;
885 __le16 unused;
886 } rrq[1];
887 } r8;
888};
889
890enum aac_log_level {
891 LOG_AAC_INIT = 10,
892 LOG_AAC_INFORMATIONAL = 20,
893 LOG_AAC_WARNING = 30,
894 LOG_AAC_LOW_ERROR = 40,
895 LOG_AAC_MEDIUM_ERROR = 50,
896 LOG_AAC_HIGH_ERROR = 60,
897 LOG_AAC_PANIC = 70,
898 LOG_AAC_DEBUG = 80,
899 LOG_AAC_WINDBG_PRINT = 90
900};
901
902#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
903#define FSAFS_NTC_FIB_CONTEXT 0x030c
904
905struct aac_dev;
906struct fib;
907struct scsi_cmnd;
908
909struct adapter_ops
910{
911
912 void (*adapter_interrupt)(struct aac_dev *dev);
913 void (*adapter_notify)(struct aac_dev *dev, u32 event);
914 void (*adapter_disable_int)(struct aac_dev *dev);
915 void (*adapter_enable_int)(struct aac_dev *dev);
916 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
917 int (*adapter_check_health)(struct aac_dev *dev);
918 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
919 void (*adapter_start)(struct aac_dev *dev);
920
921 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
922 irq_handler_t adapter_intr;
923
924 int (*adapter_deliver)(struct fib * fib);
925 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
926 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
927 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
928 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
929
930 int (*adapter_comm)(struct aac_dev * dev, int comm);
931};
932
933
934
935
936
937struct aac_driver_ident
938{
939 int (*init)(struct aac_dev *dev);
940 char * name;
941 char * vname;
942 char * model;
943 u16 channels;
944 int quirks;
945};
946
947
948
949
950
951
952#define AAC_QUIRK_31BIT 0x0001
953
954
955
956
957
958
959#define AAC_QUIRK_34SG 0x0002
960
961
962
963
964#define AAC_QUIRK_SLAVE 0x0004
965
966
967
968
969#define AAC_QUIRK_MASTER 0x0008
970
971
972
973
974
975
976#define AAC_QUIRK_17SG 0x0010
977
978
979
980
981
982#define AAC_QUIRK_SCSI_32 0x0020
983
984
985
986
987#define AAC_QUIRK_SRC 0x0040
988
989
990
991
992
993
994
995
996
997
998
999struct aac_queue {
1000 u64 logical;
1001 struct aac_entry *base;
1002 struct aac_qhdr headers;
1003 u32 entries;
1004 wait_queue_head_t qfull;
1005 wait_queue_head_t cmdready;
1006
1007 spinlock_t *lock;
1008 spinlock_t lockdata;
1009 struct list_head cmdq;
1010
1011
1012 atomic_t numpending;
1013 struct aac_dev * dev;
1014};
1015
1016
1017
1018
1019
1020
1021struct aac_queue_block
1022{
1023 struct aac_queue queue[8];
1024};
1025
1026
1027
1028
1029
1030struct sa_drawbridge_CSR {
1031
1032 __le32 reserved[10];
1033 u8 LUT_Offset;
1034 u8 reserved1[3];
1035 __le32 LUT_Data;
1036 __le32 reserved2[26];
1037 __le16 PRICLEARIRQ;
1038 __le16 SECCLEARIRQ;
1039 __le16 PRISETIRQ;
1040 __le16 SECSETIRQ;
1041 __le16 PRICLEARIRQMASK;
1042 __le16 SECCLEARIRQMASK;
1043 __le16 PRISETIRQMASK;
1044 __le16 SECSETIRQMASK;
1045 __le32 MAILBOX0;
1046 __le32 MAILBOX1;
1047 __le32 MAILBOX2;
1048 __le32 MAILBOX3;
1049 __le32 MAILBOX4;
1050 __le32 MAILBOX5;
1051 __le32 MAILBOX6;
1052 __le32 MAILBOX7;
1053 __le32 ROM_Setup_Data;
1054 __le32 ROM_Control_Addr;
1055 __le32 reserved3[12];
1056 __le32 LUT[64];
1057};
1058
1059#define Mailbox0 SaDbCSR.MAILBOX0
1060#define Mailbox1 SaDbCSR.MAILBOX1
1061#define Mailbox2 SaDbCSR.MAILBOX2
1062#define Mailbox3 SaDbCSR.MAILBOX3
1063#define Mailbox4 SaDbCSR.MAILBOX4
1064#define Mailbox5 SaDbCSR.MAILBOX5
1065#define Mailbox6 SaDbCSR.MAILBOX6
1066#define Mailbox7 SaDbCSR.MAILBOX7
1067
1068#define DoorbellReg_p SaDbCSR.PRISETIRQ
1069#define DoorbellReg_s SaDbCSR.SECSETIRQ
1070#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1071
1072
1073#define DOORBELL_0 0x0001
1074#define DOORBELL_1 0x0002
1075#define DOORBELL_2 0x0004
1076#define DOORBELL_3 0x0008
1077#define DOORBELL_4 0x0010
1078#define DOORBELL_5 0x0020
1079#define DOORBELL_6 0x0040
1080
1081
1082#define PrintfReady DOORBELL_5
1083#define PrintfDone DOORBELL_5
1084
1085struct sa_registers {
1086 struct sa_drawbridge_CSR SaDbCSR;
1087};
1088
1089
1090#define SA_INIT_NUM_MSIXVECTORS 1
1091#define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1092
1093#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1094#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1095#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1096#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1097
1098
1099
1100
1101
1102struct rx_mu_registers {
1103
1104 __le32 ARSR;
1105 __le32 reserved0;
1106 __le32 AWR;
1107 __le32 reserved1;
1108 __le32 IMRx[2];
1109 __le32 OMRx[2];
1110 __le32 IDR;
1111 __le32 IISR;
1112
1113 __le32 IIMR;
1114
1115 __le32 ODR;
1116 __le32 OISR;
1117
1118 __le32 OIMR;
1119
1120 __le32 reserved2;
1121 __le32 reserved3;
1122 __le32 InboundQueue;
1123 __le32 OutboundQueue;
1124
1125
1126};
1127
1128struct rx_inbound {
1129 __le32 Mailbox[8];
1130};
1131
1132#define INBOUNDDOORBELL_0 0x00000001
1133#define INBOUNDDOORBELL_1 0x00000002
1134#define INBOUNDDOORBELL_2 0x00000004
1135#define INBOUNDDOORBELL_3 0x00000008
1136#define INBOUNDDOORBELL_4 0x00000010
1137#define INBOUNDDOORBELL_5 0x00000020
1138#define INBOUNDDOORBELL_6 0x00000040
1139
1140#define OUTBOUNDDOORBELL_0 0x00000001
1141#define OUTBOUNDDOORBELL_1 0x00000002
1142#define OUTBOUNDDOORBELL_2 0x00000004
1143#define OUTBOUNDDOORBELL_3 0x00000008
1144#define OUTBOUNDDOORBELL_4 0x00000010
1145
1146#define InboundDoorbellReg MUnit.IDR
1147#define OutboundDoorbellReg MUnit.ODR
1148
1149struct rx_registers {
1150 struct rx_mu_registers MUnit;
1151 __le32 reserved1[2];
1152 struct rx_inbound IndexRegs;
1153};
1154
1155#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1156#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1157#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1158#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1159
1160
1161
1162
1163
1164#define rkt_mu_registers rx_mu_registers
1165#define rkt_inbound rx_inbound
1166
1167struct rkt_registers {
1168 struct rkt_mu_registers MUnit;
1169 __le32 reserved1[1006];
1170 struct rkt_inbound IndexRegs;
1171};
1172
1173#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1174#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1175#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1176#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1177
1178
1179
1180
1181
1182#define src_inbound rx_inbound
1183
1184struct src_mu_registers {
1185
1186 __le32 reserved0[6];
1187 __le32 IOAR[2];
1188 __le32 IDR;
1189 __le32 IISR;
1190 __le32 reserved1[3];
1191 __le32 OIMR;
1192 __le32 reserved2[25];
1193 __le32 ODR_R;
1194 __le32 ODR_C;
1195 __le32 reserved3[3];
1196 __le32 SCR0;
1197 __le32 reserved4[2];
1198 __le32 OMR;
1199 __le32 IQ_L;
1200 __le32 IQ_H;
1201 __le32 ODR_MSI;
1202 __le32 reserved5;
1203 __le32 IQN_L;
1204 __le32 IQN_H;
1205};
1206
1207struct src_registers {
1208 struct src_mu_registers MUnit;
1209 union {
1210 struct {
1211 __le32 reserved1[130786];
1212 struct src_inbound IndexRegs;
1213 } tupelo;
1214 struct {
1215 __le32 reserved1[970];
1216 struct src_inbound IndexRegs;
1217 } denali;
1218 } u;
1219};
1220
1221#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1222#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1223#define src_writeb(AEP, CSR, value) writeb(value, \
1224 &((AEP)->regs.src.bar0->CSR))
1225#define src_writel(AEP, CSR, value) writel(value, \
1226 &((AEP)->regs.src.bar0->CSR))
1227#if defined(writeq)
1228#define src_writeq(AEP, CSR, value) writeq(value, \
1229 &((AEP)->regs.src.bar0->CSR))
1230#endif
1231
1232#define SRC_ODR_SHIFT 12
1233#define SRC_IDR_SHIFT 9
1234#define SRC_MSI_READ_MASK 0x1000
1235
1236typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1237
1238struct aac_fib_context {
1239 s16 type;
1240 s16 size;
1241 u32 unique;
1242 ulong jiffies;
1243 struct list_head next;
1244 struct semaphore wait_sem;
1245 int wait;
1246 unsigned long count;
1247 struct list_head fib_list;
1248};
1249
1250struct sense_data {
1251 u8 error_code;
1252 u8 valid:1;
1253
1254
1255
1256 u8 segment_number;
1257 u8 sense_key:4;
1258 u8 reserved:1;
1259 u8 ILI:1;
1260 u8 EOM:1;
1261 u8 filemark:1;
1262
1263 u8 information[4];
1264
1265
1266
1267 u8 add_sense_len;
1268 u8 cmnd_info[4];
1269 u8 ASC;
1270 u8 ASCQ;
1271 u8 FRUC;
1272 u8 bit_ptr:3;
1273
1274
1275 u8 BPV:1;
1276
1277
1278 u8 reserved2:2;
1279 u8 CD:1;
1280
1281
1282 u8 SKSV:1;
1283 u8 field_ptr[2];
1284};
1285
1286struct fsa_dev_info {
1287 u64 last;
1288 u64 size;
1289 u32 type;
1290 u32 config_waiting_on;
1291 unsigned long config_waiting_stamp;
1292 u16 queue_depth;
1293 u8 config_needed;
1294 u8 valid;
1295 u8 ro;
1296 u8 locked;
1297 u8 deleted;
1298 char devname[8];
1299 struct sense_data sense_data;
1300 u32 block_size;
1301 u8 identifier[16];
1302};
1303
1304struct fib {
1305 void *next;
1306 s16 type;
1307 s16 size;
1308
1309
1310
1311 struct aac_dev *dev;
1312
1313
1314
1315
1316 struct semaphore event_wait;
1317 spinlock_t event_lock;
1318
1319 u32 done;
1320 fib_callback callback;
1321 void *callback_data;
1322 u32 flags;
1323
1324
1325
1326
1327 struct list_head fiblink;
1328 void *data;
1329 u32 vector_no;
1330 struct hw_fib *hw_fib_va;
1331 dma_addr_t hw_fib_pa;
1332 dma_addr_t hw_sgl_pa;
1333 dma_addr_t hw_error_pa;
1334 u32 hbacmd_size;
1335};
1336
1337#define AAC_INIT 0
1338#define AAC_RESCAN 1
1339
1340#define AAC_DEVTYPE_RAID_MEMBER 1
1341#define AAC_DEVTYPE_ARC_RAW 2
1342#define AAC_DEVTYPE_NATIVE_RAW 3
1343
1344#define AAC_SAFW_RESCAN_DELAY (10 * HZ)
1345
1346struct aac_hba_map_info {
1347 __le32 rmw_nexus;
1348 u8 devtype;
1349 u8 reset_state;
1350
1351 u16 qd_limit;
1352 u32 scan_counter;
1353 struct aac_ciss_identify_pd *safw_identify_resp;
1354};
1355
1356
1357
1358
1359
1360
1361
1362struct aac_adapter_info
1363{
1364 __le32 platform;
1365 __le32 cpu;
1366 __le32 subcpu;
1367 __le32 clock;
1368 __le32 execmem;
1369 __le32 buffermem;
1370 __le32 totalmem;
1371 __le32 kernelrev;
1372 __le32 kernelbuild;
1373 __le32 monitorrev;
1374 __le32 monitorbuild;
1375 __le32 hwrev;
1376 __le32 hwbuild;
1377 __le32 biosrev;
1378 __le32 biosbuild;
1379 __le32 cluster;
1380 __le32 clusterchannelmask;
1381 __le32 serial[2];
1382 __le32 battery;
1383 __le32 options;
1384 __le32 OEM;
1385};
1386
1387struct aac_supplement_adapter_info
1388{
1389 u8 adapter_type_text[17+1];
1390 u8 pad[2];
1391 __le32 flash_memory_byte_size;
1392 __le32 flash_image_id;
1393 __le32 max_number_ports;
1394 __le32 version;
1395 __le32 feature_bits;
1396 u8 slot_number;
1397 u8 reserved_pad0[3];
1398 u8 build_date[12];
1399 __le32 current_number_ports;
1400 struct {
1401 u8 assembly_pn[8];
1402 u8 fru_pn[8];
1403 u8 battery_fru_pn[8];
1404 u8 ec_version_string[8];
1405 u8 tsid[12];
1406 } vpd_info;
1407 __le32 flash_firmware_revision;
1408 __le32 flash_firmware_build;
1409 __le32 raid_type_morph_options;
1410 __le32 flash_firmware_boot_revision;
1411 __le32 flash_firmware_boot_build;
1412 u8 mfg_pcba_serial_no[12];
1413 u8 mfg_wwn_name[8];
1414 __le32 supported_options2;
1415 __le32 struct_expansion;
1416
1417 __le32 feature_bits3;
1418 __le32 supported_performance_modes;
1419 u8 host_bus_type;
1420 u8 host_bus_width;
1421 u16 host_bus_speed;
1422 u8 max_rrc_drives;
1423 u8 max_disk_xtasks;
1424
1425 u8 cpld_ver_loaded;
1426 u8 cpld_ver_in_flash;
1427
1428 __le64 max_rrc_capacity;
1429 __le32 compiled_max_hist_log_level;
1430 u8 custom_board_name[12];
1431 u16 supported_cntlr_mode;
1432 u16 reserved_for_future16;
1433 __le32 supported_options3;
1434
1435 __le16 virt_device_bus;
1436 __le16 virt_device_target;
1437 __le16 virt_device_lun;
1438 __le16 unused;
1439 __le32 reserved_for_future_growth[68];
1440
1441};
1442#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1443#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1444
1445#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1446#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1447#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1448#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1449
1450#define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1451
1452#define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1453
1454
1455
1456#define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1457#define AAC_SIS_VERSION_V3 3
1458#define AAC_SIS_SLOT_UNKNOWN 0xFF
1459
1460#define GetBusInfo 0x00000009
1461struct aac_bus_info {
1462 __le32 Command;
1463 __le32 ObjType;
1464 __le32 MethodId;
1465 __le32 ObjectId;
1466 __le32 CtlCmd;
1467};
1468
1469struct aac_bus_info_response {
1470 __le32 Status;
1471 __le32 ObjType;
1472 __le32 MethodId;
1473 __le32 ObjectId;
1474 __le32 CtlCmd;
1475 __le32 ProbeComplete;
1476 __le32 BusCount;
1477 __le32 TargetsPerBus;
1478 u8 InitiatorBusId[10];
1479 u8 BusValid[10];
1480};
1481
1482
1483
1484
1485#define AAC_BAT_REQ_PRESENT (1)
1486#define AAC_BAT_REQ_NOTPRESENT (2)
1487#define AAC_BAT_OPT_PRESENT (3)
1488#define AAC_BAT_OPT_NOTPRESENT (4)
1489#define AAC_BAT_NOT_SUPPORTED (5)
1490
1491
1492
1493#define AAC_CPU_SIMULATOR (1)
1494#define AAC_CPU_I960 (2)
1495#define AAC_CPU_STRONGARM (3)
1496
1497
1498
1499
1500#define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1501#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1502#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1503#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1504#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1505#define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1506#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1507#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1508#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1509#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1510#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1511#define AAC_OPT_ALARM cpu_to_le32(1<<11)
1512#define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1513#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1514#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1515#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1516#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1517#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1518#define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1519#define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1520#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1521#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1522#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1523#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1524
1525#define AAC_COMM_PRODUCER 0
1526#define AAC_COMM_MESSAGE 1
1527#define AAC_COMM_MESSAGE_TYPE1 3
1528#define AAC_COMM_MESSAGE_TYPE2 4
1529#define AAC_COMM_MESSAGE_TYPE3 5
1530
1531#define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1532#define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
1533
1534
1535struct aac_msix_ctx {
1536 int vector_no;
1537 struct aac_dev *dev;
1538};
1539
1540struct aac_dev
1541{
1542 struct list_head entry;
1543 const char *name;
1544 int id;
1545
1546
1547
1548
1549 unsigned int max_fib_size;
1550 unsigned int sg_tablesize;
1551 unsigned int max_num_aif;
1552
1553 unsigned int max_cmd_size;
1554
1555
1556
1557
1558 dma_addr_t hw_fib_pa;
1559 struct hw_fib *hw_fib_va;
1560 struct hw_fib *aif_base_va;
1561
1562
1563
1564 struct fib *fibs;
1565
1566 struct fib *free_fib;
1567 spinlock_t fib_lock;
1568
1569 struct mutex ioctl_mutex;
1570 struct mutex scan_mutex;
1571 struct aac_queue_block *queues;
1572
1573
1574
1575
1576
1577
1578
1579 struct list_head fib_list;
1580
1581 struct adapter_ops a_ops;
1582 unsigned long fsrev;
1583
1584 resource_size_t base_start;
1585 resource_size_t dbg_base;
1586
1587
1588 resource_size_t base_size, dbg_size;
1589
1590
1591
1592
1593
1594 union aac_init *init;
1595 dma_addr_t init_pa;
1596
1597 __le32 *host_rrq;
1598 dma_addr_t host_rrq_pa;
1599
1600 u32 host_rrq_idx[AAC_MAX_MSIX];
1601 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1602 u32 fibs_pushed_no;
1603 struct pci_dev *pdev;
1604
1605 void *printfbuf;
1606 void *comm_addr;
1607 dma_addr_t comm_phys;
1608 size_t comm_size;
1609
1610 struct Scsi_Host *scsi_host_ptr;
1611 int maximum_num_containers;
1612 int maximum_num_physicals;
1613 int maximum_num_channels;
1614 struct fsa_dev_info *fsa_dev;
1615 struct task_struct *thread;
1616 struct delayed_work safw_rescan_work;
1617 int cardtype;
1618
1619
1620
1621
1622 spinlock_t iq_lock;
1623
1624
1625
1626
1627#ifndef AAC_MIN_FOOTPRINT_SIZE
1628# define AAC_MIN_FOOTPRINT_SIZE 8192
1629# define AAC_MIN_SRC_BAR0_SIZE 0x400000
1630# define AAC_MIN_SRC_BAR1_SIZE 0x800
1631# define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1632# define AAC_MIN_SRCV_BAR1_SIZE 0x400
1633#endif
1634 union
1635 {
1636 struct sa_registers __iomem *sa;
1637 struct rx_registers __iomem *rx;
1638 struct rkt_registers __iomem *rkt;
1639 struct {
1640 struct src_registers __iomem *bar0;
1641 char __iomem *bar1;
1642 } src;
1643 } regs;
1644 volatile void __iomem *base, *dbg_base_mapped;
1645 volatile struct rx_inbound __iomem *IndexRegs;
1646 u32 OIMR;
1647
1648
1649
1650 u32 aif_thread;
1651 struct aac_adapter_info adapter_info;
1652 struct aac_supplement_adapter_info supplement_adapter_info;
1653
1654
1655
1656 u8 nondasd_support;
1657 u8 jbod;
1658 u8 cache_protected;
1659 u8 dac_support;
1660 u8 needs_dac;
1661 u8 raid_scsi_mode;
1662 u8 comm_interface;
1663 u8 raw_io_interface;
1664 u8 raw_io_64;
1665 u8 printf_enabled;
1666 u8 in_reset;
1667 u8 in_soft_reset;
1668 u8 msi;
1669 u8 sa_firmware;
1670 int management_fib_count;
1671 spinlock_t manage_lock;
1672 spinlock_t sync_lock;
1673 int sync_mode;
1674 struct fib *sync_fib;
1675 struct list_head sync_fib_list;
1676 u32 doorbell_mask;
1677 u32 max_msix;
1678 u32 vector_cap;
1679 int msi_enabled;
1680 atomic_t msix_counter;
1681 u32 scan_counter;
1682 struct msix_entry msixentry[AAC_MAX_MSIX];
1683 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX];
1684 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1685 struct aac_ciss_phys_luns_resp *safw_phys_luns;
1686 u8 adapter_shutdown;
1687 u32 handle_pci_error;
1688 bool init_reset;
1689};
1690
1691#define aac_adapter_interrupt(dev) \
1692 (dev)->a_ops.adapter_interrupt(dev)
1693
1694#define aac_adapter_notify(dev, event) \
1695 (dev)->a_ops.adapter_notify(dev, event)
1696
1697#define aac_adapter_disable_int(dev) \
1698 (dev)->a_ops.adapter_disable_int(dev)
1699
1700#define aac_adapter_enable_int(dev) \
1701 (dev)->a_ops.adapter_enable_int(dev)
1702
1703#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1704 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1705
1706#define aac_adapter_restart(dev, bled, reset_type) \
1707 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1708
1709#define aac_adapter_start(dev) \
1710 ((dev)->a_ops.adapter_start(dev))
1711
1712#define aac_adapter_ioremap(dev, size) \
1713 (dev)->a_ops.adapter_ioremap(dev, size)
1714
1715#define aac_adapter_deliver(fib) \
1716 ((fib)->dev)->a_ops.adapter_deliver(fib)
1717
1718#define aac_adapter_bounds(dev,cmd,lba) \
1719 dev->a_ops.adapter_bounds(dev,cmd,lba)
1720
1721#define aac_adapter_read(fib,cmd,lba,count) \
1722 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1723
1724#define aac_adapter_write(fib,cmd,lba,count,fua) \
1725 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1726
1727#define aac_adapter_scsi(fib,cmd) \
1728 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1729
1730#define aac_adapter_comm(dev,comm) \
1731 (dev)->a_ops.adapter_comm(dev, comm)
1732
1733#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1734#define FIB_CONTEXT_FLAG (0x00000002)
1735#define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1736#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1737#define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1738#define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1739#define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040)
1740#define FIB_CONTEXT_FLAG_EH_RESET (0x00000080)
1741
1742
1743
1744
1745
1746#define Null 0
1747#define GetAttributes 1
1748#define SetAttributes 2
1749#define Lookup 3
1750#define ReadLink 4
1751#define Read 5
1752#define Write 6
1753#define Create 7
1754#define MakeDirectory 8
1755#define SymbolicLink 9
1756#define MakeNode 10
1757#define Removex 11
1758#define RemoveDirectoryx 12
1759#define Rename 13
1760#define Link 14
1761#define ReadDirectory 15
1762#define ReadDirectoryPlus 16
1763#define FileSystemStatus 17
1764#define FileSystemInfo 18
1765#define PathConfigure 19
1766#define Commit 20
1767#define Mount 21
1768#define UnMount 22
1769#define Newfs 23
1770#define FsCheck 24
1771#define FsSync 25
1772#define SimReadWrite 26
1773#define SetFileSystemStatus 27
1774#define BlockRead 28
1775#define BlockWrite 29
1776#define NvramIoctl 30
1777#define FsSyncWait 31
1778#define ClearArchiveBit 32
1779#define SetAcl 33
1780#define GetAcl 34
1781#define AssignAcl 35
1782#define FaultInsertion 36
1783#define CrazyCache 37
1784
1785#define MAX_FSACOMMAND_NUM 38
1786
1787
1788
1789
1790
1791
1792
1793#define ST_OK 0
1794#define ST_PERM 1
1795#define ST_NOENT 2
1796#define ST_IO 5
1797#define ST_NXIO 6
1798#define ST_E2BIG 7
1799#define ST_MEDERR 8
1800#define ST_ACCES 13
1801#define ST_EXIST 17
1802#define ST_XDEV 18
1803#define ST_NODEV 19
1804#define ST_NOTDIR 20
1805#define ST_ISDIR 21
1806#define ST_INVAL 22
1807#define ST_FBIG 27
1808#define ST_NOSPC 28
1809#define ST_ROFS 30
1810#define ST_MLINK 31
1811#define ST_WOULDBLOCK 35
1812#define ST_NAMETOOLONG 63
1813#define ST_NOTEMPTY 66
1814#define ST_DQUOT 69
1815#define ST_STALE 70
1816#define ST_REMOTE 71
1817#define ST_NOT_READY 72
1818#define ST_BADHANDLE 10001
1819#define ST_NOT_SYNC 10002
1820#define ST_BAD_COOKIE 10003
1821#define ST_NOTSUPP 10004
1822#define ST_TOOSMALL 10005
1823#define ST_SERVERFAULT 10006
1824#define ST_BADTYPE 10007
1825#define ST_JUKEBOX 10008
1826#define ST_NOTMOUNTED 10009
1827#define ST_MAINTMODE 10010
1828#define ST_STALEACL 10011
1829
1830
1831
1832
1833
1834#define CACHE_CSTABLE 1
1835#define CACHE_UNSTABLE 2
1836
1837
1838
1839
1840
1841
1842#define CMFILE_SYNCH_NVRAM 1
1843#define CMDATA_SYNCH_NVRAM 2
1844#define CMFILE_SYNCH 3
1845#define CMDATA_SYNCH 4
1846#define CMUNSTABLE 5
1847
1848#define RIO_TYPE_WRITE 0x0000
1849#define RIO_TYPE_READ 0x0001
1850#define RIO_SUREWRITE 0x0008
1851
1852#define RIO2_IO_TYPE 0x0003
1853#define RIO2_IO_TYPE_WRITE 0x0000
1854#define RIO2_IO_TYPE_READ 0x0001
1855#define RIO2_IO_TYPE_VERIFY 0x0002
1856#define RIO2_IO_ERROR 0x0004
1857#define RIO2_IO_SUREWRITE 0x0008
1858#define RIO2_SGL_CONFORMANT 0x0010
1859#define RIO2_SG_FORMAT 0xF000
1860#define RIO2_SG_FORMAT_ARC 0x0000
1861#define RIO2_SG_FORMAT_SRL 0x1000
1862#define RIO2_SG_FORMAT_IEEE1212 0x2000
1863
1864struct aac_read
1865{
1866 __le32 command;
1867 __le32 cid;
1868 __le32 block;
1869 __le32 count;
1870 struct sgmap sg;
1871};
1872
1873struct aac_read64
1874{
1875 __le32 command;
1876 __le16 cid;
1877 __le16 sector_count;
1878 __le32 block;
1879 __le16 pad;
1880 __le16 flags;
1881 struct sgmap64 sg;
1882};
1883
1884struct aac_read_reply
1885{
1886 __le32 status;
1887 __le32 count;
1888};
1889
1890struct aac_write
1891{
1892 __le32 command;
1893 __le32 cid;
1894 __le32 block;
1895 __le32 count;
1896 __le32 stable;
1897 struct sgmap sg;
1898};
1899
1900struct aac_write64
1901{
1902 __le32 command;
1903 __le16 cid;
1904 __le16 sector_count;
1905 __le32 block;
1906 __le16 pad;
1907 __le16 flags;
1908 struct sgmap64 sg;
1909};
1910struct aac_write_reply
1911{
1912 __le32 status;
1913 __le32 count;
1914 __le32 committed;
1915};
1916
1917struct aac_raw_io
1918{
1919 __le32 block[2];
1920 __le32 count;
1921 __le16 cid;
1922 __le16 flags;
1923 __le16 bpTotal;
1924 __le16 bpComplete;
1925 struct sgmapraw sg;
1926};
1927
1928struct aac_raw_io2 {
1929 __le32 blockLow;
1930 __le32 blockHigh;
1931 __le32 byteCount;
1932 __le16 cid;
1933 __le16 flags;
1934 __le32 sgeFirstSize;
1935 __le32 sgeNominalSize;
1936 u8 sgeCnt;
1937 u8 bpTotal;
1938 u8 bpComplete;
1939 u8 sgeFirstIndex;
1940 u8 unused[4];
1941 struct sge_ieee1212 sge[1];
1942};
1943
1944#define CT_FLUSH_CACHE 129
1945struct aac_synchronize {
1946 __le32 command;
1947 __le32 type;
1948 __le32 cid;
1949 __le32 parm1;
1950 __le32 parm2;
1951 __le32 parm3;
1952 __le32 parm4;
1953 __le32 count;
1954};
1955
1956struct aac_synchronize_reply {
1957 __le32 dummy0;
1958 __le32 dummy1;
1959 __le32 status;
1960 __le32 parm1;
1961 __le32 parm2;
1962 __le32 parm3;
1963 __le32 parm4;
1964 __le32 parm5;
1965 u8 data[16];
1966};
1967
1968#define CT_POWER_MANAGEMENT 245
1969#define CT_PM_START_UNIT 2
1970#define CT_PM_STOP_UNIT 3
1971#define CT_PM_UNIT_IMMEDIATE 1
1972struct aac_power_management {
1973 __le32 command;
1974 __le32 type;
1975 __le32 sub;
1976 __le32 cid;
1977 __le32 parm;
1978};
1979
1980#define CT_PAUSE_IO 65
1981#define CT_RELEASE_IO 66
1982struct aac_pause {
1983 __le32 command;
1984 __le32 type;
1985 __le32 timeout;
1986 __le32 min;
1987 __le32 noRescan;
1988 __le32 parm3;
1989 __le32 parm4;
1990 __le32 count;
1991};
1992
1993struct aac_srb
1994{
1995 __le32 function;
1996 __le32 channel;
1997 __le32 id;
1998 __le32 lun;
1999 __le32 timeout;
2000 __le32 flags;
2001 __le32 count;
2002 __le32 retry_limit;
2003 __le32 cdb_size;
2004 u8 cdb[16];
2005 struct sgmap sg;
2006};
2007
2008
2009
2010
2011
2012struct user_aac_srb
2013{
2014 u32 function;
2015 u32 channel;
2016 u32 id;
2017 u32 lun;
2018 u32 timeout;
2019 u32 flags;
2020 u32 count;
2021 u32 retry_limit;
2022 u32 cdb_size;
2023 u8 cdb[16];
2024 struct user_sgmap sg;
2025};
2026
2027#define AAC_SENSE_BUFFERSIZE 30
2028
2029struct aac_srb_reply
2030{
2031 __le32 status;
2032 __le32 srb_status;
2033 __le32 scsi_status;
2034 __le32 data_xfer_length;
2035 __le32 sense_data_size;
2036 u8 sense_data[AAC_SENSE_BUFFERSIZE];
2037};
2038
2039struct aac_srb_unit {
2040 struct aac_srb srb;
2041 struct aac_srb_reply srb_reply;
2042};
2043
2044
2045
2046
2047#define SRB_NoDataXfer 0x0000
2048#define SRB_DisableDisconnect 0x0004
2049#define SRB_DisableSynchTransfer 0x0008
2050#define SRB_BypassFrozenQueue 0x0010
2051#define SRB_DisableAutosense 0x0020
2052#define SRB_DataIn 0x0040
2053#define SRB_DataOut 0x0080
2054
2055
2056
2057
2058#define SRBF_ExecuteScsi 0x0000
2059#define SRBF_ClaimDevice 0x0001
2060#define SRBF_IO_Control 0x0002
2061#define SRBF_ReceiveEvent 0x0003
2062#define SRBF_ReleaseQueue 0x0004
2063#define SRBF_AttachDevice 0x0005
2064#define SRBF_ReleaseDevice 0x0006
2065#define SRBF_Shutdown 0x0007
2066#define SRBF_Flush 0x0008
2067#define SRBF_AbortCommand 0x0010
2068#define SRBF_ReleaseRecovery 0x0011
2069#define SRBF_ResetBus 0x0012
2070#define SRBF_ResetDevice 0x0013
2071#define SRBF_TerminateIO 0x0014
2072#define SRBF_FlushQueue 0x0015
2073#define SRBF_RemoveDevice 0x0016
2074#define SRBF_DomainValidation 0x0017
2075
2076
2077
2078
2079#define SRB_STATUS_PENDING 0x00
2080#define SRB_STATUS_SUCCESS 0x01
2081#define SRB_STATUS_ABORTED 0x02
2082#define SRB_STATUS_ABORT_FAILED 0x03
2083#define SRB_STATUS_ERROR 0x04
2084#define SRB_STATUS_BUSY 0x05
2085#define SRB_STATUS_INVALID_REQUEST 0x06
2086#define SRB_STATUS_INVALID_PATH_ID 0x07
2087#define SRB_STATUS_NO_DEVICE 0x08
2088#define SRB_STATUS_TIMEOUT 0x09
2089#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2090#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2091#define SRB_STATUS_MESSAGE_REJECTED 0x0D
2092#define SRB_STATUS_BUS_RESET 0x0E
2093#define SRB_STATUS_PARITY_ERROR 0x0F
2094#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2095#define SRB_STATUS_NO_HBA 0x11
2096#define SRB_STATUS_DATA_OVERRUN 0x12
2097#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2098#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2099#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2100#define SRB_STATUS_REQUEST_FLUSHED 0x16
2101#define SRB_STATUS_DELAYED_RETRY 0x17
2102#define SRB_STATUS_INVALID_LUN 0x20
2103#define SRB_STATUS_INVALID_TARGET_ID 0x21
2104#define SRB_STATUS_BAD_FUNCTION 0x22
2105#define SRB_STATUS_ERROR_RECOVERY 0x23
2106#define SRB_STATUS_NOT_STARTED 0x24
2107#define SRB_STATUS_NOT_IN_USE 0x30
2108#define SRB_STATUS_FORCE_ABORT 0x31
2109#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2110
2111
2112
2113
2114
2115#define VM_Null 0
2116#define VM_NameServe 1
2117#define VM_ContainerConfig 2
2118#define VM_Ioctl 3
2119#define VM_FilesystemIoctl 4
2120#define VM_CloseAll 5
2121#define VM_CtBlockRead 6
2122#define VM_CtBlockWrite 7
2123#define VM_SliceBlockRead 8
2124#define VM_SliceBlockWrite 9
2125#define VM_DriveBlockRead 10
2126#define VM_DriveBlockWrite 11
2127#define VM_EnclosureMgt 12
2128#define VM_Unused 13
2129#define VM_CtBlockVerify 14
2130#define VM_CtPerf 15
2131#define VM_CtBlockRead64 16
2132#define VM_CtBlockWrite64 17
2133#define VM_CtBlockVerify64 18
2134#define VM_CtHostRead64 19
2135#define VM_CtHostWrite64 20
2136#define VM_DrvErrTblLog 21
2137#define VM_NameServe64 22
2138#define VM_NameServeAllBlk 30
2139
2140#define MAX_VMCOMMAND_NUM 23
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150struct aac_fsinfo {
2151 __le32 fsTotalSize;
2152 __le32 fsBlockSize;
2153 __le32 fsFragSize;
2154 __le32 fsMaxExtendSize;
2155 __le32 fsSpaceUnits;
2156 __le32 fsMaxNumFiles;
2157 __le32 fsNumFreeFiles;
2158 __le32 fsInodeDensity;
2159};
2160
2161struct aac_blockdevinfo {
2162 __le32 block_size;
2163 __le32 logical_phys_map;
2164 u8 identifier[16];
2165};
2166
2167union aac_contentinfo {
2168 struct aac_fsinfo filesys;
2169 struct aac_blockdevinfo bdevinfo;
2170};
2171
2172
2173
2174
2175
2176#define CT_GET_CONFIG_STATUS 147
2177struct aac_get_config_status {
2178 __le32 command;
2179 __le32 type;
2180 __le32 parm1;
2181 __le32 parm2;
2182 __le32 parm3;
2183 __le32 parm4;
2184 __le32 parm5;
2185 __le32 count;
2186};
2187
2188#define CFACT_CONTINUE 0
2189#define CFACT_PAUSE 1
2190#define CFACT_ABORT 2
2191struct aac_get_config_status_resp {
2192 __le32 response;
2193 __le32 dummy0;
2194 __le32 status;
2195 __le32 parm1;
2196 __le32 parm2;
2197 __le32 parm3;
2198 __le32 parm4;
2199 __le32 parm5;
2200 struct {
2201 __le32 action;
2202 __le16 flags;
2203 __le16 count;
2204 } data;
2205};
2206
2207
2208
2209
2210
2211#define CT_COMMIT_CONFIG 152
2212
2213struct aac_commit_config {
2214 __le32 command;
2215 __le32 type;
2216};
2217
2218
2219
2220
2221
2222#define CT_GET_CONTAINER_COUNT 4
2223struct aac_get_container_count {
2224 __le32 command;
2225 __le32 type;
2226};
2227
2228struct aac_get_container_count_resp {
2229 __le32 response;
2230 __le32 dummy0;
2231 __le32 MaxContainers;
2232 __le32 ContainerSwitchEntries;
2233 __le32 MaxPartitions;
2234 __le32 MaxSimpleVolumes;
2235};
2236
2237
2238
2239
2240
2241
2242
2243struct aac_mntent {
2244 __le32 oid;
2245 u8 name[16];
2246 struct creation_info create_info;
2247 __le32 capacity;
2248 __le32 vol;
2249 __le32 obj;
2250 __le32 state;
2251
2252 union aac_contentinfo fileinfo;
2253
2254 __le32 altoid;
2255
2256 __le32 capacityhigh;
2257};
2258
2259#define FSCS_NOTCLEAN 0x0001
2260#define FSCS_READONLY 0x0002
2261#define FSCS_HIDDEN 0x0004
2262#define FSCS_NOT_READY 0x0008
2263
2264struct aac_query_mount {
2265 __le32 command;
2266 __le32 type;
2267 __le32 count;
2268};
2269
2270struct aac_mount {
2271 __le32 status;
2272 __le32 type;
2273 __le32 count;
2274 struct aac_mntent mnt[1];
2275};
2276
2277#define CT_READ_NAME 130
2278struct aac_get_name {
2279 __le32 command;
2280 __le32 type;
2281 __le32 cid;
2282 __le32 parm1;
2283 __le32 parm2;
2284 __le32 parm3;
2285 __le32 parm4;
2286 __le32 count;
2287};
2288
2289struct aac_get_name_resp {
2290 __le32 dummy0;
2291 __le32 dummy1;
2292 __le32 status;
2293 __le32 parm1;
2294 __le32 parm2;
2295 __le32 parm3;
2296 __le32 parm4;
2297 __le32 parm5;
2298 u8 data[17];
2299};
2300
2301#define CT_CID_TO_32BITS_UID 165
2302struct aac_get_serial {
2303 __le32 command;
2304 __le32 type;
2305 __le32 cid;
2306};
2307
2308struct aac_get_serial_resp {
2309 __le32 dummy0;
2310 __le32 dummy1;
2311 __le32 status;
2312 __le32 uid;
2313};
2314
2315
2316
2317
2318
2319struct aac_close {
2320 __le32 command;
2321 __le32 cid;
2322};
2323
2324struct aac_query_disk
2325{
2326 s32 cnum;
2327 s32 bus;
2328 s32 id;
2329 s32 lun;
2330 u32 valid;
2331 u32 locked;
2332 u32 deleted;
2333 s32 instance;
2334 s8 name[10];
2335 u32 unmapped;
2336};
2337
2338struct aac_delete_disk {
2339 u32 disknum;
2340 u32 cnum;
2341};
2342
2343struct fib_ioctl
2344{
2345 u32 fibctx;
2346 s32 wait;
2347 char __user *fib;
2348};
2349
2350struct revision
2351{
2352 u32 compat;
2353 __le32 version;
2354 __le32 build;
2355};
2356
2357
2358
2359
2360
2361
2362#define CTL_CODE(function, method) ( \
2363 (4<< 16) | ((function) << 2) | (method) \
2364)
2365
2366
2367
2368
2369
2370
2371#define METHOD_BUFFERED 0
2372#define METHOD_NEITHER 3
2373
2374
2375
2376
2377
2378#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2379#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2380#define FSACTL_DELETE_DISK 0x163
2381#define FSACTL_QUERY_DISK 0x173
2382#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2383#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2384#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2385#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2386#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2387#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2388#define FSACTL_GET_CONTAINERS 2131
2389#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2390#define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2391#define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2392
2393#define HW_IOP_RESET 0x01
2394#define HW_SOFT_RESET 0x02
2395#define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2396
2397#define IBW_SWR_OFFSET 0x4000
2398#define SOFT_RESET_TIME 60
2399
2400
2401
2402struct aac_common
2403{
2404
2405
2406
2407
2408 u32 irq_mod;
2409 u32 peak_fibs;
2410 u32 zero_fibs;
2411 u32 fib_timeouts;
2412
2413
2414
2415#ifdef DBG
2416 u32 FibsSent;
2417 u32 FibRecved;
2418 u32 NativeSent;
2419 u32 NativeRecved;
2420 u32 NoResponseSent;
2421 u32 NoResponseRecved;
2422 u32 AsyncSent;
2423 u32 AsyncRecved;
2424 u32 NormalSent;
2425 u32 NormalRecved;
2426#endif
2427};
2428
2429extern struct aac_common aac_config;
2430
2431
2432
2433
2434struct aac_hba_info {
2435
2436 u8 driver_name[50];
2437 u8 adapter_number;
2438 u8 system_io_bus_number;
2439 u8 device_number;
2440 u32 function_number;
2441 u32 vendor_id;
2442 u32 device_id;
2443 u32 sub_vendor_id;
2444 u32 sub_system_id;
2445 u32 mapped_base_address_size;
2446 u32 base_physical_address_high_part;
2447 u32 base_physical_address_low_part;
2448
2449 u32 max_command_size;
2450 u32 max_fib_size;
2451 u32 max_scatter_gather_from_os;
2452 u32 max_scatter_gather_to_fw;
2453 u32 max_outstanding_fibs;
2454
2455 u32 queue_start_threshold;
2456 u32 queue_dump_threshold;
2457 u32 max_io_size_queued;
2458 u32 outstanding_io;
2459
2460 u32 firmware_build_number;
2461 u32 bios_build_number;
2462 u32 driver_build_number;
2463 u32 serial_number_high_part;
2464 u32 serial_number_low_part;
2465 u32 supported_options;
2466 u32 feature_bits;
2467 u32 currentnumber_ports;
2468
2469 u8 new_comm_interface:1;
2470 u8 new_commands_supported:1;
2471 u8 disable_passthrough:1;
2472 u8 expose_non_dasd:1;
2473 u8 queue_allowed:1;
2474 u8 bled_check_enabled:1;
2475 u8 reserved1:1;
2476 u8 reserted2:1;
2477
2478 u32 reserved3[10];
2479
2480};
2481
2482
2483
2484
2485
2486
2487#ifdef DBG
2488#define FIB_COUNTER_INCREMENT(counter) (counter)++
2489#else
2490#define FIB_COUNTER_INCREMENT(counter)
2491#endif
2492
2493
2494
2495
2496
2497
2498#define BREAKPOINT_REQUEST 0x00000004
2499#define INIT_STRUCT_BASE_ADDRESS 0x00000005
2500#define READ_PERMANENT_PARAMETERS 0x0000000a
2501#define WRITE_PERMANENT_PARAMETERS 0x0000000b
2502#define HOST_CRASHING 0x0000000d
2503#define SEND_SYNCHRONOUS_FIB 0x0000000c
2504#define COMMAND_POST_RESULTS 0x00000014
2505#define GET_ADAPTER_PROPERTIES 0x00000019
2506#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2507#define RCV_TEMP_READINGS 0x00000025
2508#define GET_COMM_PREFERRED_SETTINGS 0x00000026
2509#define IOP_RESET_FW_FIB_DUMP 0x00000034
2510#define DROP_IO 0x00000035
2511#define IOP_RESET 0x00001000
2512#define IOP_RESET_ALWAYS 0x00001001
2513#define RE_INIT_ADAPTER 0x000000ee
2514
2515#define IOP_SRC_RESET_MASK 0x00000100
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538#define SELF_TEST_FAILED 0x00000004
2539#define MONITOR_PANIC 0x00000020
2540#define KERNEL_BOOTING 0x00000040
2541#define KERNEL_UP_AND_RUNNING 0x00000080
2542#define KERNEL_PANIC 0x00000100
2543#define FLASH_UPD_PENDING 0x00002000
2544#define FLASH_UPD_SUCCESS 0x00004000
2545#define FLASH_UPD_FAILED 0x00008000
2546#define INVALID_OMR 0xffffffff
2547#define FWUPD_TIMEOUT (5 * 60)
2548
2549
2550
2551
2552
2553#define DoorBellSyncCmdAvailable (1<<0)
2554#define DoorBellPrintfDone (1<<5)
2555#define DoorBellAdapterNormCmdReady (1<<1)
2556#define DoorBellAdapterNormRespReady (1<<2)
2557#define DoorBellAdapterNormCmdNotFull (1<<3)
2558#define DoorBellAdapterNormRespNotFull (1<<4)
2559#define DoorBellPrintfReady (1<<5)
2560#define DoorBellAifPending (1<<6)
2561
2562
2563#define PmDoorBellResponseSent (1<<1)
2564
2565
2566
2567
2568
2569
2570#define AifCmdEventNotify 1
2571#define AifEnConfigChange 3
2572#define AifEnContainerChange 4
2573#define AifEnDeviceFailure 5
2574#define AifEnEnclosureManagement 13
2575#define EM_DRIVE_INSERTION 31
2576#define EM_DRIVE_REMOVAL 32
2577#define EM_SES_DRIVE_INSERTION 33
2578#define EM_SES_DRIVE_REMOVAL 26
2579#define AifEnBatteryEvent 14
2580#define AifEnAddContainer 15
2581#define AifEnDeleteContainer 16
2582#define AifEnExpEvent 23
2583#define AifExeFirmwarePanic 3
2584#define AifHighPriority 3
2585#define AifEnAddJBOD 30
2586#define AifEnDeleteJBOD 31
2587
2588#define AifBuManagerEvent 42
2589#define AifBuCacheDataLoss 10
2590#define AifBuCacheDataRecover 11
2591
2592#define AifCmdJobProgress 2
2593#define AifJobCtrZero 101
2594#define AifJobStsSuccess 1
2595#define AifJobStsRunning 102
2596#define AifCmdAPIReport 3
2597#define AifCmdDriverNotify 4
2598#define AifDenMorphComplete 200
2599#define AifDenVolumeExtendComplete 201
2600#define AifReqJobList 100
2601#define AifReqJobsForCtr 101
2602#define AifReqJobsForScsi 102
2603#define AifReqJobReport 103
2604#define AifReqTerminateJob 104
2605#define AifReqSuspendJob 105
2606#define AifReqResumeJob 106
2607#define AifReqSendAPIReport 107
2608#define AifReqAPIJobStart 108
2609#define AifReqAPIJobUpdate 109
2610#define AifReqAPIJobFinish 110
2611
2612
2613#define AifReqEvent 200
2614#define AifRawDeviceRemove 203
2615#define AifNativeDeviceAdd 204
2616#define AifNativeDeviceRemove 205
2617
2618
2619
2620
2621
2622
2623
2624
2625struct aac_aifcmd {
2626 __le32 command;
2627 __le32 seqnum;
2628 u8 data[1];
2629};
2630
2631
2632
2633
2634
2635
2636static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2637{
2638 sector_div(capacity, divisor);
2639 return capacity;
2640}
2641
2642static inline int aac_adapter_check_health(struct aac_dev *dev)
2643{
2644 if (unlikely(pci_channel_offline(dev->pdev)))
2645 return -1;
2646
2647 return (dev)->a_ops.adapter_check_health(dev);
2648}
2649
2650
2651int aac_scan_host(struct aac_dev *dev);
2652
2653static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2654{
2655 schedule_delayed_work(&dev->safw_rescan_work, AAC_SAFW_RESCAN_DELAY);
2656}
2657
2658static inline void aac_safw_rescan_worker(struct work_struct *work)
2659{
2660 struct aac_dev *dev = container_of(to_delayed_work(work),
2661 struct aac_dev, safw_rescan_work);
2662
2663 wait_event(dev->scsi_host_ptr->host_wait,
2664 !scsi_host_in_recovery(dev->scsi_host_ptr));
2665
2666 aac_scan_host(dev);
2667}
2668
2669static inline void aac_cancel_safw_rescan_worker(struct aac_dev *dev)
2670{
2671 if (dev->sa_firmware)
2672 cancel_delayed_work_sync(&dev->safw_rescan_work);
2673}
2674
2675
2676#define AAC_OWNER_MIDLEVEL 0x101
2677#define AAC_OWNER_LOWLEVEL 0x102
2678#define AAC_OWNER_ERROR_HANDLER 0x103
2679#define AAC_OWNER_FIRMWARE 0x106
2680
2681void aac_safw_rescan_worker(struct work_struct *work);
2682int aac_acquire_irq(struct aac_dev *dev);
2683void aac_free_irq(struct aac_dev *dev);
2684int aac_setup_safw_adapter(struct aac_dev *dev);
2685const char *aac_driverinfo(struct Scsi_Host *);
2686void aac_fib_vector_assign(struct aac_dev *dev);
2687struct fib *aac_fib_alloc(struct aac_dev *dev);
2688struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2689int aac_fib_setup(struct aac_dev *dev);
2690void aac_fib_map_free(struct aac_dev *dev);
2691void aac_fib_free(struct fib * context);
2692void aac_fib_init(struct fib * context);
2693void aac_printf(struct aac_dev *dev, u32 val);
2694int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2695int aac_hba_send(u8 command, struct fib *context,
2696 fib_callback callback, void *ctxt);
2697int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2698void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2699int aac_fib_complete(struct fib * context);
2700void aac_hba_callback(void *context, struct fib *fibptr);
2701#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2702struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2703void aac_src_access_devreg(struct aac_dev *dev, int mode);
2704void aac_set_intx_mode(struct aac_dev *dev);
2705int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2706int aac_get_containers(struct aac_dev *dev);
2707int aac_scsi_cmd(struct scsi_cmnd *cmd);
2708int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2709#ifndef shost_to_class
2710#define shost_to_class(shost) &shost->shost_dev
2711#endif
2712ssize_t aac_get_serial_number(struct device *dev, char *buf);
2713int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2714int aac_rx_init(struct aac_dev *dev);
2715int aac_rkt_init(struct aac_dev *dev);
2716int aac_nark_init(struct aac_dev *dev);
2717int aac_sa_init(struct aac_dev *dev);
2718int aac_src_init(struct aac_dev *dev);
2719int aac_srcv_init(struct aac_dev *dev);
2720int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2721void aac_define_int_mode(struct aac_dev *dev);
2722unsigned int aac_response_normal(struct aac_queue * q);
2723unsigned int aac_command_normal(struct aac_queue * q);
2724unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2725 int isAif, int isFastResponse,
2726 struct hw_fib *aif_fib);
2727int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2728int aac_check_health(struct aac_dev * dev);
2729int aac_command_thread(void *data);
2730int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2731int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2732struct aac_driver_ident* aac_get_driver_ident(int devtype);
2733int aac_get_adapter_info(struct aac_dev* dev);
2734int aac_send_shutdown(struct aac_dev *dev);
2735int aac_probe_container(struct aac_dev *dev, int cid);
2736int _aac_rx_init(struct aac_dev *dev);
2737int aac_rx_select_comm(struct aac_dev *dev, int comm);
2738int aac_rx_deliver_producer(struct fib * fib);
2739
2740static inline int aac_is_src(struct aac_dev *dev)
2741{
2742 u16 device = dev->pdev->device;
2743
2744 if (device == PMC_DEVICE_S6 ||
2745 device == PMC_DEVICE_S7 ||
2746 device == PMC_DEVICE_S8)
2747 return 1;
2748 return 0;
2749}
2750
2751static inline int aac_supports_2T(struct aac_dev *dev)
2752{
2753 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2754}
2755
2756char * get_container_type(unsigned type);
2757extern int numacb;
2758extern char aac_driver_version[];
2759extern int startup_timeout;
2760extern int aif_timeout;
2761extern int expose_physicals;
2762extern int aac_reset_devices;
2763extern int aac_msi;
2764extern int aac_commit;
2765extern int update_interval;
2766extern int check_interval;
2767extern int aac_check_reset;
2768extern int aac_fib_dump;
2769#endif
2770