1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _GDTH_H 3#define _GDTH_H 4 5/* 6 * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux 7 * 8 * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner 9 * See gdth.c for further informations and 10 * below for supported controller types 11 * 12 * <achim_leubner@adaptec.com> 13 * 14 * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $ 15 */ 16 17#include <linux/types.h> 18 19#ifndef TRUE 20#define TRUE 1 21#endif 22#ifndef FALSE 23#define FALSE 0 24#endif 25 26/* defines, macros */ 27 28/* driver version */ 29#define GDTH_VERSION_STR "3.05" 30#define GDTH_VERSION 3 31#define GDTH_SUBVERSION 5 32 33/* protocol version */ 34#define PROTOCOL_VERSION 1 35 36/* OEM IDs */ 37#define OEM_ID_ICP 0x941c 38#define OEM_ID_INTEL 0x8000 39 40/* controller classes */ 41#define GDT_ISA 0x01 /* ISA controller */ 42#define GDT_EISA 0x02 /* EISA controller */ 43#define GDT_PCI 0x03 /* PCI controller */ 44#define GDT_PCINEW 0x04 /* new PCI controller */ 45#define GDT_PCIMPR 0x05 /* PCI MPR controller */ 46/* GDT_EISA, controller subtypes EISA */ 47#define GDT3_ID 0x0130941c /* GDT3000/3020 */ 48#define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */ 49#define GDT3B_ID 0x0330941c /* GDT3000B/3010A */ 50/* GDT_ISA */ 51#define GDT2_ID 0x0120941c /* GDT2000/2020 */ 52 53#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0 54/* GDT_PCI */ 55#define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */ 56#define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */ 57/* GDT_PCINEW */ 58#define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */ 59#define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */ 60#define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */ 61#define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */ 62/* GDT_PCINEW, wide/ultra SCSI controllers */ 63#define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */ 64#define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */ 65#define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */ 66#define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */ 67/* GDT_PCINEW, wide SCSI controllers */ 68#define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */ 69#define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */ 70#define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */ 71#define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */ 72#endif 73 74#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP 75/* GDT_MPR, RP series, wide/ultra SCSI */ 76#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */ 77#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */ 78#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */ 79#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */ 80/* GDT_MPR, RP series, narrow/ultra SCSI */ 81#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */ 82#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */ 83#endif 84#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD 85/* GDT_MPR, RD series, wide/ultra SCSI */ 86#define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */ 87#define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */ 88#define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */ 89#define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */ 90/* GDT_MPR, RD series, narrow/ultra SCSI */ 91#define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */ 92#define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */ 93/* GDT_MPR, RD series, wide/ultra2 SCSI */ 94#define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/ 95 GDT6618RD */ 96#define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/ 97 GDT6628RD */ 98#define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */ 99#define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */ 100/* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */ 101#define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/ 102 GDT7618RN */ 103#define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/ 104 GDT7628RN */ 105#define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */ 106#define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */ 107#endif 108 109#ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD 110/* GDT_MPR, RD series, Fibre Channel */ 111#define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */ 112#define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */ 113/* GDT_MPR, RN series (64-bit PCI), Fibre Channel */ 114#define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */ 115#define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */ 116#endif 117 118#ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP 119/* GDT_MPR, last device ID */ 120#define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff 121#endif 122 123#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX 124/* new GDT Rx Controller */ 125#define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300 126#endif 127 128#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2 129/* new(2) GDT Rx Controller */ 130#define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301 131#endif 132 133#ifndef PCI_DEVICE_ID_INTEL_SRC 134/* Intel Storage RAID Controller */ 135#define PCI_DEVICE_ID_INTEL_SRC 0x600 136#endif 137 138#ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE 139/* Intel Storage RAID Controller */ 140#define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601 141#endif 142 143/* limits */ 144#define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */ 145#define GDTH_MAXCMDS 120 146#define GDTH_MAXC_P_L 16 /* max. cmds per lun */ 147#define GDTH_MAX_RAW 2 /* max. cmds per raw device */ 148#define MAXOFFSETS 128 149#define MAXHA 16 150#define MAXID 127 151#define MAXLUN 8 152#define MAXBUS 6 153#define MAX_EVENTS 100 /* event buffer count */ 154#define MAX_RES_ARGS 40 /* device reservation, 155 must be a multiple of 4 */ 156#define MAXCYLS 1024 157#define HEADS 64 158#define SECS 32 /* mapping 64*32 */ 159#define MEDHEADS 127 160#define MEDSECS 63 /* mapping 127*63 */ 161#define BIGHEADS 255 162#define BIGSECS 63 /* mapping 255*63 */ 163 164/* special command ptr. */ 165#define UNUSED_CMND ((struct scsi_cmnd *)-1) 166#define INTERNAL_CMND ((struct scsi_cmnd *)-2) 167#define SCREEN_CMND ((struct scsi_cmnd *)-3) 168#define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND) 169 170/* controller services */ 171#define SCSIRAWSERVICE 3 172#define CACHESERVICE 9 173#define SCREENSERVICE 11 174 175/* screenservice defines */ 176#define MSG_INV_HANDLE -1 /* special message handle */ 177#define MSGLEN 16 /* size of message text */ 178#define MSG_SIZE 34 /* size of message structure */ 179#define MSG_REQUEST 0 /* async. event: message */ 180 181/* DPMEM constants */ 182#define DPMEM_MAGIC 0xC0FFEE11 183#define IC_HEADER_BYTES 48 184#define IC_QUEUE_BYTES 4 185#define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS 186 187/* cluster_type constants */ 188#define CLUSTER_DRIVE 1 189#define CLUSTER_MOUNTED 2 190#define CLUSTER_RESERVED 4 191#define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED) 192 193/* commands for all services, cache service */ 194#define GDT_INIT 0 /* service initialization */ 195#define GDT_READ 1 /* read command */ 196#define GDT_WRITE 2 /* write command */ 197#define GDT_INFO 3 /* information about devices */ 198#define GDT_FLUSH 4 /* flush dirty cache buffers */ 199#define GDT_IOCTL 5 /* ioctl command */ 200#define GDT_DEVTYPE 9 /* additional information */ 201#define GDT_MOUNT 10 /* mount cache device */ 202#define GDT_UNMOUNT 11 /* unmount cache device */ 203#define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */ 204#define GDT_GET_FEAT 13 /* get features */ 205#define GDT_WRITE_THR 16 /* write through */ 206#define GDT_READ_THR 17 /* read through */ 207#define GDT_EXT_INFO 18 /* extended info */ 208#define GDT_RESET 19 /* controller reset */ 209#define GDT_RESERVE_DRV 20 /* reserve host drive */ 210#define GDT_RELEASE_DRV 21 /* release host drive */ 211#define GDT_CLUST_INFO 22 /* cluster info */ 212#define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/ 213#define GDT_CLUST_RESET 24 /* releases the cluster drives*/ 214#define GDT_FREEZE_IO 25 /* freezes all IOs */ 215#define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */ 216#define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */ 217#define GDT_X_INFO 30 /* ext. info for drives>2TB */ 218 219/* raw service commands */ 220#define GDT_RESERVE 14 /* reserve dev. to raw serv. */ 221#define GDT_RELEASE 15 /* release device */ 222#define GDT_RESERVE_ALL 16 /* reserve all devices */ 223#define GDT_RELEASE_ALL 17 /* release all devices */ 224#define GDT_RESET_BUS 18 /* reset bus */ 225#define GDT_SCAN_START 19 /* start device scan */ 226#define GDT_SCAN_END 20 /* stop device scan */ 227#define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */ 228 229/* screen service commands */ 230#define GDT_REALTIME 3 /* realtime clock to screens. */ 231#define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */ 232 233/* IOCTL command defines */ 234#define SCSI_DR_INFO 0x00 /* SCSI drive info */ 235#define SCSI_CHAN_CNT 0x05 /* SCSI channel count */ 236#define SCSI_DR_LIST 0x06 /* SCSI drive list */ 237#define SCSI_DEF_CNT 0x15 /* grown/primary defects */ 238#define DSK_STATISTICS 0x4b /* SCSI disk statistics */ 239#define IOCHAN_DESC 0x5d /* description of IO channel */ 240#define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */ 241#define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */ 242#define ARRAY_INFO 0x12 /* array drive info */ 243#define ARRAY_DRV_LIST 0x0f /* array drive list */ 244#define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */ 245#define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */ 246#define CACHE_DRV_CNT 0x01 /* cache drive count */ 247#define CACHE_DRV_LIST 0x02 /* cache drive list */ 248#define CACHE_INFO 0x04 /* cache info */ 249#define CACHE_CONFIG 0x05 /* cache configuration */ 250#define CACHE_DRV_INFO 0x07 /* cache drive info */ 251#define BOARD_FEATURES 0x15 /* controller features */ 252#define BOARD_INFO 0x28 /* controller info */ 253#define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */ 254#define GET_PERF_MODES 0x83 /* get mode */ 255#define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */ 256#define HOST_GET 0x10001L /* get host drive list */ 257#define IO_CHANNEL 0x00020000L /* default IO channel */ 258#define INVALID_CHANNEL 0x0000ffffL /* invalid channel */ 259 260/* service errors */ 261#define S_OK 1 /* no error */ 262#define S_GENERR 6 /* general error */ 263#define S_BSY 7 /* controller busy */ 264#define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */ 265#define S_RAW_SCSI 12 /* raw serv.: target error */ 266#define S_RAW_ILL 0xff /* raw serv.: illegal */ 267#define S_NOFUNC -2 /* unknown function */ 268#define S_CACHE_RESERV -24 /* cache: reserv. conflict */ 269 270/* timeout values */ 271#define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */ 272#define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */ 273#define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */ 274 275/* priorities */ 276#define DEFAULT_PRI 0x20 277#define IOCTL_PRI 0x10 278#define HIGH_PRI 0x08 279 280/* data directions */ 281#define GDTH_DATA_IN 0x01000000L /* data from target */ 282#define GDTH_DATA_OUT 0x00000000L /* data to target */ 283 284/* BMIC registers (EISA controllers) */ 285#define ID0REG 0x0c80 /* board ID */ 286#define EINTENABREG 0x0c89 /* interrupt enable */ 287#define SEMA0REG 0x0c8a /* command semaphore */ 288#define SEMA1REG 0x0c8b /* status semaphore */ 289#define LDOORREG 0x0c8d /* local doorbell */ 290#define EDENABREG 0x0c8e /* EISA system doorbell enab. */ 291#define EDOORREG 0x0c8f /* EISA system doorbell */ 292#define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */ 293#define EISAREG 0x0cc0 /* EISA configuration */ 294 295/* other defines */ 296#define LINUX_OS 8 /* used for cache optim. */ 297#define SECS32 0x1f /* round capacity */ 298#define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */ 299#define LOCALBOARD 0 /* board node always 0 */ 300#define ASYNCINDEX 0 /* cmd index async. event */ 301#define SPEZINDEX 1 /* cmd index unknown service */ 302#define COALINDEX (GDTH_MAXCMDS + 2) 303 304/* features */ 305#define SCATTER_GATHER 1 /* s/g feature */ 306#define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */ 307#define GDT_64BIT 0x200 /* 64bit / drv>2TB support */ 308 309#include "gdth_ioctl.h" 310 311/* screenservice message */ 312typedef struct { 313 u32 msg_handle; /* message handle */ 314 u32 msg_len; /* size of message */ 315 u32 msg_alen; /* answer length */ 316 u8 msg_answer; /* answer flag */ 317 u8 msg_ext; /* more messages */ 318 u8 msg_reserved[2]; 319 char msg_text[MSGLEN+2]; /* the message text */ 320} __attribute__((packed)) gdth_msg_str; 321 322 323/* IOCTL data structures */ 324 325/* Status coalescing buffer for returning multiple requests per interrupt */ 326typedef struct { 327 u32 status; 328 u32 ext_status; 329 u32 info0; 330 u32 info1; 331} __attribute__((packed)) gdth_coal_status; 332 333/* performance mode data structure */ 334typedef struct { 335 u32 version; /* The version of this IOCTL structure. */ 336 u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */ 337 u32 st_buff_addr1; /* physical address of status buffer 1 */ 338 u32 st_buff_u_addr1; /* reserved for 64 bit addressing */ 339 u32 st_buff_indx1; /* reserved command idx. for this buffer */ 340 u32 st_buff_addr2; /* physical address of status buffer 1 */ 341 u32 st_buff_u_addr2; /* reserved for 64 bit addressing */ 342 u32 st_buff_indx2; /* reserved command idx. for this buffer */ 343 u32 st_buff_size; /* size of each buffer in bytes */ 344 u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */ 345 u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */ 346 u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */ 347 u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */ 348 u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */ 349 u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */ 350 u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */ 351 u32 cmd_buff_size; /* size of each cmd buffer in bytes */ 352 u32 reserved1; 353 u32 reserved2; 354} __attribute__((packed)) gdth_perf_modes; 355 356/* SCSI drive info */ 357typedef struct { 358 u8 vendor[8]; /* vendor string */ 359 u8 product[16]; /* product string */ 360 u8 revision[4]; /* revision */ 361 u32 sy_rate; /* current rate for sync. tr. */ 362 u32 sy_max_rate; /* max. rate for sync. tr. */ 363 u32 no_ldrive; /* belongs to this log. drv.*/ 364 u32 blkcnt; /* number of blocks */ 365 u16 blksize; /* size of block in bytes */ 366 u8 available; /* flag: access is available */ 367 u8 init; /* medium is initialized */ 368 u8 devtype; /* SCSI devicetype */ 369 u8 rm_medium; /* medium is removable */ 370 u8 wp_medium; /* medium is write protected */ 371 u8 ansi; /* SCSI I/II or III? */ 372 u8 protocol; /* same as ansi */ 373 u8 sync; /* flag: sync. transfer enab. */ 374 u8 disc; /* flag: disconnect enabled */ 375 u8 queueing; /* flag: command queing enab. */ 376 u8 cached; /* flag: caching enabled */ 377 u8 target_id; /* target ID of device */ 378 u8 lun; /* LUN id of device */ 379 u8 orphan; /* flag: drive fragment */ 380 u32 last_error; /* sense key or drive state */ 381 u32 last_result; /* result of last command */ 382 u32 check_errors; /* err. in last surface check */ 383 u8 percent; /* progress for surface check */ 384 u8 last_check; /* IOCTRL operation */ 385 u8 res[2]; 386 u32 flags; /* from 1.19/2.19: raw reserv.*/ 387 u8 multi_bus; /* multi bus dev? (fibre ch.) */ 388 u8 mb_status; /* status: available? */ 389 u8 res2[2]; 390 u8 mb_alt_status; /* status on second bus */ 391 u8 mb_alt_bid; /* number of second bus */ 392 u8 mb_alt_tid; /* target id on second bus */ 393 u8 res3; 394 u8 fc_flag; /* from 1.22/2.22: info valid?*/ 395 u8 res4; 396 u16 fc_frame_size; /* frame size (bytes) */ 397 char wwn[8]; /* world wide name */ 398} __attribute__((packed)) gdth_diskinfo_str; 399 400/* get SCSI channel count */ 401typedef struct { 402 u32 channel_no; /* number of channel */ 403 u32 drive_cnt; /* drive count */ 404 u8 siop_id; /* SCSI processor ID */ 405 u8 siop_state; /* SCSI processor state */ 406} __attribute__((packed)) gdth_getch_str; 407 408/* get SCSI drive numbers */ 409typedef struct { 410 u32 sc_no; /* SCSI channel */ 411 u32 sc_cnt; /* sc_list[] elements */ 412 u32 sc_list[MAXID]; /* minor device numbers */ 413} __attribute__((packed)) gdth_drlist_str; 414 415/* get grown/primary defect count */ 416typedef struct { 417 u8 sddc_type; /* 0x08: grown, 0x10: prim. */ 418 u8 sddc_format; /* list entry format */ 419 u8 sddc_len; /* list entry length */ 420 u8 sddc_res; 421 u32 sddc_cnt; /* entry count */ 422} __attribute__((packed)) gdth_defcnt_str; 423 424/* disk statistics */ 425typedef struct { 426 u32 bid; /* SCSI channel */ 427 u32 first; /* first SCSI disk */ 428 u32 entries; /* number of elements */ 429 u32 count; /* (R) number of init. el. */ 430 u32 mon_time; /* time stamp */ 431 struct { 432 u8 tid; /* target ID */ 433 u8 lun; /* LUN */ 434 u8 res[2]; 435 u32 blk_size; /* block size in bytes */ 436 u32 rd_count; /* bytes read */ 437 u32 wr_count; /* bytes written */ 438 u32 rd_blk_count; /* blocks read */ 439 u32 wr_blk_count; /* blocks written */ 440 u32 retries; /* retries */ 441 u32 reassigns; /* reassigns */ 442 } __attribute__((packed)) list[1]; 443} __attribute__((packed)) gdth_dskstat_str; 444 445/* IO channel header */ 446typedef struct { 447 u32 version; /* version (-1UL: newest) */ 448 u8 list_entries; /* list entry count */ 449 u8 first_chan; /* first channel number */ 450 u8 last_chan; /* last channel number */ 451 u8 chan_count; /* (R) channel count */ 452 u32 list_offset; /* offset of list[0] */ 453} __attribute__((packed)) gdth_iochan_header; 454 455/* get IO channel description */ 456typedef struct { 457 gdth_iochan_header hdr; 458 struct { 459 u32 address; /* channel address */ 460 u8 type; /* type (SCSI, FCAL) */ 461 u8 local_no; /* local number */ 462 u16 features; /* channel features */ 463 } __attribute__((packed)) list[MAXBUS]; 464} __attribute__((packed)) gdth_iochan_str; 465 466/* get raw IO channel description */ 467typedef struct { 468 gdth_iochan_header hdr; 469 struct { 470 u8 proc_id; /* processor id */ 471 u8 proc_defect; /* defect ? */ 472 u8 reserved[2]; 473 } __attribute__((packed)) list[MAXBUS]; 474} __attribute__((packed)) gdth_raw_iochan_str; 475 476/* array drive component */ 477typedef struct { 478 u32 al_controller; /* controller ID */ 479 u8 al_cache_drive; /* cache drive number */ 480 u8 al_status; /* cache drive state */ 481 u8 al_res[2]; 482} __attribute__((packed)) gdth_arraycomp_str; 483 484/* array drive information */ 485typedef struct { 486 u8 ai_type; /* array type (RAID0,4,5) */ 487 u8 ai_cache_drive_cnt; /* active cachedrives */ 488 u8 ai_state; /* array drive state */ 489 u8 ai_master_cd; /* master cachedrive */ 490 u32 ai_master_controller; /* ID of master controller */ 491 u32 ai_size; /* user capacity [sectors] */ 492 u32 ai_striping_size; /* striping size [sectors] */ 493 u32 ai_secsize; /* sector size [bytes] */ 494 u32 ai_err_info; /* failed cache drive */ 495 u8 ai_name[8]; /* name of the array drive */ 496 u8 ai_controller_cnt; /* number of controllers */ 497 u8 ai_removable; /* flag: removable */ 498 u8 ai_write_protected; /* flag: write protected */ 499 u8 ai_devtype; /* type: always direct access */ 500 gdth_arraycomp_str ai_drives[35]; /* drive components: */ 501 u8 ai_drive_entries; /* number of drive components */ 502 u8 ai_protected; /* protection flag */ 503 u8 ai_verify_state; /* state of a parity verify */ 504 u8 ai_ext_state; /* extended array drive state */ 505 u8 ai_expand_state; /* array expand state (>=2.18)*/ 506 u8 ai_reserved[3]; 507} __attribute__((packed)) gdth_arrayinf_str; 508 509/* get array drive list */ 510typedef struct { 511 u32 controller_no; /* controller no. */ 512 u8 cd_handle; /* master cachedrive */ 513 u8 is_arrayd; /* Flag: is array drive? */ 514 u8 is_master; /* Flag: is array master? */ 515 u8 is_parity; /* Flag: is parity drive? */ 516 u8 is_hotfix; /* Flag: is hotfix drive? */ 517 u8 res[3]; 518} __attribute__((packed)) gdth_alist_str; 519 520typedef struct { 521 u32 entries_avail; /* allocated entries */ 522 u32 entries_init; /* returned entries */ 523 u32 first_entry; /* first entry number */ 524 u32 list_offset; /* offset of following list */ 525 gdth_alist_str list[1]; /* list */ 526} __attribute__((packed)) gdth_arcdl_str; 527 528/* cache info/config IOCTL */ 529typedef struct { 530 u32 version; /* firmware version */ 531 u16 state; /* cache state (on/off) */ 532 u16 strategy; /* cache strategy */ 533 u16 write_back; /* write back state (on/off) */ 534 u16 block_size; /* cache block size */ 535} __attribute__((packed)) gdth_cpar_str; 536 537typedef struct { 538 u32 csize; /* cache size */ 539 u32 read_cnt; /* read/write counter */ 540 u32 write_cnt; 541 u32 tr_hits; /* hits */ 542 u32 sec_hits; 543 u32 sec_miss; /* misses */ 544} __attribute__((packed)) gdth_cstat_str; 545 546typedef struct { 547 gdth_cpar_str cpar; 548 gdth_cstat_str cstat; 549} __attribute__((packed)) gdth_cinfo_str; 550 551/* cache drive info */ 552typedef struct { 553 u8 cd_name[8]; /* cache drive name */ 554 u32 cd_devtype; /* SCSI devicetype */ 555 u32 cd_ldcnt; /* number of log. drives */ 556 u32 cd_last_error; /* last error */ 557 u8 cd_initialized; /* drive is initialized */ 558 u8 cd_removable; /* media is removable */ 559 u8 cd_write_protected; /* write protected */ 560 u8 cd_flags; /* Pool Hot Fix? */ 561 u32 ld_blkcnt; /* number of blocks */ 562 u32 ld_blksize; /* blocksize */ 563 u32 ld_dcnt; /* number of disks */ 564 u32 ld_slave; /* log. drive index */ 565 u32 ld_dtype; /* type of logical drive */ 566 u32 ld_last_error; /* last error */ 567 u8 ld_name[8]; /* log. drive name */ 568 u8 ld_error; /* error */ 569} __attribute__((packed)) gdth_cdrinfo_str; 570 571/* OEM string */ 572typedef struct { 573 u32 ctl_version; 574 u32 file_major_version; 575 u32 file_minor_version; 576 u32 buffer_size; 577 u32 cpy_count; 578 u32 ext_error; 579 u32 oem_id; 580 u32 board_id; 581} __attribute__((packed)) gdth_oem_str_params; 582 583typedef struct { 584 u8 product_0_1_name[16]; 585 u8 product_4_5_name[16]; 586 u8 product_cluster_name[16]; 587 u8 product_reserved[16]; 588 u8 scsi_cluster_target_vendor_id[16]; 589 u8 cluster_raid_fw_name[16]; 590 u8 oem_brand_name[16]; 591 u8 oem_raid_type[16]; 592 u8 bios_type[13]; 593 u8 bios_title[50]; 594 u8 oem_company_name[37]; 595 u32 pci_id_1; 596 u32 pci_id_2; 597 u8 validation_status[80]; 598 u8 reserved_1[4]; 599 u8 scsi_host_drive_inquiry_vendor_id[16]; 600 u8 library_file_template[16]; 601 u8 reserved_2[16]; 602 u8 tool_name_1[32]; 603 u8 tool_name_2[32]; 604 u8 tool_name_3[32]; 605 u8 oem_contact_1[84]; 606 u8 oem_contact_2[84]; 607 u8 oem_contact_3[84]; 608} __attribute__((packed)) gdth_oem_str; 609 610typedef struct { 611 gdth_oem_str_params params; 612 gdth_oem_str text; 613} __attribute__((packed)) gdth_oem_str_ioctl; 614 615/* board features */ 616typedef struct { 617 u8 chaining; /* Chaining supported */ 618 u8 striping; /* Striping (RAID-0) supp. */ 619 u8 mirroring; /* Mirroring (RAID-1) supp. */ 620 u8 raid; /* RAID-4/5/10 supported */ 621} __attribute__((packed)) gdth_bfeat_str; 622 623/* board info IOCTL */ 624typedef struct { 625 u32 ser_no; /* serial no. */ 626 u8 oem_id[2]; /* OEM ID */ 627 u16 ep_flags; /* eprom flags */ 628 u32 proc_id; /* processor ID */ 629 u32 memsize; /* memory size (bytes) */ 630 u8 mem_banks; /* memory banks */ 631 u8 chan_type; /* channel type */ 632 u8 chan_count; /* channel count */ 633 u8 rdongle_pres; /* dongle present? */ 634 u32 epr_fw_ver; /* (eprom) firmware version */ 635 u32 upd_fw_ver; /* (update) firmware version */ 636 u32 upd_revision; /* update revision */ 637 char type_string[16]; /* controller name */ 638 char raid_string[16]; /* RAID firmware name */ 639 u8 update_pres; /* update present? */ 640 u8 xor_pres; /* XOR engine present? */ 641 u8 prom_type; /* ROM type (eprom/flash) */ 642 u8 prom_count; /* number of ROM devices */ 643 u32 dup_pres; /* duplexing module present? */ 644 u32 chan_pres; /* number of expansion chn. */ 645 u32 mem_pres; /* memory expansion inst. ? */ 646 u8 ft_bus_system; /* fault bus supported? */ 647 u8 subtype_valid; /* board_subtype valid? */ 648 u8 board_subtype; /* subtype/hardware level */ 649 u8 ramparity_pres; /* RAM parity check hardware? */ 650} __attribute__((packed)) gdth_binfo_str; 651 652/* get host drive info */ 653typedef struct { 654 char name[8]; /* host drive name */ 655 u32 size; /* size (sectors) */ 656 u8 host_drive; /* host drive number */ 657 u8 log_drive; /* log. drive (master) */ 658 u8 reserved; 659 u8 rw_attribs; /* r/w attribs */ 660 u32 start_sec; /* start sector */ 661} __attribute__((packed)) gdth_hentry_str; 662 663typedef struct { 664 u32 entries; /* entry count */ 665 u32 offset; /* offset of entries */ 666 u8 secs_p_head; /* sectors/head */ 667 u8 heads_p_cyl; /* heads/cylinder */ 668 u8 reserved; 669 u8 clust_drvtype; /* cluster drive type */ 670 u32 location; /* controller number */ 671 gdth_hentry_str entry[MAX_HDRIVES]; /* entries */ 672} __attribute__((packed)) gdth_hget_str; 673 674 675/* DPRAM structures */ 676 677/* interface area ISA/PCI */ 678typedef struct { 679 u8 S_Cmd_Indx; /* special command */ 680 u8 volatile S_Status; /* status special command */ 681 u16 reserved1; 682 u32 S_Info[4]; /* add. info special command */ 683 u8 volatile Sema0; /* command semaphore */ 684 u8 reserved2[3]; 685 u8 Cmd_Index; /* command number */ 686 u8 reserved3[3]; 687 u16 volatile Status; /* command status */ 688 u16 Service; /* service(for async.events) */ 689 u32 Info[2]; /* additional info */ 690 struct { 691 u16 offset; /* command offs. in the DPRAM*/ 692 u16 serv_id; /* service */ 693 } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */ 694 u32 bios_reserved[2]; 695 u8 gdt_dpr_cmd[1]; /* commands */ 696} __attribute__((packed)) gdt_dpr_if; 697 698/* SRAM structure PCI controllers */ 699typedef struct { 700 u32 magic; /* controller ID from BIOS */ 701 u16 need_deinit; /* switch betw. BIOS/driver */ 702 u8 switch_support; /* see need_deinit */ 703 u8 padding[9]; 704 u8 os_used[16]; /* OS code per service */ 705 u8 unused[28]; 706 u8 fw_magic; /* contr. ID from firmware */ 707} __attribute__((packed)) gdt_pci_sram; 708 709/* SRAM structure EISA controllers (but NOT GDT3000/3020) */ 710typedef struct { 711 u8 os_used[16]; /* OS code per service */ 712 u16 need_deinit; /* switch betw. BIOS/driver */ 713 u8 switch_support; /* see need_deinit */ 714 u8 padding; 715} __attribute__((packed)) gdt_eisa_sram; 716 717 718/* DPRAM ISA controllers */ 719typedef struct { 720 union { 721 struct { 722 u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */ 723 u32 magic; /* controller (EISA) ID */ 724 u16 need_deinit; /* switch betw. BIOS/driver */ 725 u8 switch_support; /* see need_deinit */ 726 u8 padding[9]; 727 u8 os_used[16]; /* OS code per service */ 728 } __attribute__((packed)) dp_sram; 729 u8 bios_area[0x4000]; /* 16KB reserved for BIOS */ 730 } bu; 731 union { 732 gdt_dpr_if ic; /* interface area */ 733 u8 if_area[0x3000]; /* 12KB for interface */ 734 } u; 735 struct { 736 u8 memlock; /* write protection DPRAM */ 737 u8 event; /* release event */ 738 u8 irqen; /* board interrupts enable */ 739 u8 irqdel; /* acknowledge board int. */ 740 u8 volatile Sema1; /* status semaphore */ 741 u8 rq; /* IRQ/DRQ configuration */ 742 } __attribute__((packed)) io; 743} __attribute__((packed)) gdt2_dpram_str; 744 745/* DPRAM PCI controllers */ 746typedef struct { 747 union { 748 gdt_dpr_if ic; /* interface area */ 749 u8 if_area[0xff0-sizeof(gdt_pci_sram)]; 750 } u; 751 gdt_pci_sram gdt6sr; /* SRAM structure */ 752 struct { 753 u8 unused0[1]; 754 u8 volatile Sema1; /* command semaphore */ 755 u8 unused1[3]; 756 u8 irqen; /* board interrupts enable */ 757 u8 unused2[2]; 758 u8 event; /* release event */ 759 u8 unused3[3]; 760 u8 irqdel; /* acknowledge board int. */ 761 u8 unused4[3]; 762 } __attribute__((packed)) io; 763} __attribute__((packed)) gdt6_dpram_str; 764 765/* PLX register structure (new PCI controllers) */ 766typedef struct { 767 u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/ 768 u8 unused1[0x3f]; 769 u8 volatile sema0_reg; /* command semaphore */ 770 u8 volatile sema1_reg; /* status semaphore */ 771 u8 unused2[2]; 772 u16 volatile status; /* command status */ 773 u16 service; /* service */ 774 u32 info[2]; /* additional info */ 775 u8 unused3[0x10]; 776 u8 ldoor_reg; /* PCI to local doorbell */ 777 u8 unused4[3]; 778 u8 volatile edoor_reg; /* local to PCI doorbell */ 779 u8 unused5[3]; 780 u8 control0; /* control0 register(unused) */ 781 u8 control1; /* board interrupts enable */ 782 u8 unused6[0x16]; 783} __attribute__((packed)) gdt6c_plx_regs; 784 785/* DPRAM new PCI controllers */ 786typedef struct { 787 union { 788 gdt_dpr_if ic; /* interface area */ 789 u8 if_area[0x4000-sizeof(gdt_pci_sram)]; 790 } u; 791 gdt_pci_sram gdt6sr; /* SRAM structure */ 792} __attribute__((packed)) gdt6c_dpram_str; 793 794/* i960 register structure (PCI MPR controllers) */ 795typedef struct { 796 u8 unused1[16]; 797 u8 volatile sema0_reg; /* command semaphore */ 798 u8 unused2; 799 u8 volatile sema1_reg; /* status semaphore */ 800 u8 unused3; 801 u16 volatile status; /* command status */ 802 u16 service; /* service */ 803 u32 info[2]; /* additional info */ 804 u8 ldoor_reg; /* PCI to local doorbell */ 805 u8 unused4[11]; 806 u8 volatile edoor_reg; /* local to PCI doorbell */ 807 u8 unused5[7]; 808 u8 edoor_en_reg; /* board interrupts enable */ 809 u8 unused6[27]; 810 u32 unused7[939]; 811 u32 severity; 812 char evt_str[256]; /* event string */ 813} __attribute__((packed)) gdt6m_i960_regs; 814 815/* DPRAM PCI MPR controllers */ 816typedef struct { 817 gdt6m_i960_regs i960r; /* 4KB i960 registers */ 818 union { 819 gdt_dpr_if ic; /* interface area */ 820 u8 if_area[0x3000-sizeof(gdt_pci_sram)]; 821 } u; 822 gdt_pci_sram gdt6sr; /* SRAM structure */ 823} __attribute__((packed)) gdt6m_dpram_str; 824 825 826/* PCI resources */ 827typedef struct { 828 struct pci_dev *pdev; 829 unsigned long dpmem; /* DPRAM address */ 830 unsigned long io; /* IO address */ 831} gdth_pci_str; 832 833 834/* controller information structure */ 835typedef struct { 836 struct Scsi_Host *shost; 837 struct list_head list; 838 u16 hanum; 839 u16 oem_id; /* OEM */ 840 u16 type; /* controller class */ 841 u32 stype; /* subtype (PCI: device ID) */ 842 u16 fw_vers; /* firmware version */ 843 u16 cache_feat; /* feat. cache serv. (s/g,..)*/ 844 u16 raw_feat; /* feat. raw service (s/g,..)*/ 845 u16 screen_feat; /* feat. raw service (s/g,..)*/ 846 u16 bmic; /* BMIC address (EISA) */ 847 void __iomem *brd; /* DPRAM address */ 848 u32 brd_phys; /* slot number/BIOS address */ 849 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */ 850 gdth_cmd_str cmdext; 851 gdth_cmd_str *pccb; /* address command structure */ 852 u32 ccb_phys; /* phys. address */ 853#ifdef INT_COAL 854 gdth_coal_status *coal_stat; /* buffer for coalescing int.*/ 855 u64 coal_stat_phys; /* phys. address */ 856#endif 857 char *pscratch; /* scratch (DMA) buffer */ 858 u64 scratch_phys; /* phys. address */ 859 u8 scratch_busy; /* in use? */ 860 u8 dma64_support; /* 64-bit DMA supported? */ 861 gdth_msg_str *pmsg; /* message buffer */ 862 u64 msg_phys; /* phys. address */ 863 u8 scan_mode; /* current scan mode */ 864 u8 irq; /* IRQ */ 865 u8 drq; /* DRQ (ISA controllers) */ 866 u16 status; /* command status */ 867 u16 service; /* service/firmware ver./.. */ 868 u32 info; 869 u32 info2; /* additional info */ 870 struct scsi_cmnd *req_first; /* top of request queue */ 871 struct { 872 u8 present; /* Flag: host drive present? */ 873 u8 is_logdrv; /* Flag: log. drive (master)? */ 874 u8 is_arraydrv; /* Flag: array drive? */ 875 u8 is_master; /* Flag: array drive master? */ 876 u8 is_parity; /* Flag: parity drive? */ 877 u8 is_hotfix; /* Flag: hotfix drive? */ 878 u8 master_no; /* number of master drive */ 879 u8 lock; /* drive locked? (hot plug) */ 880 u8 heads; /* mapping */ 881 u8 secs; 882 u16 devtype; /* further information */ 883 u64 size; /* capacity */ 884 u8 ldr_no; /* log. drive no. */ 885 u8 rw_attribs; /* r/w attributes */ 886 u8 cluster_type; /* cluster properties */ 887 u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */ 888 u32 start_sec; /* start sector */ 889 } hdr[MAX_LDRIVES]; /* host drives */ 890 struct { 891 u8 lock; /* channel locked? (hot plug) */ 892 u8 pdev_cnt; /* physical device count */ 893 u8 local_no; /* local channel number */ 894 u8 io_cnt[MAXID]; /* current IO count */ 895 u32 address; /* channel address */ 896 u32 id_list[MAXID]; /* IDs of the phys. devices */ 897 } raw[MAXBUS]; /* SCSI channels */ 898 struct { 899 struct scsi_cmnd *cmnd; /* pending request */ 900 u16 service; /* service */ 901 } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */ 902 struct gdth_cmndinfo { /* per-command private info */ 903 int index; 904 int internal_command; /* don't call scsi_done */ 905 gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/ 906 dma_addr_t sense_paddr; /* sense dma-addr */ 907 u8 priority; 908 int timeout_count; /* # of timeout calls */ 909 volatile int wait_for_completion; 910 u16 status; 911 u32 info; 912 enum dma_data_direction dma_dir; 913 int phase; /* ???? */ 914 int OpCode; 915 } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */ 916 u8 bus_cnt; /* SCSI bus count */ 917 u8 tid_cnt; /* Target ID count */ 918 u8 bus_id[MAXBUS]; /* IOP IDs */ 919 u8 virt_bus; /* number of virtual bus */ 920 u8 more_proc; /* more /proc info supported */ 921 u16 cmd_cnt; /* command count in DPRAM */ 922 u16 cmd_len; /* length of actual command */ 923 u16 cmd_offs_dpmem; /* actual offset in DPRAM */ 924 u16 ic_all_size; /* sizeof DPRAM interf. area */ 925 gdth_cpar_str cpar; /* controller cache par. */ 926 gdth_bfeat_str bfeat; /* controller features */ 927 gdth_binfo_str binfo; /* controller info */ 928 gdth_evt_data dvr; /* event structure */ 929 spinlock_t smp_lock; 930 struct pci_dev *pdev; 931 char oem_name[8]; 932#ifdef GDTH_DMA_STATISTICS 933 unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */ 934#endif 935 struct scsi_device *sdev; 936} gdth_ha_str; 937 938static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd) 939{ 940 return (struct gdth_cmndinfo *)cmd->host_scribble; 941} 942 943/* INQUIRY data format */ 944typedef struct { 945 u8 type_qual; 946 u8 modif_rmb; 947 u8 version; 948 u8 resp_aenc; 949 u8 add_length; 950 u8 reserved1; 951 u8 reserved2; 952 u8 misc; 953 u8 vendor[8]; 954 u8 product[16]; 955 u8 revision[4]; 956} __attribute__((packed)) gdth_inq_data; 957 958/* READ_CAPACITY data format */ 959typedef struct { 960 u32 last_block_no; 961 u32 block_length; 962} __attribute__((packed)) gdth_rdcap_data; 963 964/* READ_CAPACITY (16) data format */ 965typedef struct { 966 u64 last_block_no; 967 u32 block_length; 968} __attribute__((packed)) gdth_rdcap16_data; 969 970/* REQUEST_SENSE data format */ 971typedef struct { 972 u8 errorcode; 973 u8 segno; 974 u8 key; 975 u32 info; 976 u8 add_length; 977 u32 cmd_info; 978 u8 adsc; 979 u8 adsq; 980 u8 fruc; 981 u8 key_spec[3]; 982} __attribute__((packed)) gdth_sense_data; 983 984/* MODE_SENSE data format */ 985typedef struct { 986 struct { 987 u8 data_length; 988 u8 med_type; 989 u8 dev_par; 990 u8 bd_length; 991 } __attribute__((packed)) hd; 992 struct { 993 u8 dens_code; 994 u8 block_count[3]; 995 u8 reserved; 996 u8 block_length[3]; 997 } __attribute__((packed)) bd; 998} __attribute__((packed)) gdth_modep_data; 999 1000/* stack frame */
1001typedef struct { 1002 unsigned long b[10]; /* 32/64 bit compiler ! */ 1003} __attribute__((packed)) gdth_stackframe; 1004 1005 1006/* function prototyping */ 1007 1008int gdth_show_info(struct seq_file *, struct Scsi_Host *); 1009int gdth_set_info(struct Scsi_Host *, char *, int); 1010 1011#endif 1012