LXR linux/drivers/scsi/qla2xxx/qla

   1/*
   2 * QLogic Fibre Channel HBA Driver
   3 * Copyright (c)  2003-2014 QLogic Corporation
   4 *
   5 * See LICENSE.qla2xxx for copyright and licensing details.
   6 */
   7#ifndef __QLA_FW_H
   8#define __QLA_FW_H
   9
  10#include <linux/nvme.h>
  11#include <linux/nvme-fc.h>
  12
  13#include "qla_dsd.h"
  14
  15#define MBS_CHECKSUM_ERROR      0x4010
  16#define MBS_INVALID_PRODUCT_KEY 0x4020
  17
  18/*
  19 * Firmware Options.
  20 */
  21#define FO1_ENABLE_PUREX        BIT_10
  22#define FO1_DISABLE_LED_CTRL    BIT_6
  23#define FO1_ENABLE_8016         BIT_0
  24#define FO2_ENABLE_SEL_CLASS2   BIT_5
  25#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
  26#define FO3_HOLD_STS_IOCB       BIT_12
  27
  28/*
  29 * Port Database structure definition for ISP 24xx.
  30 */
  31#define PDO_FORCE_ADISC         BIT_1
  32#define PDO_FORCE_PLOGI         BIT_0
  33
  34struct buffer_credit_24xx {
  35        u32 parameter[28];
  36};
  37
  38#define PORT_DATABASE_24XX_SIZE         64
  39struct port_database_24xx {
  40        uint16_t flags;
  41#define PDF_TASK_RETRY_ID       BIT_14
  42#define PDF_FC_TAPE             BIT_7
  43#define PDF_ACK0_CAPABLE        BIT_6
  44#define PDF_FCP2_CONF           BIT_5
  45#define PDF_CLASS_2             BIT_4
  46#define PDF_HARD_ADDR           BIT_1
  47
  48        /*
  49         * for NVMe, the login_state field has been
  50         * split into nibbles.
  51         * The lower nibble is for FCP.
  52         * The upper nibble is for NVMe.
  53         */
  54        uint8_t current_login_state;
  55        uint8_t last_login_state;
  56#define PDS_PLOGI_PENDING       0x03
  57#define PDS_PLOGI_COMPLETE      0x04
  58#define PDS_PRLI_PENDING        0x05
  59#define PDS_PRLI_COMPLETE       0x06
  60#define PDS_PORT_UNAVAILABLE    0x07
  61#define PDS_PRLO_PENDING        0x09
  62#define PDS_LOGO_PENDING        0x11
  63#define PDS_PRLI2_PENDING       0x12
  64
  65        uint8_t hard_address[3];
  66        uint8_t reserved_1;
  67
  68        uint8_t port_id[3];
  69        uint8_t sequence_id;
  70
  71        uint16_t port_timer;
  72
  73        uint16_t nport_handle;                  /* N_PORT handle. */
  74
  75        uint16_t receive_data_size;
  76        uint16_t reserved_2;
  77
  78        uint8_t prli_svc_param_word_0[2];       /* Big endian */
  79                                                /* Bits 15-0 of word 0 */
  80        uint8_t prli_svc_param_word_3[2];       /* Big endian */
  81                                                /* Bits 15-0 of word 3 */
  82
  83        uint8_t port_name[WWN_SIZE];
  84        uint8_t node_name[WWN_SIZE];
  85
  86        uint8_t reserved_3[4];
  87        uint16_t prli_nvme_svc_param_word_0;    /* Bits 15-0 of word 0 */
  88        uint16_t prli_nvme_svc_param_word_3;    /* Bits 15-0 of word 3 */
  89        uint16_t nvme_first_burst_size;
  90        uint8_t reserved_4[14];
  91};
  92
  93/*
  94 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
  95 * However, in this case it returns 1st 40 bytes.
  96 */
  97struct get_name_list_extended {
  98        __le16 flags;
  99        u8 current_login_state;
 100        u8 last_login_state;
 101        u8 hard_address[3];
 102        u8 reserved_1;
 103        u8 port_id[3];
 104        u8 sequence_id;
 105        __le16 port_timer;
 106        __le16 nport_handle;                    /* N_PORT handle. */
 107        __le16 receive_data_size;
 108        __le16 reserved_2;
 109
 110        /* PRLI SVC Param are Big endian */
 111        u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
 112        u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
 113        u8 port_name[WWN_SIZE];
 114        u8 node_name[WWN_SIZE];
 115};
 116
 117/* MB 75h: This is the short version of the database */
 118struct get_name_list {
 119        u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
 120        __le16 nport_handle;
 121        u8 reserved;
 122};
 123
 124struct vp_database_24xx {
 125        uint16_t vp_status;
 126        uint8_t  options;
 127        uint8_t  id;
 128        uint8_t  port_name[WWN_SIZE];
 129        uint8_t  node_name[WWN_SIZE];
 130        uint16_t port_id_low;
 131        uint16_t port_id_high;
 132};
 133
 134struct nvram_24xx {
 135        /* NVRAM header. */
 136        uint8_t id[4];
 137        __le16  nvram_version;
 138        uint16_t reserved_0;
 139
 140        /* Firmware Initialization Control Block. */
 141        __le16  version;
 142        uint16_t reserved_1;
 143        __le16  frame_payload_size;
 144        __le16  execution_throttle;
 145        __le16  exchange_count;
 146        __le16  hard_address;
 147
 148        uint8_t port_name[WWN_SIZE];
 149        uint8_t node_name[WWN_SIZE];
 150
 151        __le16  login_retry_count;
 152        __le16  link_down_on_nos;
 153        __le16  interrupt_delay_timer;
 154        __le16  login_timeout;
 155
 156        __le32  firmware_options_1;
 157        __le32  firmware_options_2;
 158        __le32  firmware_options_3;
 159
 160        /* Offset 56. */
 161
 162        /*
 163         * BIT 0     = Control Enable
 164         * BIT 1-15  =
 165         *
 166         * BIT 0-7   = Reserved
 167         * BIT 8-10  = Output Swing 1G
 168         * BIT 11-13 = Output Emphasis 1G
 169         * BIT 14-15 = Reserved
 170         *
 171         * BIT 0-7   = Reserved
 172         * BIT 8-10  = Output Swing 2G
 173         * BIT 11-13 = Output Emphasis 2G
 174         * BIT 14-15 = Reserved
 175         *
 176         * BIT 0-7   = Reserved
 177         * BIT 8-10  = Output Swing 4G
 178         * BIT 11-13 = Output Emphasis 4G
 179         * BIT 14-15 = Reserved
 180         */
 181        __le16  seriallink_options[4];
 182
 183        uint16_t reserved_2[16];
 184
 185        /* Offset 96. */
 186        uint16_t reserved_3[16];
 187
 188        /* PCIe table entries. */
 189        uint16_t reserved_4[16];
 190
 191        /* Offset 160. */
 192        uint16_t reserved_5[16];
 193
 194        /* Offset 192. */
 195        uint16_t reserved_6[16];
 196
 197        /* Offset 224. */
 198        uint16_t reserved_7[16];
 199
 200        /*
 201         * BIT 0  = Enable spinup delay
 202         * BIT 1  = Disable BIOS
 203         * BIT 2  = Enable Memory Map BIOS
 204         * BIT 3  = Enable Selectable Boot
 205         * BIT 4  = Disable RISC code load
 206         * BIT 5  = Disable Serdes
 207         * BIT 6  =
 208         * BIT 7  =
 209         *
 210         * BIT 8  =
 211         * BIT 9  =
 212         * BIT 10 = Enable lip full login
 213         * BIT 11 = Enable target reset
 214         * BIT 12 =
 215         * BIT 13 =
 216         * BIT 14 =
 217         * BIT 15 = Enable alternate WWN
 218         *
 219         * BIT 16-31 =
 220         */
 221        __le32  host_p;
 222
 223        uint8_t alternate_port_name[WWN_SIZE];
 224        uint8_t alternate_node_name[WWN_SIZE];
 225
 226        uint8_t boot_port_name[WWN_SIZE];
 227        __le16  boot_lun_number;
 228        uint16_t reserved_8;
 229
 230        uint8_t alt1_boot_port_name[WWN_SIZE];
 231        __le16  alt1_boot_lun_number;
 232        uint16_t reserved_9;
 233
 234        uint8_t alt2_boot_port_name[WWN_SIZE];
 235        __le16  alt2_boot_lun_number;
 236        uint16_t reserved_10;
 237
 238        uint8_t alt3_boot_port_name[WWN_SIZE];
 239        __le16  alt3_boot_lun_number;
 240        uint16_t reserved_11;
 241
 242        /*
 243         * BIT 0 = Selective Login
 244         * BIT 1 = Alt-Boot Enable
 245         * BIT 2 = Reserved
 246         * BIT 3 = Boot Order List
 247         * BIT 4 = Reserved
 248         * BIT 5 = Selective LUN
 249         * BIT 6 = Reserved
 250         * BIT 7-31 =
 251         */
 252        __le32  efi_parameters;
 253
 254        uint8_t reset_delay;
 255        uint8_t reserved_12;
 256        uint16_t reserved_13;
 257
 258        __le16  boot_id_number;
 259        uint16_t reserved_14;
 260
 261        __le16  max_luns_per_target;
 262        uint16_t reserved_15;
 263
 264        __le16  port_down_retry_count;
 265        __le16  link_down_timeout;
 266
 267        /* FCode parameters. */
 268        __le16  fcode_parameter;
 269
 270        uint16_t reserved_16[3];
 271
 272        /* Offset 352. */
 273        uint8_t prev_drv_ver_major;
 274        uint8_t prev_drv_ver_submajob;
 275        uint8_t prev_drv_ver_minor;
 276        uint8_t prev_drv_ver_subminor;
 277
 278        __le16  prev_bios_ver_major;
 279        __le16  prev_bios_ver_minor;
 280
 281        __le16  prev_efi_ver_major;
 282        __le16  prev_efi_ver_minor;
 283
 284        __le16  prev_fw_ver_major;
 285        uint8_t prev_fw_ver_minor;
 286        uint8_t prev_fw_ver_subminor;
 287
 288        uint16_t reserved_17[8];
 289
 290        /* Offset 384. */
 291        uint16_t reserved_18[16];
 292
 293        /* Offset 416. */
 294        uint16_t reserved_19[16];
 295
 296        /* Offset 448. */
 297        uint16_t reserved_20[16];
 298
 299        /* Offset 480. */
 300        uint8_t model_name[16];
 301
 302        uint16_t reserved_21[2];
 303
 304        /* Offset 500. */
 305        /* HW Parameter Block. */
 306        uint16_t pcie_table_sig;
 307        uint16_t pcie_table_offset;
 308
 309        uint16_t subsystem_vendor_id;
 310        uint16_t subsystem_device_id;
 311
 312        __le32  checksum;
 313};
 314
 315/*
 316 * ISP Initialization Control Block.
 317 * Little endian except where noted.
 318 */
 319#define ICB_VERSION 1
 320struct init_cb_24xx {
 321        __le16  version;
 322        uint16_t reserved_1;
 323
 324        __le16  frame_payload_size;
 325        __le16  execution_throttle;
 326        __le16  exchange_count;
 327
 328        __le16  hard_address;
 329
 330        uint8_t port_name[WWN_SIZE];            /* Big endian. */
 331        uint8_t node_name[WWN_SIZE];            /* Big endian. */
 332
 333        __le16  response_q_inpointer;
 334        __le16  request_q_outpointer;
 335
 336        __le16  login_retry_count;
 337
 338        __le16  prio_request_q_outpointer;
 339
 340        __le16  response_q_length;
 341        __le16  request_q_length;
 342
 343        __le16  link_down_on_nos;               /* Milliseconds. */
 344
 345        __le16  prio_request_q_length;
 346
 347        __le64   request_q_address __packed;
 348        __le64   response_q_address __packed;
 349        __le64   prio_request_q_address __packed;
 350
 351        __le16  msix;
 352        __le16  msix_atio;
 353        uint8_t reserved_2[4];
 354
 355        __le16  atio_q_inpointer;
 356        __le16  atio_q_length;
 357        __le64  atio_q_address __packed;
 358
 359        __le16  interrupt_delay_timer;          /* 100us increments. */
 360        __le16  login_timeout;
 361
 362        /*
 363         * BIT 0  = Enable Hard Loop Id
 364         * BIT 1  = Enable Fairness
 365         * BIT 2  = Enable Full-Duplex
 366         * BIT 3  = Reserved
 367         * BIT 4  = Enable Target Mode
 368         * BIT 5  = Disable Initiator Mode
 369         * BIT 6  = Acquire FA-WWN
 370         * BIT 7  = Enable D-port Diagnostics
 371         *
 372         * BIT 8  = Reserved
 373         * BIT 9  = Non Participating LIP
 374         * BIT 10 = Descending Loop ID Search
 375         * BIT 11 = Acquire Loop ID in LIPA
 376         * BIT 12 = Reserved
 377         * BIT 13 = Full Login after LIP
 378         * BIT 14 = Node Name Option
 379         * BIT 15-31 = Reserved
 380         */
 381        __le32  firmware_options_1;
 382
 383        /*
 384         * BIT 0  = Operation Mode bit 0
 385         * BIT 1  = Operation Mode bit 1
 386         * BIT 2  = Operation Mode bit 2
 387         * BIT 3  = Operation Mode bit 3
 388         * BIT 4  = Connection Options bit 0
 389         * BIT 5  = Connection Options bit 1
 390         * BIT 6  = Connection Options bit 2
 391         * BIT 7  = Enable Non part on LIHA failure
 392         *
 393         * BIT 8  = Enable Class 2
 394         * BIT 9  = Enable ACK0
 395         * BIT 10 = Reserved
 396         * BIT 11 = Enable FC-SP Security
 397         * BIT 12 = FC Tape Enable
 398         * BIT 13 = Reserved
 399         * BIT 14 = Enable Target PRLI Control
 400         * BIT 15-31 = Reserved
 401         */
 402        __le32  firmware_options_2;
 403
 404        /*
 405         * BIT 0  = Reserved
 406         * BIT 1  = Soft ID only
 407         * BIT 2  = Reserved
 408         * BIT 3  = Reserved
 409         * BIT 4  = FCP RSP Payload bit 0
 410         * BIT 5  = FCP RSP Payload bit 1
 411         * BIT 6  = Enable Receive Out-of-Order data frame handling
 412         * BIT 7  = Disable Automatic PLOGI on Local Loop
 413         *
 414         * BIT 8  = Reserved
 415         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
 416         * BIT 10 = Reserved
 417         * BIT 11 = Reserved
 418         * BIT 12 = Reserved
 419         * BIT 13 = Data Rate bit 0
 420         * BIT 14 = Data Rate bit 1
 421         * BIT 15 = Data Rate bit 2
 422         * BIT 16 = Enable 75 ohm Termination Select
 423         * BIT 17-28 = Reserved
 424         * BIT 29 = Enable response queue 0 in index shadowing
 425         * BIT 30 = Enable request queue 0 out index shadowing
 426         * BIT 31 = Reserved
 427         */
 428        __le32  firmware_options_3;
 429        __le16   qos;
 430        __le16   rid;
 431        uint8_t  reserved_3[20];
 432};
 433
 434/*
 435 * ISP queue - command entry structure definition.
 436 */
 437#define COMMAND_BIDIRECTIONAL 0x75
 438struct cmd_bidir {
 439        uint8_t entry_type;             /* Entry type. */
 440        uint8_t entry_count;            /* Entry count. */
 441        uint8_t sys_define;             /* System defined */
 442        uint8_t entry_status;           /* Entry status. */
 443
 444        uint32_t handle;                /* System handle. */
 445
 446        __le16  nport_handle;           /* N_PORT handle. */
 447
 448        __le16  timeout;                /* Command timeout. */
 449
 450        __le16  wr_dseg_count;          /* Write Data segment count. */
 451        __le16  rd_dseg_count;          /* Read Data segment count. */
 452
 453        struct scsi_lun lun;            /* FCP LUN (BE). */
 454
 455        __le16  control_flags;          /* Control flags. */
 456#define BD_WRAP_BACK                    BIT_3
 457#define BD_READ_DATA                    BIT_1
 458#define BD_WRITE_DATA                   BIT_0
 459
 460        __le16  fcp_cmnd_dseg_len;              /* Data segment length. */
 461        __le64   fcp_cmnd_dseg_address __packed;/* Data segment address. */
 462
 463        uint16_t reserved[2];                   /* Reserved */
 464
 465        __le32  rd_byte_count;                  /* Total Byte count Read. */
 466        __le32  wr_byte_count;                  /* Total Byte count write. */
 467
 468        uint8_t port_id[3];                     /* PortID of destination port.*/
 469        uint8_t vp_index;
 470
 471        struct dsd64 fcp_dsd;
 472};
 473
 474#define COMMAND_TYPE_6  0x48            /* Command Type 6 entry */
 475struct cmd_type_6 {
 476        uint8_t entry_type;             /* Entry type. */
 477        uint8_t entry_count;            /* Entry count. */
 478        uint8_t sys_define;             /* System defined. */
 479        uint8_t entry_status;           /* Entry Status. */
 480
 481        uint32_t handle;                /* System handle. */
 482
 483        __le16  nport_handle;           /* N_PORT handle. */
 484        __le16  timeout;                /* Command timeout. */
 485
 486        __le16  dseg_count;             /* Data segment count. */
 487
 488        __le16  fcp_rsp_dsd_len;        /* FCP_RSP DSD length. */
 489
 490        struct scsi_lun lun;            /* FCP LUN (BE). */
 491
 492        __le16  control_flags;          /* Control flags. */
 493#define CF_DIF_SEG_DESCR_ENABLE         BIT_3
 494#define CF_DATA_SEG_DESCR_ENABLE        BIT_2
 495#define CF_READ_DATA                    BIT_1
 496#define CF_WRITE_DATA                   BIT_0
 497
 498        __le16  fcp_cmnd_dseg_len;      /* Data segment length. */
 499                                        /* Data segment address. */
 500        __le64   fcp_cmnd_dseg_address __packed;
 501                                        /* Data segment address. */
 502        __le64   fcp_rsp_dseg_address __packed;
 503
 504        __le32  byte_count;             /* Total byte count. */
 505
 506        uint8_t port_id[3];             /* PortID of destination port. */
 507        uint8_t vp_index;
 508
 509        struct dsd64 fcp_dsd;
 510};
 511
 512#define COMMAND_TYPE_7  0x18            /* Command Type 7 entry */
 513struct cmd_type_7 {
 514        uint8_t entry_type;             /* Entry type. */
 515        uint8_t entry_count;            /* Entry count. */
 516        uint8_t sys_define;             /* System defined. */
 517        uint8_t entry_status;           /* Entry Status. */
 518
 519        uint32_t handle;                /* System handle. */
 520
 521        __le16  nport_handle;           /* N_PORT handle. */
 522        __le16  timeout;                /* Command timeout. */
 523#define FW_MAX_TIMEOUT          0x1999
 524
 525        __le16  dseg_count;             /* Data segment count. */
 526        uint16_t reserved_1;
 527
 528        struct scsi_lun lun;            /* FCP LUN (BE). */
 529
 530        __le16  task_mgmt_flags;        /* Task management flags. */
 531#define TMF_CLEAR_ACA           BIT_14
 532#define TMF_TARGET_RESET        BIT_13
 533#define TMF_LUN_RESET           BIT_12
 534#define TMF_CLEAR_TASK_SET      BIT_10
 535#define TMF_ABORT_TASK_SET      BIT_9
 536#define TMF_DSD_LIST_ENABLE     BIT_2
 537#define TMF_READ_DATA           BIT_1
 538#define TMF_WRITE_DATA          BIT_0
 539
 540        uint8_t task;
 541#define TSK_SIMPLE              0
 542#define TSK_HEAD_OF_QUEUE       1
 543#define TSK_ORDERED             2
 544#define TSK_ACA                 4
 545#define TSK_UNTAGGED            5
 546
 547        uint8_t crn;
 548
 549        uint8_t fcp_cdb[MAX_CMDSZ];     /* SCSI command words. */
 550        __le32  byte_count;             /* Total byte count. */
 551
 552        uint8_t port_id[3];             /* PortID of destination port. */
 553        uint8_t vp_index;
 554
 555        struct dsd64 dsd;
 556};
 557
 558#define COMMAND_TYPE_CRC_2      0x6A    /* Command Type CRC_2 (Type 6)
 559                                         * (T10-DIF) */
 560struct cmd_type_crc_2 {
 561        uint8_t entry_type;             /* Entry type. */
 562        uint8_t entry_count;            /* Entry count. */
 563        uint8_t sys_define;             /* System defined. */
 564        uint8_t entry_status;           /* Entry Status. */
 565
 566        uint32_t handle;                /* System handle. */
 567
 568        __le16  nport_handle;           /* N_PORT handle. */
 569        __le16  timeout;                /* Command timeout. */
 570
 571        __le16  dseg_count;             /* Data segment count. */
 572
 573        __le16  fcp_rsp_dseg_len;       /* FCP_RSP DSD length. */
 574
 575        struct scsi_lun lun;            /* FCP LUN (BE). */
 576
 577        __le16  control_flags;          /* Control flags. */
 578
 579        __le16  fcp_cmnd_dseg_len;      /* Data segment length. */
 580        __le64   fcp_cmnd_dseg_address __packed;
 581                                        /* Data segment address. */
 582        __le64   fcp_rsp_dseg_address __packed;
 583
 584        __le32  byte_count;             /* Total byte count. */
 585
 586        uint8_t port_id[3];             /* PortID of destination port. */
 587        uint8_t vp_index;
 588
 589        __le64   crc_context_address __packed;  /* Data segment address. */
 590        __le16  crc_context_len;                /* Data segment length. */
 591        uint16_t reserved_1;                    /* MUST be set to 0. */
 592};
 593
 594
 595/*
 596 * ISP queue - status entry structure definition.
 597 */
 598#define STATUS_TYPE     0x03            /* Status entry. */
 599struct sts_entry_24xx {
 600        uint8_t entry_type;             /* Entry type. */
 601        uint8_t entry_count;            /* Entry count. */
 602        uint8_t sys_define;             /* System defined. */
 603        uint8_t entry_status;           /* Entry Status. */
 604
 605        uint32_t handle;                /* System handle. */
 606
 607        __le16  comp_status;            /* Completion status. */
 608        __le16  ox_id;                  /* OX_ID used by the firmware. */
 609
 610        __le32  residual_len;           /* FW calc residual transfer length. */
 611
 612        union {
 613                __le16 reserved_1;
 614                __le16  nvme_rsp_pyld_len;
 615        };
 616
 617        __le16  state_flags;            /* State flags. */
 618#define SF_TRANSFERRED_DATA     BIT_11
 619#define SF_NVME_ERSP            BIT_6
 620#define SF_FCP_RSP_DMA          BIT_0
 621
 622        __le16  status_qualifier;
 623        __le16  scsi_status;            /* SCSI status. */
 624#define SS_CONFIRMATION_REQ             BIT_12
 625
 626        __le32  rsp_residual_count;     /* FCP RSP residual count. */
 627
 628        __le32  sense_len;              /* FCP SENSE length. */
 629
 630        union {
 631                struct {
 632                        __le32  rsp_data_len;   /* FCP response data length  */
 633                        uint8_t data[28];       /* FCP rsp/sense information */
 634                };
 635                struct nvme_fc_ersp_iu nvme_ersp;
 636                uint8_t nvme_ersp_data[32];
 637        };
 638
 639        /*
 640         * If DIF Error is set in comp_status, these additional fields are
 641         * defined:
 642         *
 643         * !!! NOTE: Firmware sends expected/actual DIF data in big endian
 644         * format; but all of the "data" field gets swab32-d in the beginning
 645         * of qla2x00_status_entry().
 646         *
 647         * &data[10] : uint8_t report_runt_bg[2];       - computed guard
 648         * &data[12] : uint8_t actual_dif[8];           - DIF Data received
 649         * &data[20] : uint8_t expected_dif[8];         - DIF Data computed
 650        */
 651};
 652
 653
 654/*
 655 * Status entry completion status
 656 */
 657#define CS_DATA_REASSEMBLY_ERROR 0x11   /* Data Reassembly Error.. */
 658#define CS_ABTS_BY_TARGET       0x13    /* Target send ABTS to abort IOCB. */
 659#define CS_FW_RESOURCE          0x2C    /* Firmware Resource Unavailable. */
 660#define CS_TASK_MGMT_OVERRUN    0x30    /* Task management overrun (8+). */
 661#define CS_ABORT_BY_TARGET      0x47    /* Abort By Target. */
 662
 663/*
 664 * ISP queue - marker entry structure definition.
 665 */
 666#define MARKER_TYPE     0x04            /* Marker entry. */
 667struct mrk_entry_24xx {
 668        uint8_t entry_type;             /* Entry type. */
 669        uint8_t entry_count;            /* Entry count. */
 670        uint8_t handle_count;           /* Handle count. */
 671        uint8_t entry_status;           /* Entry Status. */
 672
 673        uint32_t handle;                /* System handle. */
 674
 675        __le16  nport_handle;           /* N_PORT handle. */
 676
 677        uint8_t modifier;               /* Modifier (7-0). */
 678#define MK_SYNC_ID_LUN  0               /* Synchronize ID/LUN */
 679#define MK_SYNC_ID      1               /* Synchronize ID */
 680#define MK_SYNC_ALL     2               /* Synchronize all ID/LUN */
 681        uint8_t reserved_1;
 682
 683        uint8_t reserved_2;
 684        uint8_t vp_index;
 685
 686        uint16_t reserved_3;
 687
 688        uint8_t lun[8];                 /* FCP LUN (BE). */
 689        uint8_t reserved_4[40];
 690};
 691
 692/*
 693 * ISP queue - CT Pass-Through entry structure definition.
 694 */
 695#define CT_IOCB_TYPE            0x29    /* CT Pass-Through IOCB entry */
 696struct ct_entry_24xx {
 697        uint8_t entry_type;             /* Entry type. */
 698        uint8_t entry_count;            /* Entry count. */
 699        uint8_t sys_define;             /* System Defined. */
 700        uint8_t entry_status;           /* Entry Status. */
 701
 702        uint32_t handle;                /* System handle. */
 703
 704        __le16  comp_status;            /* Completion status. */
 705
 706        __le16  nport_handle;           /* N_PORT handle. */
 707
 708        __le16  cmd_dsd_count;
 709
 710        uint8_t vp_index;
 711        uint8_t reserved_1;
 712
 713        __le16  timeout;                /* Command timeout. */
 714        uint16_t reserved_2;
 715
 716        __le16  rsp_dsd_count;
 717
 718        uint8_t reserved_3[10];
 719
 720        __le32  rsp_byte_count;
 721        __le32  cmd_byte_count;
 722
 723        struct dsd64 dsd[2];
 724};
 725
 726#define PURX_ELS_HEADER_SIZE    0x18
 727
 728/*
 729 * ISP queue - PUREX IOCB entry structure definition
 730 */
 731#define PUREX_IOCB_TYPE         0x51    /* CT Pass Through IOCB entry */
 732struct purex_entry_24xx {
 733        uint8_t entry_type;             /* Entry type. */
 734        uint8_t entry_count;            /* Entry count. */
 735        uint8_t sys_define;             /* System defined. */
 736        uint8_t entry_status;           /* Entry Status. */
 737
 738        __le16  reserved1;
 739        uint8_t vp_idx;
 740        uint8_t reserved2;
 741
 742        __le16  status_flags;
 743        __le16  nport_handle;
 744
 745        __le16  frame_size;
 746        __le16  trunc_frame_size;
 747
 748        __le32  rx_xchg_addr;
 749
 750        uint8_t d_id[3];
 751        uint8_t r_ctl;
 752
 753        uint8_t s_id[3];
 754        uint8_t cs_ctl;
 755
 756        uint8_t f_ctl[3];
 757        uint8_t type;
 758
 759        __le16  seq_cnt;
 760        uint8_t df_ctl;
 761        uint8_t seq_id;
 762
 763        __le16  rx_id;
 764        __le16  ox_id;
 765        __le32  param;
 766
 767        uint8_t els_frame_payload[20];
 768};
 769
 770/*
 771 * ISP queue - ELS Pass-Through entry structure definition.
 772 */
 773#define ELS_IOCB_TYPE           0x53    /* ELS Pass-Through IOCB entry */
 774struct els_entry_24xx {
 775        uint8_t entry_type;             /* Entry type. */
 776        uint8_t entry_count;            /* Entry count. */
 777        uint8_t sys_define;             /* System Defined. */
 778        uint8_t entry_status;           /* Entry Status. */
 779
 780        uint32_t handle;                /* System handle. */
 781
 782        __le16  comp_status;            /* response only */
 783        __le16  nport_handle;
 784
 785        __le16  tx_dsd_count;
 786
 787        uint8_t vp_index;
 788        uint8_t sof_type;
 789#define EST_SOFI3               (1 << 4)
 790#define EST_SOFI2               (3 << 4)
 791
 792        __le32  rx_xchg_address;        /* Receive exchange address. */
 793        __le16  rx_dsd_count;
 794
 795        uint8_t opcode;
 796        uint8_t reserved_2;
 797
 798        uint8_t d_id[3];
 799        uint8_t s_id[3];
 800
 801        __le16  control_flags;          /* Control flags. */
 802#define ECF_PAYLOAD_DESCR_MASK  (BIT_15|BIT_14|BIT_13)
 803#define EPD_ELS_COMMAND         (0 << 13)
 804#define EPD_ELS_ACC             (1 << 13)
 805#define EPD_ELS_RJT             (2 << 13)
 806#define EPD_RX_XCHG             (3 << 13)
 807#define ECF_CLR_PASSTHRU_PEND   BIT_12
 808#define ECF_INCL_FRAME_HDR      BIT_11
 809
 810        union {
 811                struct {
 812                        __le32   rx_byte_count;
 813                        __le32   tx_byte_count;
 814
 815                        __le64   tx_address __packed;   /* DSD 0 address. */
 816                        __le32   tx_len;                /* DSD 0 length. */
 817
 818                        __le64   rx_address __packed;   /* DSD 1 address. */
 819                        __le32   rx_len;                /* DSD 1 length. */
 820                };
 821                struct {
 822                        __le32  total_byte_count;
 823                        __le32  error_subcode_1;
 824                        __le32  error_subcode_2;
 825                        __le32  error_subcode_3;
 826                };
 827        };
 828};
 829
 830struct els_sts_entry_24xx {
 831        uint8_t entry_type;             /* Entry type. */
 832        uint8_t entry_count;            /* Entry count. */
 833        uint8_t sys_define;             /* System Defined. */
 834        uint8_t entry_status;           /* Entry Status. */
 835
 836        __le32  handle;         /* System handle. */
 837
 838        __le16  comp_status;
 839
 840        __le16  nport_handle;           /* N_PORT handle. */
 841
 842        __le16  reserved_1;
 843
 844        uint8_t vp_index;
 845        uint8_t sof_type;
 846
 847        __le32  rx_xchg_address;        /* Receive exchange address. */
 848        __le16  reserved_2;
 849
 850        uint8_t opcode;
 851        uint8_t reserved_3;
 852
 853        uint8_t d_id[3];
 854        uint8_t s_id[3];
 855
 856        __le16  control_flags;          /* Control flags. */
 857        __le32  total_byte_count;
 858        __le32  error_subcode_1;
 859        __le32  error_subcode_2;
 860        __le32  error_subcode_3;
 861
 862        __le32  reserved_4[4];
 863};
 864/*
 865 * ISP queue - Mailbox Command entry structure definition.
 866 */
 867#define MBX_IOCB_TYPE   0x39
 868struct mbx_entry_24xx {
 869        uint8_t entry_type;             /* Entry type. */
 870        uint8_t entry_count;            /* Entry count. */
 871        uint8_t handle_count;           /* Handle count. */
 872        uint8_t entry_status;           /* Entry Status. */
 873
 874        uint32_t handle;                /* System handle. */
 875
 876        uint16_t mbx[28];
 877};
 878
 879
 880#define LOGINOUT_PORT_IOCB_TYPE 0x52    /* Login/Logout Port entry. */
 881struct logio_entry_24xx {
 882        uint8_t entry_type;             /* Entry type. */
 883        uint8_t entry_count;            /* Entry count. */
 884        uint8_t sys_define;             /* System defined. */
 885        uint8_t entry_status;           /* Entry Status. */
 886
 887        uint32_t handle;                /* System handle. */
 888
 889        __le16  comp_status;            /* Completion status. */
 890#define CS_LOGIO_ERROR          0x31    /* Login/Logout IOCB error. */
 891
 892        __le16  nport_handle;           /* N_PORT handle. */
 893
 894        __le16  control_flags;          /* Control flags. */
 895                                        /* Modifiers. */
 896#define LCF_INCLUDE_SNS         BIT_10  /* Include SNS (FFFFFC) during LOGO. */
 897#define LCF_FCP2_OVERRIDE       BIT_9   /* Set/Reset word 3 of PRLI. */
 898#define LCF_CLASS_2             BIT_8   /* Enable class 2 during PLOGI. */
 899#define LCF_FREE_NPORT          BIT_7   /* Release NPORT handle after LOGO. */
 900#define LCF_EXPL_LOGO           BIT_6   /* Perform an explicit LOGO. */
 901#define LCF_NVME_PRLI           BIT_6   /* Perform NVME FC4 PRLI */
 902#define LCF_SKIP_PRLI           BIT_5   /* Skip PRLI after PLOGI. */
 903#define LCF_IMPL_LOGO_ALL       BIT_5   /* Implicit LOGO to all ports. */
 904#define LCF_COND_PLOGI          BIT_4   /* PLOGI only if not logged-in. */
 905#define LCF_IMPL_LOGO           BIT_4   /* Perform an implicit LOGO. */
 906#define LCF_IMPL_PRLO           BIT_4   /* Perform an implicit PRLO. */
 907                                        /* Commands. */
 908#define LCF_COMMAND_PLOGI       0x00    /* PLOGI. */
 909#define LCF_COMMAND_PRLI        0x01    /* PRLI. */
 910#define LCF_COMMAND_PDISC       0x02    /* PDISC. */
 911#define LCF_COMMAND_ADISC       0x03    /* ADISC. */
 912#define LCF_COMMAND_LOGO        0x08    /* LOGO. */
 913#define LCF_COMMAND_PRLO        0x09    /* PRLO. */
 914#define LCF_COMMAND_TPRLO       0x0A    /* TPRLO. */
 915
 916        uint8_t vp_index;
 917        uint8_t reserved_1;
 918
 919        uint8_t port_id[3];             /* PortID of destination port. */
 920
 921        uint8_t rsp_size;               /* Response size in 32bit words. */
 922
 923        __le32  io_parameter[11];       /* General I/O parameters. */
 924#define LSC_SCODE_NOLINK        0x01
 925#define LSC_SCODE_NOIOCB        0x02
 926#define LSC_SCODE_NOXCB         0x03
 927#define LSC_SCODE_CMD_FAILED    0x04
 928#define LSC_SCODE_NOFABRIC      0x05
 929#define LSC_SCODE_FW_NOT_READY  0x07
 930#define LSC_SCODE_NOT_LOGGED_IN 0x09
 931#define LSC_SCODE_NOPCB         0x0A
 932
 933#define LSC_SCODE_ELS_REJECT    0x18
 934#define LSC_SCODE_CMD_PARAM_ERR 0x19
 935#define LSC_SCODE_PORTID_USED   0x1A
 936#define LSC_SCODE_NPORT_USED    0x1B
 937#define LSC_SCODE_NONPORT       0x1C
 938#define LSC_SCODE_LOGGED_IN     0x1D
 939#define LSC_SCODE_NOFLOGI_ACC   0x1F
 940};
 941
 942#define TSK_MGMT_IOCB_TYPE      0x14
 943struct tsk_mgmt_entry {
 944        uint8_t entry_type;             /* Entry type. */
 945        uint8_t entry_count;            /* Entry count. */
 946        uint8_t handle_count;           /* Handle count. */
 947        uint8_t entry_status;           /* Entry Status. */
 948
 949        uint32_t handle;                /* System handle. */
 950
 951        __le16  nport_handle;           /* N_PORT handle. */
 952
 953        uint16_t reserved_1;
 954
 955        __le16  delay;                  /* Activity delay in seconds. */
 956
 957        __le16  timeout;                /* Command timeout. */
 958
 959        struct scsi_lun lun;            /* FCP LUN (BE). */
 960
 961        __le32  control_flags;          /* Control Flags. */
 962#define TCF_NOTMCMD_TO_TARGET   BIT_31
 963#define TCF_LUN_RESET           BIT_4
 964#define TCF_ABORT_TASK_SET      BIT_3
 965#define TCF_CLEAR_TASK_SET      BIT_2
 966#define TCF_TARGET_RESET        BIT_1
 967#define TCF_CLEAR_ACA           BIT_0
 968
 969        uint8_t reserved_2[20];
 970
 971        uint8_t port_id[3];             /* PortID of destination port. */
 972        uint8_t vp_index;
 973
 974        uint8_t reserved_3[12];
 975};
 976
 977#define ABORT_IOCB_TYPE 0x33
 978struct abort_entry_24xx {
 979        uint8_t entry_type;             /* Entry type. */
 980        uint8_t entry_count;            /* Entry count. */
 981        uint8_t handle_count;           /* Handle count. */
 982        uint8_t entry_status;           /* Entry Status. */
 983
 984        uint32_t handle;                /* System handle. */
 985
 986        union {
 987                __le16 nport_handle;            /* N_PORT handle. */
 988                __le16 comp_status;             /* Completion status. */
 989        };
 990
 991        __le16  options;                /* Options. */
 992#define AOF_NO_ABTS             BIT_0   /* Do not send any ABTS. */
 993#define AOF_NO_RRQ              BIT_1   /* Do not send RRQ. */
 994#define AOF_ABTS_TIMEOUT        BIT_2   /* Disable logout on ABTS timeout. */
 995#define AOF_ABTS_RTY_CNT        BIT_3   /* Use driver specified retry count. */
 996#define AOF_RSP_TIMEOUT         BIT_4   /* Use specified response timeout. */
 997
 998
 999        uint32_t handle_to_abort;       /* System handle to abort. */
1000

1001        __le16  req_que_no;
1002        uint8_t reserved_1[30];
1003
1004        uint8_t port_id[3];             /* PortID of destination port. */
1005        uint8_t vp_index;
1006        u8      reserved_2[4];
1007        union {
1008                struct {
1009                        __le16 abts_rty_cnt;
1010                        __le16 rsp_timeout;
1011                } drv;
1012                struct {
1013                        u8      ba_rjt_vendorUnique;
1014                        u8      ba_rjt_reasonCodeExpl;
1015                        u8      ba_rjt_reasonCode;
1016                        u8      reserved_3;
1017                } fw;
1018        };
1019        u8      reserved_4[4];
1020};
1021
1022#define ABTS_RCV_TYPE           0x54
1023#define ABTS_RSP_TYPE           0x55
1024struct abts_entry_24xx {
1025        uint8_t entry_type;
1026        uint8_t entry_count;
1027        uint8_t handle_count;
1028        uint8_t entry_status;
1029
1030        __le32  handle;         /* type 0x55 only */
1031
1032        __le16  comp_status;            /* type 0x55 only */
1033        __le16  nport_handle;           /* type 0x54 only */
1034
1035        __le16  control_flags;          /* type 0x55 only */
1036        uint8_t vp_idx;
1037        uint8_t sof_type;               /* sof_type is upper nibble */
1038
1039        __le32  rx_xch_addr;
1040
1041        uint8_t d_id[3];
1042        uint8_t r_ctl;
1043
1044        uint8_t s_id[3];
1045        uint8_t cs_ctl;
1046
1047        uint8_t f_ctl[3];
1048        uint8_t type;
1049
1050        __le16  seq_cnt;
1051        uint8_t df_ctl;
1052        uint8_t seq_id;
1053
1054        __le16  rx_id;
1055        __le16  ox_id;
1056
1057        __le32  param;
1058
1059        union {
1060                struct {
1061                        __le32  subcode3;
1062                        __le32  rsvd;
1063                        __le32  subcode1;
1064                        __le32  subcode2;
1065                } error;
1066                struct {
1067                        __le16  rsrvd1;
1068                        uint8_t last_seq_id;
1069                        uint8_t seq_id_valid;
1070                        __le16  aborted_rx_id;
1071                        __le16  aborted_ox_id;
1072                        __le16  high_seq_cnt;
1073                        __le16  low_seq_cnt;
1074                } ba_acc;
1075                struct {
1076                        uint8_t vendor_unique;
1077                        uint8_t explanation;
1078                        uint8_t reason;
1079                } ba_rjt;
1080        } payload;
1081
1082        __le32  rx_xch_addr_to_abort;
1083} __packed;
1084
1085/* ABTS payload explanation values */
1086#define BA_RJT_EXP_NO_ADDITIONAL        0
1087#define BA_RJT_EXP_INV_OX_RX_ID         3
1088#define BA_RJT_EXP_SEQ_ABORTED          5
1089
1090/* ABTS payload reason values */
1091#define BA_RJT_RSN_INV_CMD_CODE         1
1092#define BA_RJT_RSN_LOGICAL_ERROR        3
1093#define BA_RJT_RSN_LOGICAL_BUSY         5
1094#define BA_RJT_RSN_PROTOCOL_ERROR       7
1095#define BA_RJT_RSN_UNABLE_TO_PERFORM    9
1096#define BA_RJT_RSN_VENDOR_SPECIFIC      0xff
1097
1098/* FC_F values */
1099#define FC_TYPE_BLD             0x000           /* Basic link data */
1100#define FC_F_CTL_RSP_CNTXT      0x800000        /* Responder of exchange */
1101#define FC_F_CTL_LAST_SEQ       0x100000        /* Last sequence */
1102#define FC_F_CTL_END_SEQ        0x80000         /* Last sequence */
1103#define FC_F_CTL_SEQ_INIT       0x010000        /* Sequence initiative */
1104#define FC_ROUTING_BLD          0x80            /* Basic link data frame */
1105#define FC_R_CTL_BLD_BA_ACC     0x04            /* BA_ACC (basic accept) */
1106
1107/*
1108 * ISP I/O Register Set structure definitions.
1109 */
1110struct device_reg_24xx {
1111        __le32  flash_addr;             /* Flash/NVRAM BIOS address. */
1112#define FARX_DATA_FLAG  BIT_31
1113#define FARX_ACCESS_FLASH_CONF  0x7FFD0000
1114#define FARX_ACCESS_FLASH_DATA  0x7FF00000
1115#define FARX_ACCESS_NVRAM_CONF  0x7FFF0000
1116#define FARX_ACCESS_NVRAM_DATA  0x7FFE0000
1117
1118#define FA_NVRAM_FUNC0_ADDR     0x80
1119#define FA_NVRAM_FUNC1_ADDR     0x180
1120
1121#define FA_NVRAM_VPD_SIZE       0x200
1122#define FA_NVRAM_VPD0_ADDR      0x00
1123#define FA_NVRAM_VPD1_ADDR      0x100
1124
1125#define FA_BOOT_CODE_ADDR       0x00000
1126                                        /*
1127                                         * RISC code begins at offset 512KB
1128                                         * within flash. Consisting of two
1129                                         * contiguous RISC code segments.
1130                                         */
1131#define FA_RISC_CODE_ADDR       0x20000
1132#define FA_RISC_CODE_SEGMENTS   2
1133
1134#define FA_FLASH_DESCR_ADDR_24  0x11000
1135#define FA_FLASH_LAYOUT_ADDR_24 0x11400
1136#define FA_NPIV_CONF0_ADDR_24   0x16000
1137#define FA_NPIV_CONF1_ADDR_24   0x17000
1138
1139#define FA_FW_AREA_ADDR         0x40000
1140#define FA_VPD_NVRAM_ADDR       0x48000
1141#define FA_FEATURE_ADDR         0x4C000
1142#define FA_FLASH_DESCR_ADDR     0x50000
1143#define FA_FLASH_LAYOUT_ADDR    0x50400
1144#define FA_HW_EVENT0_ADDR       0x54000
1145#define FA_HW_EVENT1_ADDR       0x54400
1146#define FA_HW_EVENT_SIZE        0x200
1147#define FA_HW_EVENT_ENTRY_SIZE  4
1148#define FA_NPIV_CONF0_ADDR      0x5C000
1149#define FA_NPIV_CONF1_ADDR      0x5D000
1150#define FA_FCP_PRIO0_ADDR       0x10000
1151#define FA_FCP_PRIO1_ADDR       0x12000
1152
1153/*
1154 * Flash Error Log Event Codes.
1155 */
1156#define HW_EVENT_RESET_ERR      0xF00B
1157#define HW_EVENT_ISP_ERR        0xF020
1158#define HW_EVENT_PARITY_ERR     0xF022
1159#define HW_EVENT_NVRAM_CHKSUM_ERR       0xF023
1160#define HW_EVENT_FLASH_FW_ERR   0xF024
1161
1162        __le32  flash_data;             /* Flash/NVRAM BIOS data. */
1163
1164        __le32  ctrl_status;            /* Control/Status. */
1165#define CSRX_FLASH_ACCESS_ERROR BIT_18  /* Flash/NVRAM Access Error. */
1166#define CSRX_DMA_ACTIVE         BIT_17  /* DMA Active status. */
1167#define CSRX_DMA_SHUTDOWN       BIT_16  /* DMA Shutdown control status. */
1168#define CSRX_FUNCTION           BIT_15  /* Function number. */
1169                                        /* PCI-X Bus Mode. */
1170#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1171#define PBM_PCI_33MHZ           (0 << 8)
1172#define PBM_PCIX_M1_66MHZ       (1 << 8)
1173#define PBM_PCIX_M1_100MHZ      (2 << 8)
1174#define PBM_PCIX_M1_133MHZ      (3 << 8)
1175#define PBM_PCIX_M2_66MHZ       (5 << 8)
1176#define PBM_PCIX_M2_100MHZ      (6 << 8)
1177#define PBM_PCIX_M2_133MHZ      (7 << 8)
1178#define PBM_PCI_66MHZ           (8 << 8)
1179                                        /* Max Write Burst byte count. */
1180#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1181#define MWB_512_BYTES           (0 << 4)
1182#define MWB_1024_BYTES          (1 << 4)
1183#define MWB_2048_BYTES          (2 << 4)
1184#define MWB_4096_BYTES          (3 << 4)
1185
1186#define CSRX_64BIT_SLOT         BIT_2   /* PCI 64-Bit Bus Slot. */
1187#define CSRX_FLASH_ENABLE       BIT_1   /* Flash BIOS Read/Write enable. */
1188#define CSRX_ISP_SOFT_RESET     BIT_0   /* ISP soft reset. */
1189
1190        __le32  ictrl;                  /* Interrupt control. */
1191#define ICRX_EN_RISC_INT        BIT_3   /* Enable RISC interrupts on PCI. */
1192
1193        __le32  istatus;                /* Interrupt status. */
1194#define ISRX_RISC_INT           BIT_3   /* RISC interrupt. */
1195
1196        __le32  unused_1[2];            /* Gap. */
1197
1198                                        /* Request Queue. */
1199        __le32  req_q_in;               /*  In-Pointer. */
1200        __le32  req_q_out;              /*  Out-Pointer. */
1201                                        /* Response Queue. */
1202        __le32  rsp_q_in;               /*  In-Pointer. */
1203        __le32  rsp_q_out;              /*  Out-Pointer. */
1204                                        /* Priority Request Queue. */
1205        __le32  preq_q_in;              /*  In-Pointer. */
1206        __le32  preq_q_out;             /*  Out-Pointer. */
1207
1208        __le32  unused_2[2];            /* Gap. */
1209
1210                                        /* ATIO Queue. */
1211        __le32  atio_q_in;              /*  In-Pointer. */
1212        __le32  atio_q_out;             /*  Out-Pointer. */
1213
1214        __le32  host_status;
1215#define HSRX_RISC_INT           BIT_15  /* RISC to Host interrupt. */
1216#define HSRX_RISC_PAUSED        BIT_8   /* RISC Paused. */
1217
1218        __le32  hccr;                   /* Host command & control register. */
1219                                        /* HCCR statuses. */
1220#define HCCRX_HOST_INT          BIT_6   /* Host to RISC interrupt bit. */
1221#define HCCRX_RISC_RESET        BIT_5   /* RISC Reset mode bit. */
1222                                        /* HCCR commands. */
1223                                        /* NOOP. */
1224#define HCCRX_NOOP              0x00000000
1225                                        /* Set RISC Reset. */
1226#define HCCRX_SET_RISC_RESET    0x10000000
1227                                        /* Clear RISC Reset. */
1228#define HCCRX_CLR_RISC_RESET    0x20000000
1229                                        /* Set RISC Pause. */
1230#define HCCRX_SET_RISC_PAUSE    0x30000000
1231                                        /* Releases RISC Pause. */
1232#define HCCRX_REL_RISC_PAUSE    0x40000000
1233                                        /* Set HOST to RISC interrupt. */
1234#define HCCRX_SET_HOST_INT      0x50000000
1235                                        /* Clear HOST to RISC interrupt. */
1236#define HCCRX_CLR_HOST_INT      0x60000000
1237                                        /* Clear RISC to PCI interrupt. */
1238#define HCCRX_CLR_RISC_INT      0xA0000000
1239
1240        __le32  gpiod;                  /* GPIO Data register. */
1241
1242                                        /* LED update mask. */
1243#define GPDX_LED_UPDATE_MASK    (BIT_20|BIT_19|BIT_18)
1244                                        /* Data update mask. */
1245#define GPDX_DATA_UPDATE_MASK   (BIT_17|BIT_16)
1246                                        /* Data update mask. */
1247#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1248                                        /* LED control mask. */
1249#define GPDX_LED_COLOR_MASK     (BIT_4|BIT_3|BIT_2)
1250                                        /* LED bit values. Color names as
1251                                         * referenced in fw spec.
1252                                         */
1253#define GPDX_LED_YELLOW_ON      BIT_2
1254#define GPDX_LED_GREEN_ON       BIT_3
1255#define GPDX_LED_AMBER_ON       BIT_4
1256                                        /* Data in/out. */
1257#define GPDX_DATA_INOUT         (BIT_1|BIT_0)
1258
1259        __le32  gpioe;                  /* GPIO Enable register. */
1260                                        /* Enable update mask. */
1261#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1262                                        /* Enable update mask. */
1263#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1264                                        /* Enable. */
1265#define GPEX_ENABLE             (BIT_1|BIT_0)
1266
1267        __le32  iobase_addr;            /* I/O Bus Base Address register. */
1268
1269        __le32  unused_3[10];           /* Gap. */
1270
1271        __le16  mailbox0;
1272        __le16  mailbox1;
1273        __le16  mailbox2;
1274        __le16  mailbox3;
1275        __le16  mailbox4;
1276        __le16  mailbox5;
1277        __le16  mailbox6;
1278        __le16  mailbox7;
1279        __le16  mailbox8;
1280        __le16  mailbox9;
1281        __le16  mailbox10;
1282        __le16  mailbox11;
1283        __le16  mailbox12;
1284        __le16  mailbox13;
1285        __le16  mailbox14;
1286        __le16  mailbox15;
1287        __le16  mailbox16;
1288        __le16  mailbox17;
1289        __le16  mailbox18;
1290        __le16  mailbox19;
1291        __le16  mailbox20;
1292        __le16  mailbox21;
1293        __le16  mailbox22;
1294        __le16  mailbox23;
1295        __le16  mailbox24;
1296        __le16  mailbox25;
1297        __le16  mailbox26;
1298        __le16  mailbox27;
1299        __le16  mailbox28;
1300        __le16  mailbox29;
1301        __le16  mailbox30;
1302        __le16  mailbox31;
1303
1304        __le32  iobase_window;
1305        __le32  iobase_c4;
1306        __le32  iobase_c8;
1307        __le32  unused_4_1[6];          /* Gap. */
1308        __le32  iobase_q;
1309        __le32  unused_5[2];            /* Gap. */
1310        __le32  iobase_select;
1311        __le32  unused_6[2];            /* Gap. */
1312        __le32  iobase_sdata;
1313};
1314/* RISC-RISC semaphore register PCI offet */
1315#define RISC_REGISTER_BASE_OFFSET       0x7010
1316#define RISC_REGISTER_WINDOW_OFFSET     0x6
1317
1318/* RISC-RISC semaphore/flag register (risc address 0x7016) */
1319
1320#define RISC_SEMAPHORE          0x1UL
1321#define RISC_SEMAPHORE_WE       (RISC_SEMAPHORE << 16)
1322#define RISC_SEMAPHORE_CLR      (RISC_SEMAPHORE_WE | 0x0UL)
1323#define RISC_SEMAPHORE_SET      (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1324
1325#define RISC_SEMAPHORE_FORCE            0x8000UL
1326#define RISC_SEMAPHORE_FORCE_WE         (RISC_SEMAPHORE_FORCE << 16)
1327#define RISC_SEMAPHORE_FORCE_CLR        (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1328#define RISC_SEMAPHORE_FORCE_SET        \
1329                (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1330
1331/* RISC semaphore timeouts (ms) */
1332#define TIMEOUT_SEMAPHORE               2500
1333#define TIMEOUT_SEMAPHORE_FORCE         2000
1334#define TIMEOUT_TOTAL_ELAPSED           4500
1335
1336/* Trace Control *************************************************************/
1337
1338#define TC_AEN_DISABLE          0
1339
1340#define TC_EFT_ENABLE           4
1341#define TC_EFT_DISABLE          5
1342
1343#define TC_FCE_ENABLE           8
1344#define TC_FCE_OPTIONS          0
1345#define TC_FCE_DEFAULT_RX_SIZE  2112
1346#define TC_FCE_DEFAULT_TX_SIZE  2112
1347#define TC_FCE_DISABLE          9
1348#define TC_FCE_DISABLE_TRACE    BIT_0
1349
1350/* MID Support ***************************************************************/
1351
1352#define MIN_MULTI_ID_FABRIC     64      /* Must be power-of-2. */
1353#define MAX_MULTI_ID_FABRIC     256     /* ... */
1354
1355struct mid_conf_entry_24xx {
1356        uint16_t reserved_1;
1357
1358        /*
1359         * BIT 0  = Enable Hard Loop Id
1360         * BIT 1  = Acquire Loop ID in LIPA
1361         * BIT 2  = ID not Acquired
1362         * BIT 3  = Enable VP
1363         * BIT 4  = Enable Initiator Mode
1364         * BIT 5  = Disable Target Mode
1365         * BIT 6-7 = Reserved
1366         */
1367        uint8_t options;
1368
1369        uint8_t hard_address;
1370
1371        uint8_t port_name[WWN_SIZE];
1372        uint8_t node_name[WWN_SIZE];
1373};
1374
1375struct mid_init_cb_24xx {
1376        struct init_cb_24xx init_cb;
1377
1378        __le16  count;
1379        __le16  options;
1380
1381        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1382};
1383
1384
1385struct mid_db_entry_24xx {
1386        uint16_t status;
1387#define MDBS_NON_PARTIC         BIT_3
1388#define MDBS_ID_ACQUIRED        BIT_1
1389#define MDBS_ENABLED            BIT_0
1390
1391        uint8_t options;
1392        uint8_t hard_address;
1393
1394        uint8_t port_name[WWN_SIZE];
1395        uint8_t node_name[WWN_SIZE];
1396
1397        uint8_t port_id[3];
1398        uint8_t reserved_1;
1399};
1400
1401/*
1402 * Virtual Port Control IOCB
1403 */
1404#define VP_CTRL_IOCB_TYPE       0x30    /* Virtual Port Control entry. */
1405struct vp_ctrl_entry_24xx {
1406        uint8_t entry_type;             /* Entry type. */
1407        uint8_t entry_count;            /* Entry count. */
1408        uint8_t sys_define;             /* System defined. */
1409        uint8_t entry_status;           /* Entry Status. */
1410
1411        uint32_t handle;                /* System handle. */
1412
1413        __le16  vp_idx_failed;
1414
1415        __le16  comp_status;            /* Completion status. */
1416#define CS_VCE_IOCB_ERROR       0x01    /* Error processing IOCB */
1417#define CS_VCE_ACQ_ID_ERROR     0x02    /* Error while acquireing ID. */
1418#define CS_VCE_BUSY             0x05    /* Firmware not ready to accept cmd. */
1419
1420        __le16  command;
1421#define VCE_COMMAND_ENABLE_VPS  0x00    /* Enable VPs. */
1422#define VCE_COMMAND_DISABLE_VPS 0x08    /* Disable VPs. */
1423#define VCE_COMMAND_DISABLE_VPS_REINIT  0x09 /* Disable VPs and reinit link. */
1424#define VCE_COMMAND_DISABLE_VPS_LOGO    0x0a /* Disable VPs and LOGO ports. */
1425#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL        0x0b /* Disable VPs and LOGO ports. */
1426
1427        __le16  vp_count;
1428
1429        uint8_t vp_idx_map[16];
1430        __le16  flags;
1431        __le16  id;
1432        uint16_t reserved_4;
1433        __le16  hopct;
1434        uint8_t reserved_5[24];
1435};
1436
1437/*
1438 * Modify Virtual Port Configuration IOCB
1439 */
1440#define VP_CONFIG_IOCB_TYPE     0x31    /* Virtual Port Config entry. */
1441struct vp_config_entry_24xx {
1442        uint8_t entry_type;             /* Entry type. */
1443        uint8_t entry_count;            /* Entry count. */
1444        uint8_t handle_count;
1445        uint8_t entry_status;           /* Entry Status. */
1446
1447        uint32_t handle;                /* System handle. */
1448
1449        __le16  flags;
1450#define CS_VF_BIND_VPORTS_TO_VF         BIT_0
1451#define CS_VF_SET_QOS_OF_VPORTS         BIT_1
1452#define CS_VF_SET_HOPS_OF_VPORTS        BIT_2
1453
1454        __le16  comp_status;            /* Completion status. */
1455#define CS_VCT_STS_ERROR        0x01    /* Specified VPs were not disabled. */
1456#define CS_VCT_CNT_ERROR        0x02    /* Invalid VP count. */
1457#define CS_VCT_ERROR            0x03    /* Unknown error. */
1458#define CS_VCT_IDX_ERROR        0x02    /* Invalid VP index. */
1459#define CS_VCT_BUSY             0x05    /* Firmware not ready to accept cmd. */
1460
1461        uint8_t command;
1462#define VCT_COMMAND_MOD_VPS     0x00    /* Modify VP configurations. */
1463#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1464
1465        uint8_t vp_count;
1466
1467        uint8_t vp_index1;
1468        uint8_t vp_index2;
1469
1470        uint8_t options_idx1;
1471        uint8_t hard_address_idx1;
1472        uint16_t reserved_vp1;
1473        uint8_t port_name_idx1[WWN_SIZE];
1474        uint8_t node_name_idx1[WWN_SIZE];
1475
1476        uint8_t options_idx2;
1477        uint8_t hard_address_idx2;
1478        uint16_t reserved_vp2;
1479        uint8_t port_name_idx2[WWN_SIZE];
1480        uint8_t node_name_idx2[WWN_SIZE];
1481        __le16  id;
1482        uint16_t reserved_4;
1483        __le16  hopct;
1484        uint8_t reserved_5[2];
1485};
1486
1487#define VP_RPT_ID_IOCB_TYPE     0x32    /* Report ID Acquisition entry. */
1488enum VP_STATUS {
1489        VP_STAT_COMPL,
1490        VP_STAT_FAIL,
1491        VP_STAT_ID_CHG,
1492        VP_STAT_SNS_TO,                         /* timeout */
1493        VP_STAT_SNS_RJT,
1494        VP_STAT_SCR_TO,                         /* timeout */
1495        VP_STAT_SCR_RJT,
1496};
1497
1498enum VP_FLAGS {
1499        VP_FLAGS_CON_FLOOP = 1,
1500        VP_FLAGS_CON_P2P = 2,
1501        VP_FLAGS_CON_FABRIC = 3,
1502        VP_FLAGS_NAME_VALID = BIT_5,
1503};
1504
1505struct vp_rpt_id_entry_24xx {
1506        uint8_t entry_type;             /* Entry type. */
1507        uint8_t entry_count;            /* Entry count. */
1508        uint8_t sys_define;             /* System defined. */
1509        uint8_t entry_status;           /* Entry Status. */
1510        __le32 resv1;
1511        uint8_t vp_acquired;
1512        uint8_t vp_setup;
1513        uint8_t vp_idx;         /* Format 0=reserved */
1514        uint8_t vp_status;      /* Format 0=reserved */
1515
1516        uint8_t port_id[3];
1517        uint8_t format;
1518        union {
1519                struct _f0 {
1520                        /* format 0 loop */
1521                        uint8_t vp_idx_map[16];
1522                        uint8_t reserved_4[32];
1523                } f0;
1524                struct _f1 {
1525                        /* format 1 fabric */
1526                        uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1527                        uint8_t flags;
1528#define TOPO_MASK  0xE
1529#define TOPO_FL    0x2
1530#define TOPO_N2N   0x4
1531#define TOPO_F     0x6
1532
1533                        uint16_t fip_flags;
1534                        uint8_t rsv2[12];
1535
1536                        uint8_t ls_rjt_vendor;
1537                        uint8_t ls_rjt_explanation;
1538                        uint8_t ls_rjt_reason;
1539                        uint8_t rsv3[5];
1540
1541                        uint8_t port_name[8];
1542                        uint8_t node_name[8];
1543                        uint16_t bbcr;
1544                        uint8_t reserved_5[6];
1545                } f1;
1546                struct _f2 { /* format 2: N2N direct connect */
1547                        uint8_t vpstat1_subcode;
1548                        uint8_t flags;
1549                        uint16_t fip_flags;
1550                        uint8_t rsv2[12];
1551
1552                        uint8_t ls_rjt_vendor;
1553                        uint8_t ls_rjt_explanation;
1554                        uint8_t ls_rjt_reason;
1555                        uint8_t rsv3[5];
1556
1557                        uint8_t port_name[8];
1558                        uint8_t node_name[8];
1559                        uint16_t bbcr;
1560                        uint8_t reserved_5[2];
1561                        uint8_t remote_nport_id[4];
1562                } f2;
1563        } u;
1564};
1565
1566#define VF_EVFP_IOCB_TYPE       0x26    /* Exchange Virtual Fabric Parameters entry. */
1567struct vf_evfp_entry_24xx {
1568        uint8_t entry_type;             /* Entry type. */
1569        uint8_t entry_count;            /* Entry count. */
1570        uint8_t sys_define;             /* System defined. */
1571        uint8_t entry_status;           /* Entry Status. */
1572
1573        uint32_t handle;                /* System handle. */
1574        __le16  comp_status;           /* Completion status. */
1575        __le16  timeout;               /* timeout */
1576        __le16  adim_tagging_mode;
1577
1578        __le16  vfport_id;
1579        uint32_t exch_addr;
1580
1581        __le16  nport_handle;          /* N_PORT handle. */
1582        __le16  control_flags;
1583        uint32_t io_parameter_0;
1584        uint32_t io_parameter_1;
1585        __le64   tx_address __packed;   /* Data segment 0 address. */
1586        uint32_t tx_len;                /* Data segment 0 length. */
1587        __le64   rx_address __packed;   /* Data segment 1 address. */
1588        uint32_t rx_len;                /* Data segment 1 length. */
1589};
1590
1591/* END MID Support ***********************************************************/
1592
1593/* Flash Description Table ***************************************************/
1594
1595struct qla_fdt_layout {
1596        uint8_t sig[4];
1597        __le16  version;
1598        __le16  len;
1599        __le16  checksum;
1600        uint8_t unused1[2];
1601        uint8_t model[16];
1602        __le16  man_id;
1603        __le16  id;
1604        uint8_t flags;
1605        uint8_t erase_cmd;
1606        uint8_t alt_erase_cmd;
1607        uint8_t wrt_enable_cmd;
1608        uint8_t wrt_enable_bits;
1609        uint8_t wrt_sts_reg_cmd;
1610        uint8_t unprotect_sec_cmd;
1611        uint8_t read_man_id_cmd;
1612        __le32 block_size;
1613        __le32 alt_block_size;
1614        __le32 flash_size;
1615        __le32 wrt_enable_data;
1616        uint8_t read_id_addr_len;
1617        uint8_t wrt_disable_bits;
1618        uint8_t read_dev_id_len;
1619        uint8_t chip_erase_cmd;
1620        __le16  read_timeout;
1621        uint8_t protect_sec_cmd;
1622        uint8_t unused2[65];
1623};
1624
1625/* Flash Layout Table ********************************************************/
1626
1627struct qla_flt_location {
1628        uint8_t sig[4];
1629        __le16  start_lo;
1630        __le16  start_hi;
1631        uint8_t version;
1632        uint8_t unused[5];
1633        __le16  checksum;
1634};
1635
1636#define FLT_REG_FW              0x01
1637#define FLT_REG_BOOT_CODE       0x07
1638#define FLT_REG_VPD_0           0x14
1639#define FLT_REG_NVRAM_0         0x15
1640#define FLT_REG_VPD_1           0x16
1641#define FLT_REG_NVRAM_1         0x17
1642#define FLT_REG_VPD_2           0xD4
1643#define FLT_REG_NVRAM_2         0xD5
1644#define FLT_REG_VPD_3           0xD6
1645#define FLT_REG_NVRAM_3         0xD7
1646#define FLT_REG_FDT             0x1a
1647#define FLT_REG_FLT             0x1c
1648#define FLT_REG_HW_EVENT_0      0x1d
1649#define FLT_REG_HW_EVENT_1      0x1f
1650#define FLT_REG_NPIV_CONF_0     0x29
1651#define FLT_REG_NPIV_CONF_1     0x2a
1652#define FLT_REG_GOLD_FW         0x2f
1653#define FLT_REG_FCP_PRIO_0      0x87
1654#define FLT_REG_FCP_PRIO_1      0x88
1655#define FLT_REG_CNA_FW          0x97
1656#define FLT_REG_BOOT_CODE_8044  0xA2
1657#define FLT_REG_FCOE_FW         0xA4
1658#define FLT_REG_FCOE_NVRAM_0    0xAA
1659#define FLT_REG_FCOE_NVRAM_1    0xAC
1660
1661/* 27xx */
1662#define FLT_REG_IMG_PRI_27XX    0x95
1663#define FLT_REG_IMG_SEC_27XX    0x96
1664#define FLT_REG_FW_SEC_27XX     0x02
1665#define FLT_REG_BOOTLOAD_SEC_27XX       0x9
1666#define FLT_REG_VPD_SEC_27XX_0  0x50
1667#define FLT_REG_VPD_SEC_27XX_1  0x52
1668#define FLT_REG_VPD_SEC_27XX_2  0xD8
1669#define FLT_REG_VPD_SEC_27XX_3  0xDA
1670
1671/* 28xx */
1672#define FLT_REG_AUX_IMG_PRI_28XX        0x125
1673#define FLT_REG_AUX_IMG_SEC_28XX        0x126
1674#define FLT_REG_VPD_SEC_28XX_0          0x10C
1675#define FLT_REG_VPD_SEC_28XX_1          0x10E
1676#define FLT_REG_VPD_SEC_28XX_2          0x110
1677#define FLT_REG_VPD_SEC_28XX_3          0x112
1678#define FLT_REG_NVRAM_SEC_28XX_0        0x10D
1679#define FLT_REG_NVRAM_SEC_28XX_1        0x10F
1680#define FLT_REG_NVRAM_SEC_28XX_2        0x111
1681#define FLT_REG_NVRAM_SEC_28XX_3        0x113
1682#define FLT_REG_MPI_PRI_28XX            0xD3
1683#define FLT_REG_MPI_SEC_28XX            0xF0
1684#define FLT_REG_PEP_PRI_28XX            0xD1
1685#define FLT_REG_PEP_SEC_28XX            0xF1
1686
1687struct qla_flt_region {
1688        __le16  code;
1689        uint8_t attribute;
1690        uint8_t reserved;
1691        __le32 size;
1692        __le32 start;
1693        __le32 end;
1694};
1695
1696struct qla_flt_header {
1697        __le16  version;
1698        __le16  length;
1699        __le16  checksum;
1700        __le16  unused;
1701        struct qla_flt_region region[0];
1702};
1703
1704#define FLT_REGION_SIZE         16
1705#define FLT_MAX_REGIONS         0xFF
1706#define FLT_REGIONS_SIZE        (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1707
1708/* Flash NPIV Configuration Table ********************************************/
1709
1710struct qla_npiv_header {
1711        uint8_t sig[2];
1712        __le16  version;
1713        __le16  entries;
1714        __le16  unused[4];
1715        __le16  checksum;
1716};
1717
1718struct qla_npiv_entry {
1719        __le16  flags;
1720        __le16  vf_id;
1721        uint8_t q_qos;
1722        uint8_t f_qos;
1723        __le16  unused1;
1724        uint8_t port_name[WWN_SIZE];
1725        uint8_t node_name[WWN_SIZE];
1726};
1727
1728/* 84XX Support **************************************************************/
1729
1730#define MBA_ISP84XX_ALERT       0x800f  /* Alert Notification. */
1731#define A84_PANIC_RECOVERY      0x1
1732#define A84_OP_LOGIN_COMPLETE   0x2
1733#define A84_DIAG_LOGIN_COMPLETE 0x3
1734#define A84_GOLD_LOGIN_COMPLETE 0x4
1735
1736#define MBC_ISP84XX_RESET       0x3a    /* Reset. */
1737
1738#define FSTATE_REMOTE_FC_DOWN   BIT_0
1739#define FSTATE_NSL_LINK_DOWN    BIT_1
1740#define FSTATE_IS_DIAG_FW       BIT_2
1741#define FSTATE_LOGGED_IN        BIT_3
1742#define FSTATE_WAITING_FOR_VERIFY       BIT_4
1743
1744#define VERIFY_CHIP_IOCB_TYPE   0x1B
1745struct verify_chip_entry_84xx {
1746        uint8_t entry_type;
1747        uint8_t entry_count;
1748        uint8_t sys_defined;
1749        uint8_t entry_status;
1750
1751        uint32_t handle;
1752
1753        __le16  options;
1754#define VCO_DONT_UPDATE_FW      BIT_0
1755#define VCO_FORCE_UPDATE        BIT_1
1756#define VCO_DONT_RESET_UPDATE   BIT_2
1757#define VCO_DIAG_FW             BIT_3
1758#define VCO_END_OF_DATA         BIT_14
1759#define VCO_ENABLE_DSD          BIT_15
1760
1761        __le16  reserved_1;
1762
1763        __le16  data_seg_cnt;
1764        __le16  reserved_2[3];
1765
1766        __le32  fw_ver;
1767        __le32  exchange_address;
1768
1769        __le32 reserved_3[3];
1770        __le32  fw_size;
1771        __le32  fw_seq_size;
1772        __le32  relative_offset;
1773
1774        struct dsd64 dsd;
1775};
1776
1777struct verify_chip_rsp_84xx {
1778        uint8_t entry_type;
1779        uint8_t entry_count;
1780        uint8_t sys_defined;
1781        uint8_t entry_status;
1782
1783        uint32_t handle;
1784
1785        __le16  comp_status;
1786#define CS_VCS_CHIP_FAILURE     0x3
1787#define CS_VCS_BAD_EXCHANGE     0x8
1788#define CS_VCS_SEQ_COMPLETEi    0x40
1789
1790        __le16  failure_code;
1791#define VFC_CHECKSUM_ERROR      0x1
1792#define VFC_INVALID_LEN         0x2
1793#define VFC_ALREADY_IN_PROGRESS 0x8
1794
1795        __le16  reserved_1[4];
1796
1797        __le32  fw_ver;
1798        __le32  exchange_address;
1799
1800        __le32 reserved_2[6];
1801};
1802
1803#define ACCESS_CHIP_IOCB_TYPE   0x2B
1804struct access_chip_84xx {
1805        uint8_t entry_type;
1806        uint8_t entry_count;
1807        uint8_t sys_defined;
1808        uint8_t entry_status;
1809
1810        uint32_t handle;
1811
1812        __le16  options;
1813#define ACO_DUMP_MEMORY         0x0
1814#define ACO_LOAD_MEMORY         0x1
1815#define ACO_CHANGE_CONFIG_PARAM 0x2
1816#define ACO_REQUEST_INFO        0x3
1817
1818        __le16  reserved1;
1819
1820        __le16  dseg_count;
1821        __le16  reserved2[3];
1822
1823        __le32  parameter1;
1824        __le32  parameter2;
1825        __le32  parameter3;
1826
1827        __le32  reserved3[3];
1828        __le32  total_byte_cnt;
1829        __le32  reserved4;
1830
1831        struct dsd64 dsd;
1832};
1833
1834struct access_chip_rsp_84xx {
1835        uint8_t entry_type;
1836        uint8_t entry_count;
1837        uint8_t sys_defined;
1838        uint8_t entry_status;
1839
1840        uint32_t handle;
1841
1842        __le16  comp_status;
1843        __le16  failure_code;
1844        __le32  residual_count;
1845
1846        __le32  reserved[12];
1847};
1848
1849/* 81XX Support **************************************************************/
1850
1851#define MBA_DCBX_START          0x8016
1852#define MBA_DCBX_COMPLETE       0x8030
1853#define MBA_FCF_CONF_ERR        0x8031
1854#define MBA_DCBX_PARAM_UPDATE   0x8032
1855#define MBA_IDC_COMPLETE        0x8100
1856#define MBA_IDC_NOTIFY          0x8101
1857#define MBA_IDC_TIME_EXT        0x8102
1858
1859#define MBC_IDC_ACK             0x101
1860#define MBC_RESTART_MPI_FW      0x3d
1861#define MBC_FLASH_ACCESS_CTRL   0x3e    /* Control flash access. */
1862#define MBC_GET_XGMAC_STATS     0x7a
1863#define MBC_GET_DCBX_PARAMS     0x51
1864
1865/*
1866 * ISP83xx mailbox commands
1867 */
1868#define MBC_WRITE_REMOTE_REG            0x0001 /* Write remote register */
1869#define MBC_READ_REMOTE_REG             0x0009 /* Read remote register */
1870#define MBC_RESTART_NIC_FIRMWARE        0x003d /* Restart NIC firmware */
1871#define MBC_SET_ACCESS_CONTROL          0x003e /* Access control command */
1872
1873/* Flash access control option field bit definitions */
1874#define FAC_OPT_FORCE_SEMAPHORE         BIT_15
1875#define FAC_OPT_REQUESTOR_ID            BIT_14
1876#define FAC_OPT_CMD_SUBCODE             0xff
1877
1878/* Flash access control command subcodes */
1879#define FAC_OPT_CMD_WRITE_PROTECT       0x00
1880#define FAC_OPT_CMD_WRITE_ENABLE        0x01
1881#define FAC_OPT_CMD_ERASE_SECTOR        0x02
1882#define FAC_OPT_CMD_LOCK_SEMAPHORE      0x03
1883#define FAC_OPT_CMD_UNLOCK_SEMAPHORE    0x04
1884#define FAC_OPT_CMD_GET_SECTOR_SIZE     0x05
1885
1886/* enhanced features bit definitions */
1887#define NEF_LR_DIST_ENABLE      BIT_0
1888
1889/* LR Distance bit positions */
1890#define LR_DIST_NV_POS          2
1891#define LR_DIST_NV_MASK         0xf
1892#define LR_DIST_FW_POS          12
1893
1894/* FAC semaphore defines */
1895#define FAC_SEMAPHORE_UNLOCK    0
1896#define FAC_SEMAPHORE_LOCK      1
1897
1898struct nvram_81xx {
1899        /* NVRAM header. */
1900        uint8_t id[4];
1901        __le16  nvram_version;
1902        __le16  reserved_0;
1903
1904        /* Firmware Initialization Control Block. */
1905        __le16  version;
1906        __le16  reserved_1;
1907        __le16  frame_payload_size;
1908        __le16  execution_throttle;
1909        __le16  exchange_count;
1910        __le16  reserved_2;
1911
1912        uint8_t port_name[WWN_SIZE];
1913        uint8_t node_name[WWN_SIZE];
1914
1915        __le16  login_retry_count;
1916        __le16  reserved_3;
1917        __le16  interrupt_delay_timer;
1918        __le16  login_timeout;
1919
1920        __le32  firmware_options_1;
1921        __le32  firmware_options_2;
1922        __le32  firmware_options_3;
1923
1924        __le16  reserved_4[4];
1925
1926        /* Offset 64. */
1927        uint8_t enode_mac[6];
1928        __le16  reserved_5[5];
1929
1930        /* Offset 80. */
1931        __le16  reserved_6[24];
1932
1933        /* Offset 128. */
1934        __le16  ex_version;
1935        uint8_t prio_fcf_matching_flags;
1936        uint8_t reserved_6_1[3];
1937        __le16  pri_fcf_vlan_id;
1938        uint8_t pri_fcf_fabric_name[8];
1939        __le16  reserved_6_2[7];
1940        uint8_t spma_mac_addr[6];
1941        __le16  reserved_6_3[14];
1942
1943        /* Offset 192. */
1944        uint8_t min_supported_speed;
1945        uint8_t reserved_7_0;
1946        __le16  reserved_7[31];
1947
1948        /*
1949         * BIT 0  = Enable spinup delay
1950         * BIT 1  = Disable BIOS
1951         * BIT 2  = Enable Memory Map BIOS
1952         * BIT 3  = Enable Selectable Boot
1953         * BIT 4  = Disable RISC code load
1954         * BIT 5  = Disable Serdes
1955         * BIT 6  = Opt boot mode
1956         * BIT 7  = Interrupt enable
1957         *
1958         * BIT 8  = EV Control enable
1959         * BIT 9  = Enable lip reset
1960         * BIT 10 = Enable lip full login
1961         * BIT 11 = Enable target reset
1962         * BIT 12 = Stop firmware
1963         * BIT 13 = Enable nodename option
1964         * BIT 14 = Default WWPN valid
1965         * BIT 15 = Enable alternate WWN
1966         *
1967         * BIT 16 = CLP LUN string
1968         * BIT 17 = CLP Target string
1969         * BIT 18 = CLP BIOS enable string
1970         * BIT 19 = CLP Serdes string
1971         * BIT 20 = CLP WWPN string
1972         * BIT 21 = CLP WWNN string
1973         * BIT 22 =
1974         * BIT 23 =
1975         * BIT 24 = Keep WWPN
1976         * BIT 25 = Temp WWPN
1977         * BIT 26-31 =
1978         */
1979        __le32  host_p;
1980
1981        uint8_t alternate_port_name[WWN_SIZE];
1982        uint8_t alternate_node_name[WWN_SIZE];
1983
1984        uint8_t boot_port_name[WWN_SIZE];
1985        __le16  boot_lun_number;
1986        __le16  reserved_8;
1987
1988        uint8_t alt1_boot_port_name[WWN_SIZE];
1989        __le16  alt1_boot_lun_number;
1990        __le16  reserved_9;
1991
1992        uint8_t alt2_boot_port_name[WWN_SIZE];
1993        __le16  alt2_boot_lun_number;
1994        __le16  reserved_10;
1995
1996        uint8_t alt3_boot_port_name[WWN_SIZE];
1997        __le16  alt3_boot_lun_number;
1998        __le16  reserved_11;
1999
2000        /*

2001         * BIT 0 = Selective Login
2002         * BIT 1 = Alt-Boot Enable
2003         * BIT 2 = Reserved
2004         * BIT 3 = Boot Order List
2005         * BIT 4 = Reserved
2006         * BIT 5 = Selective LUN
2007         * BIT 6 = Reserved
2008         * BIT 7-31 =
2009         */
2010        __le32  efi_parameters;
2011
2012        uint8_t reset_delay;
2013        uint8_t reserved_12;
2014        __le16  reserved_13;
2015
2016        __le16  boot_id_number;
2017        __le16  reserved_14;
2018
2019        __le16  max_luns_per_target;
2020        __le16  reserved_15;
2021
2022        __le16  port_down_retry_count;
2023        __le16  link_down_timeout;
2024
2025        /* FCode parameters. */
2026        __le16  fcode_parameter;
2027
2028        __le16  reserved_16[3];
2029
2030        /* Offset 352. */
2031        uint8_t reserved_17[4];
2032        __le16  reserved_18[5];
2033        uint8_t reserved_19[2];
2034        __le16  reserved_20[8];
2035
2036        /* Offset 384. */
2037        uint8_t reserved_21[16];
2038        __le16  reserved_22[3];
2039
2040        /* Offset 406 (0x196) Enhanced Features
2041         * BIT 0    = Extended BB credits for LR
2042         * BIT 1    = Virtual Fabric Enable
2043         * BIT 2-5  = Distance Support if BIT 0 is on
2044         * BIT 6    = Prefer FCP
2045         * BIT 7    = SCM Disabled if BIT is set (1)
2046         * BIT 8-15 = Unused
2047         */
2048        uint16_t enhanced_features;
2049
2050        uint16_t reserved_24[4];
2051
2052        /* Offset 416. */
2053        __le16  reserved_25[32];
2054
2055        /* Offset 480. */
2056        uint8_t model_name[16];
2057
2058        /* Offset 496. */
2059        __le16  feature_mask_l;
2060        __le16  feature_mask_h;
2061        __le16  reserved_26[2];
2062
2063        __le16  subsystem_vendor_id;
2064        __le16  subsystem_device_id;
2065
2066        __le32  checksum;
2067};
2068
2069/*
2070 * ISP Initialization Control Block.
2071 * Little endian except where noted.
2072 */
2073#define ICB_VERSION 1
2074struct init_cb_81xx {
2075        __le16  version;
2076        __le16  reserved_1;
2077
2078        __le16  frame_payload_size;
2079        __le16  execution_throttle;
2080        __le16  exchange_count;
2081
2082        __le16  reserved_2;
2083
2084        uint8_t port_name[WWN_SIZE];            /* Big endian. */
2085        uint8_t node_name[WWN_SIZE];            /* Big endian. */
2086
2087        __le16  response_q_inpointer;
2088        __le16  request_q_outpointer;
2089
2090        __le16  login_retry_count;
2091
2092        __le16  prio_request_q_outpointer;
2093
2094        __le16  response_q_length;
2095        __le16  request_q_length;
2096
2097        __le16  reserved_3;
2098
2099        __le16  prio_request_q_length;
2100
2101        __le64   request_q_address __packed;
2102        __le64   response_q_address __packed;
2103        __le64   prio_request_q_address __packed;
2104
2105        uint8_t reserved_4[8];
2106
2107        __le16  atio_q_inpointer;
2108        __le16  atio_q_length;
2109        __le64   atio_q_address __packed;
2110
2111        __le16  interrupt_delay_timer;          /* 100us increments. */
2112        __le16  login_timeout;
2113
2114        /*
2115         * BIT 0-3 = Reserved
2116         * BIT 4  = Enable Target Mode
2117         * BIT 5  = Disable Initiator Mode
2118         * BIT 6  = Reserved
2119         * BIT 7  = Reserved
2120         *
2121         * BIT 8-13 = Reserved
2122         * BIT 14 = Node Name Option
2123         * BIT 15-31 = Reserved
2124         */
2125        __le32  firmware_options_1;
2126
2127        /*
2128         * BIT 0  = Operation Mode bit 0
2129         * BIT 1  = Operation Mode bit 1
2130         * BIT 2  = Operation Mode bit 2
2131         * BIT 3  = Operation Mode bit 3
2132         * BIT 4-7 = Reserved
2133         *
2134         * BIT 8  = Enable Class 2
2135         * BIT 9  = Enable ACK0
2136         * BIT 10 = Reserved
2137         * BIT 11 = Enable FC-SP Security
2138         * BIT 12 = FC Tape Enable
2139         * BIT 13 = Reserved
2140         * BIT 14 = Enable Target PRLI Control
2141         * BIT 15-31 = Reserved
2142         */
2143        __le32  firmware_options_2;
2144
2145        /*
2146         * BIT 0-3 = Reserved
2147         * BIT 4  = FCP RSP Payload bit 0
2148         * BIT 5  = FCP RSP Payload bit 1
2149         * BIT 6  = Enable Receive Out-of-Order data frame handling
2150         * BIT 7  = Reserved
2151         *
2152         * BIT 8  = Reserved
2153         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
2154         * BIT 10-16 = Reserved
2155         * BIT 17 = Enable multiple FCFs
2156         * BIT 18-20 = MAC addressing mode
2157         * BIT 21-25 = Ethernet data rate
2158         * BIT 26 = Enable ethernet header rx IOCB for ATIO q
2159         * BIT 27 = Enable ethernet header rx IOCB for response q
2160         * BIT 28 = SPMA selection bit 0
2161         * BIT 28 = SPMA selection bit 1
2162         * BIT 30-31 = Reserved
2163         */
2164        __le32  firmware_options_3;
2165
2166        uint8_t  reserved_5[8];
2167
2168        uint8_t enode_mac[6];
2169
2170        uint8_t reserved_6[10];
2171};
2172
2173struct mid_init_cb_81xx {
2174        struct init_cb_81xx init_cb;
2175
2176        uint16_t count;
2177        uint16_t options;
2178
2179        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
2180};
2181
2182struct ex_init_cb_81xx {
2183        uint16_t ex_version;
2184        uint8_t prio_fcf_matching_flags;
2185        uint8_t reserved_1[3];
2186        uint16_t pri_fcf_vlan_id;
2187        uint8_t pri_fcf_fabric_name[8];
2188        uint16_t reserved_2[7];
2189        uint8_t spma_mac_addr[6];
2190        uint16_t reserved_3[14];
2191};
2192
2193#define FARX_ACCESS_FLASH_CONF_81XX     0x7FFD0000
2194#define FARX_ACCESS_FLASH_DATA_81XX     0x7F800000
2195#define FARX_ACCESS_FLASH_CONF_28XX     0x7FFD0000
2196#define FARX_ACCESS_FLASH_DATA_28XX     0x7F7D0000
2197
2198/* FCP priority config defines *************************************/
2199/* operations */
2200#define QLFC_FCP_PRIO_DISABLE           0x0
2201#define QLFC_FCP_PRIO_ENABLE            0x1
2202#define QLFC_FCP_PRIO_GET_CONFIG        0x2
2203#define QLFC_FCP_PRIO_SET_CONFIG        0x3
2204
2205struct qla_fcp_prio_entry {
2206        uint16_t flags;         /* Describes parameter(s) in FCP        */
2207        /* priority entry that are valid        */
2208#define FCP_PRIO_ENTRY_VALID            0x1
2209#define FCP_PRIO_ENTRY_TAG_VALID        0x2
2210#define FCP_PRIO_ENTRY_SPID_VALID       0x4
2211#define FCP_PRIO_ENTRY_DPID_VALID       0x8
2212#define FCP_PRIO_ENTRY_LUNB_VALID       0x10
2213#define FCP_PRIO_ENTRY_LUNE_VALID       0x20
2214#define FCP_PRIO_ENTRY_SWWN_VALID       0x40
2215#define FCP_PRIO_ENTRY_DWWN_VALID       0x80
2216        uint8_t  tag;           /* Priority value                   */
2217        uint8_t  reserved;      /* Reserved for future use          */
2218        uint32_t src_pid;       /* Src port id. high order byte     */
2219                                /* unused; -1 (wild card)           */
2220        uint32_t dst_pid;       /* Src port id. high order byte     */
2221        /* unused; -1 (wild card)           */
2222        uint16_t lun_beg;       /* 1st lun num of lun range.        */
2223                                /* -1 (wild card)                   */
2224        uint16_t lun_end;       /* 2nd lun num of lun range.        */
2225                                /* -1 (wild card)                   */
2226        uint8_t  src_wwpn[8];   /* Source WWPN: -1 (wild card)      */
2227        uint8_t  dst_wwpn[8];   /* Destination WWPN: -1 (wild card) */
2228};
2229
2230struct qla_fcp_prio_cfg {
2231        uint8_t  signature[4];  /* "HQOS" signature of config data  */
2232        uint16_t version;       /* 1: Initial version               */
2233        uint16_t length;        /* config data size in num bytes    */
2234        uint16_t checksum;      /* config data bytes checksum       */
2235        uint16_t num_entries;   /* Number of entries                */
2236        uint16_t size_of_entry; /* Size of each entry in num bytes  */
2237        uint8_t  attributes;    /* enable/disable, persistence      */
2238#define FCP_PRIO_ATTR_DISABLE   0x0
2239#define FCP_PRIO_ATTR_ENABLE    0x1
2240#define FCP_PRIO_ATTR_PERSIST   0x2
2241        uint8_t  reserved;      /* Reserved for future use          */
2242#define FCP_PRIO_CFG_HDR_SIZE   offsetof(struct qla_fcp_prio_cfg, entry)
2243        struct qla_fcp_prio_entry entry[1023]; /* fcp priority entries  */
2244        uint8_t  reserved2[16];
2245};
2246
2247#define FCP_PRIO_CFG_SIZE       (32*1024) /* fcp prio data per port*/
2248
2249/* 25XX Support ****************************************************/
2250#define FA_FCP_PRIO0_ADDR_25    0x3C000
2251#define FA_FCP_PRIO1_ADDR_25    0x3E000
2252
2253/* 81XX Flash locations -- occupies second 2MB region. */
2254#define FA_BOOT_CODE_ADDR_81    0x80000
2255#define FA_RISC_CODE_ADDR_81    0xA0000
2256#define FA_FW_AREA_ADDR_81      0xC0000
2257#define FA_VPD_NVRAM_ADDR_81    0xD0000
2258#define FA_VPD0_ADDR_81         0xD0000
2259#define FA_VPD1_ADDR_81         0xD0400
2260#define FA_NVRAM0_ADDR_81       0xD0080
2261#define FA_NVRAM1_ADDR_81       0xD0180
2262#define FA_FEATURE_ADDR_81      0xD4000
2263#define FA_FLASH_DESCR_ADDR_81  0xD8000
2264#define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2265#define FA_HW_EVENT0_ADDR_81    0xDC000
2266#define FA_HW_EVENT1_ADDR_81    0xDC400
2267#define FA_NPIV_CONF0_ADDR_81   0xD1000
2268#define FA_NPIV_CONF1_ADDR_81   0xD2000
2269
2270/* 83XX Flash locations -- occupies second 8MB region. */
2271#define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2272#define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2273
2274#define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196
2275
2276#endif
2277