1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#ifndef _VNIC_INTR_H_
19#define _VNIC_INTR_H_
20
21#include <linux/pci.h>
22#include "vnic_dev.h"
23
24#define VNIC_INTR_TIMER_MAX 0xffff
25
26#define VNIC_INTR_TIMER_TYPE_ABS 0
27#define VNIC_INTR_TIMER_TYPE_QUIET 1
28
29
30struct vnic_intr_ctrl {
31 u32 coalescing_timer;
32 u32 pad0;
33 u32 coalescing_value;
34 u32 pad1;
35 u32 coalescing_type;
36 u32 pad2;
37 u32 mask_on_assertion;
38 u32 pad3;
39 u32 mask;
40 u32 pad4;
41 u32 int_credits;
42 u32 pad5;
43 u32 int_credit_return;
44 u32 pad6;
45};
46
47struct vnic_intr {
48 unsigned int index;
49 struct vnic_dev *vdev;
50 struct vnic_intr_ctrl __iomem *ctrl;
51};
52
53static inline void
54svnic_intr_unmask(struct vnic_intr *intr)
55{
56 iowrite32(0, &intr->ctrl->mask);
57}
58
59static inline void
60svnic_intr_mask(struct vnic_intr *intr)
61{
62 iowrite32(1, &intr->ctrl->mask);
63}
64
65static inline void
66svnic_intr_return_credits(struct vnic_intr *intr,
67 unsigned int credits,
68 int unmask,
69 int reset_timer)
70{
71#define VNIC_INTR_UNMASK_SHIFT 16
72#define VNIC_INTR_RESET_TIMER_SHIFT 17
73
74 u32 int_credit_return = (credits & 0xffff) |
75 (unmask ? (1 << VNIC_INTR_UNMASK_SHIFT) : 0) |
76 (reset_timer ? (1 << VNIC_INTR_RESET_TIMER_SHIFT) : 0);
77
78 iowrite32(int_credit_return, &intr->ctrl->int_credit_return);
79}
80
81static inline unsigned int
82svnic_intr_credits(struct vnic_intr *intr)
83{
84 return ioread32(&intr->ctrl->int_credits);
85}
86
87static inline void
88svnic_intr_return_all_credits(struct vnic_intr *intr)
89{
90 unsigned int credits = svnic_intr_credits(intr);
91 int unmask = 1;
92 int reset_timer = 1;
93
94 svnic_intr_return_credits(intr, credits, unmask, reset_timer);
95}
96
97void svnic_intr_free(struct vnic_intr *);
98int svnic_intr_alloc(struct vnic_dev *, struct vnic_intr *, unsigned int);
99void svnic_intr_init(struct vnic_intr *intr,
100 unsigned int coalescing_timer,
101 unsigned int coalescing_type,
102 unsigned int mask_on_assertion);
103void svnic_intr_clean(struct vnic_intr *);
104
105#endif
106