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13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/pm_domain.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21
22#define GPC_CNTR 0x000
23
24#define GPC_PGC_CTRL_OFFS 0x0
25#define GPC_PGC_PUPSCR_OFFS 0x4
26#define GPC_PGC_PDNSCR_OFFS 0x8
27#define GPC_PGC_SW2ISO_SHIFT 0x8
28#define GPC_PGC_SW_SHIFT 0x0
29
30#define GPC_PGC_PCI_PDN 0x200
31#define GPC_PGC_PCI_SR 0x20c
32
33#define GPC_PGC_GPU_PDN 0x260
34#define GPC_PGC_GPU_PUPSCR 0x264
35#define GPC_PGC_GPU_PDNSCR 0x268
36#define GPC_PGC_GPU_SR 0x26c
37
38#define GPC_PGC_DISP_PDN 0x240
39#define GPC_PGC_DISP_SR 0x24c
40
41#define GPU_VPU_PUP_REQ BIT(1)
42#define GPU_VPU_PDN_REQ BIT(0)
43
44#define GPC_CLK_MAX 6
45
46#define PGC_DOMAIN_FLAG_NO_PD BIT(0)
47
48struct imx_pm_domain {
49 struct generic_pm_domain base;
50 struct regmap *regmap;
51 struct regulator *supply;
52 struct clk *clk[GPC_CLK_MAX];
53 int num_clks;
54 unsigned int reg_offs;
55 signed char cntr_pdn_bit;
56 unsigned int ipg_rate_mhz;
57 unsigned int flags;
58};
59
60static inline struct imx_pm_domain *
61to_imx_pm_domain(struct generic_pm_domain *genpd)
62{
63 return container_of(genpd, struct imx_pm_domain, base);
64}
65
66static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
67{
68 struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
69 int iso, iso2sw;
70 u32 val;
71
72 if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
73 return -EBUSY;
74
75
76 regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
77 iso = val & 0x3f;
78 iso2sw = (val >> 8) & 0x3f;
79
80
81 regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
82 0x1, 0x1);
83
84
85 val = BIT(pd->cntr_pdn_bit);
86 regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
87
88
89 udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
90
91 if (pd->supply)
92 regulator_disable(pd->supply);
93
94 return 0;
95}
96
97static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
98{
99 struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
100 int i, ret, sw, sw2iso;
101 u32 val;
102
103 if (pd->supply) {
104 ret = regulator_enable(pd->supply);
105 if (ret) {
106 pr_err("%s: failed to enable regulator: %d\n",
107 __func__, ret);
108 return ret;
109 }
110 }
111
112
113 for (i = 0; i < pd->num_clks; i++)
114 clk_prepare_enable(pd->clk[i]);
115
116
117 regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
118 0x1, 0x1);
119
120
121 regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
122 sw = val & 0x3f;
123 sw2iso = (val >> 8) & 0x3f;
124
125
126 val = BIT(pd->cntr_pdn_bit + 1);
127 regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
128
129
130 udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
131
132
133 for (i = 0; i < pd->num_clks; i++)
134 clk_disable_unprepare(pd->clk[i]);
135
136 return 0;
137}
138
139static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
140{
141 int i, ret;
142
143 for (i = 0; ; i++) {
144 struct clk *clk = of_clk_get(dev->of_node, i);
145 if (IS_ERR(clk))
146 break;
147 if (i >= GPC_CLK_MAX) {
148 dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
149 ret = -EINVAL;
150 goto clk_err;
151 }
152 domain->clk[i] = clk;
153 }
154 domain->num_clks = i;
155
156 return 0;
157
158clk_err:
159 while (i--)
160 clk_put(domain->clk[i]);
161
162 return ret;
163}
164
165static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
166{
167 int i;
168
169 for (i = domain->num_clks - 1; i >= 0; i--)
170 clk_put(domain->clk[i]);
171}
172
173static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
174{
175
176 domain->supply = devm_regulator_get_optional(dev, "power");
177 if (IS_ERR(domain->supply)) {
178 if (PTR_ERR(domain->supply) == -ENODEV)
179 domain->supply = NULL;
180 else
181 return PTR_ERR(domain->supply);
182 }
183
184
185 return imx_pgc_get_clocks(dev, domain);
186}
187
188static int imx_pgc_power_domain_probe(struct platform_device *pdev)
189{
190 struct imx_pm_domain *domain = pdev->dev.platform_data;
191 struct device *dev = &pdev->dev;
192 int ret;
193
194
195 if (dev->of_node) {
196 ret = imx_pgc_parse_dt(dev, domain);
197 if (ret)
198 return ret;
199 }
200
201
202 if (domain->base.power_on)
203 domain->base.power_on(&domain->base);
204
205 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
206 pm_genpd_init(&domain->base, NULL, false);
207 ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
208 if (ret)
209 goto genpd_err;
210 }
211
212 device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE_CONSUMER);
213
214 return 0;
215
216genpd_err:
217 pm_genpd_remove(&domain->base);
218 imx_pgc_put_clocks(domain);
219
220 return ret;
221}
222
223static int imx_pgc_power_domain_remove(struct platform_device *pdev)
224{
225 struct imx_pm_domain *domain = pdev->dev.platform_data;
226
227 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
228 of_genpd_del_provider(pdev->dev.of_node);
229 pm_genpd_remove(&domain->base);
230 imx_pgc_put_clocks(domain);
231 }
232
233 return 0;
234}
235
236static const struct platform_device_id imx_pgc_power_domain_id[] = {
237 { "imx-pgc-power-domain"},
238 { },
239};
240
241static struct platform_driver imx_pgc_power_domain_driver = {
242 .driver = {
243 .name = "imx-pgc-pd",
244 },
245 .probe = imx_pgc_power_domain_probe,
246 .remove = imx_pgc_power_domain_remove,
247 .id_table = imx_pgc_power_domain_id,
248};
249builtin_platform_driver(imx_pgc_power_domain_driver)
250
251#define GPC_PGC_DOMAIN_ARM 0
252#define GPC_PGC_DOMAIN_PU 1
253#define GPC_PGC_DOMAIN_DISPLAY 2
254
255static struct genpd_power_state imx6_pm_domain_pu_state = {
256 .power_off_latency_ns = 25000,
257 .power_on_latency_ns = 2000000,
258};
259
260static struct imx_pm_domain imx_gpc_domains[] = {
261 {
262 .base = {
263 .name = "ARM",
264 .flags = GENPD_FLAG_ALWAYS_ON,
265 },
266 }, {
267 .base = {
268 .name = "PU",
269 .power_off = imx6_pm_domain_power_off,
270 .power_on = imx6_pm_domain_power_on,
271 .states = &imx6_pm_domain_pu_state,
272 .state_count = 1,
273 },
274 .reg_offs = 0x260,
275 .cntr_pdn_bit = 0,
276 }, {
277 .base = {
278 .name = "DISPLAY",
279 .power_off = imx6_pm_domain_power_off,
280 .power_on = imx6_pm_domain_power_on,
281 },
282 .reg_offs = 0x240,
283 .cntr_pdn_bit = 4,
284 }, {
285 .base = {
286 .name = "PCI",
287 .power_off = imx6_pm_domain_power_off,
288 .power_on = imx6_pm_domain_power_on,
289 },
290 .reg_offs = 0x200,
291 .cntr_pdn_bit = 6,
292 },
293};
294
295struct imx_gpc_dt_data {
296 int num_domains;
297 bool err009619_present;
298};
299
300static const struct imx_gpc_dt_data imx6q_dt_data = {
301 .num_domains = 2,
302 .err009619_present = false,
303};
304
305static const struct imx_gpc_dt_data imx6qp_dt_data = {
306 .num_domains = 2,
307 .err009619_present = true,
308};
309
310static const struct imx_gpc_dt_data imx6sl_dt_data = {
311 .num_domains = 3,
312 .err009619_present = false,
313};
314
315static const struct imx_gpc_dt_data imx6sx_dt_data = {
316 .num_domains = 4,
317 .err009619_present = false,
318};
319
320static const struct of_device_id imx_gpc_dt_ids[] = {
321 { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
322 { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
323 { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
324 { .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
325 { }
326};
327
328static const struct regmap_range yes_ranges[] = {
329 regmap_reg_range(GPC_CNTR, GPC_CNTR),
330 regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
331 regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
332 regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
333};
334
335static const struct regmap_access_table access_table = {
336 .yes_ranges = yes_ranges,
337 .n_yes_ranges = ARRAY_SIZE(yes_ranges),
338};
339
340static const struct regmap_config imx_gpc_regmap_config = {
341 .reg_bits = 32,
342 .val_bits = 32,
343 .reg_stride = 4,
344 .rd_table = &access_table,
345 .wr_table = &access_table,
346 .max_register = 0x2ac,
347};
348
349static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
350 &imx_gpc_domains[0].base,
351 &imx_gpc_domains[1].base,
352};
353
354static struct genpd_onecell_data imx_gpc_onecell_data = {
355 .domains = imx_gpc_onecell_domains,
356 .num_domains = 2,
357};
358
359static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
360 unsigned int num_domains)
361{
362 struct imx_pm_domain *domain;
363 int i, ret;
364
365 for (i = 0; i < num_domains; i++) {
366 domain = &imx_gpc_domains[i];
367 domain->regmap = regmap;
368 domain->ipg_rate_mhz = 66;
369
370 if (i == 1) {
371 domain->supply = devm_regulator_get(dev, "pu");
372 if (IS_ERR(domain->supply))
373 return PTR_ERR(domain->supply);
374
375 ret = imx_pgc_get_clocks(dev, domain);
376 if (ret)
377 goto clk_err;
378
379 domain->base.power_on(&domain->base);
380 }
381 }
382
383 for (i = 0; i < num_domains; i++)
384 pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
385
386 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
387 ret = of_genpd_add_provider_onecell(dev->of_node,
388 &imx_gpc_onecell_data);
389 if (ret)
390 goto genpd_err;
391 }
392
393 return 0;
394
395genpd_err:
396 for (i = 0; i < num_domains; i++)
397 pm_genpd_remove(&imx_gpc_domains[i].base);
398 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
399clk_err:
400 return ret;
401}
402
403static int imx_gpc_probe(struct platform_device *pdev)
404{
405 const struct of_device_id *of_id =
406 of_match_device(imx_gpc_dt_ids, &pdev->dev);
407 const struct imx_gpc_dt_data *of_id_data = of_id->data;
408 struct device_node *pgc_node;
409 struct regmap *regmap;
410 struct resource *res;
411 void __iomem *base;
412 int ret;
413
414 pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
415
416
417 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
418 !pgc_node)
419 return 0;
420
421 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
422 base = devm_ioremap_resource(&pdev->dev, res);
423 if (IS_ERR(base))
424 return PTR_ERR(base);
425
426 regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
427 &imx_gpc_regmap_config);
428 if (IS_ERR(regmap)) {
429 ret = PTR_ERR(regmap);
430 dev_err(&pdev->dev, "failed to init regmap: %d\n",
431 ret);
432 return ret;
433 }
434
435
436 if (of_id_data->err009619_present)
437 imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
438 PGC_DOMAIN_FLAG_NO_PD;
439
440 if (!pgc_node) {
441 ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
442 of_id_data->num_domains);
443 if (ret)
444 return ret;
445 } else {
446 struct imx_pm_domain *domain;
447 struct platform_device *pd_pdev;
448 struct device_node *np;
449 struct clk *ipg_clk;
450 unsigned int ipg_rate_mhz;
451 int domain_index;
452
453 ipg_clk = devm_clk_get(&pdev->dev, "ipg");
454 if (IS_ERR(ipg_clk))
455 return PTR_ERR(ipg_clk);
456 ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
457
458 for_each_child_of_node(pgc_node, np) {
459 ret = of_property_read_u32(np, "reg", &domain_index);
460 if (ret) {
461 of_node_put(np);
462 return ret;
463 }
464 if (domain_index >= of_id_data->num_domains)
465 continue;
466
467 pd_pdev = platform_device_alloc("imx-pgc-power-domain",
468 domain_index);
469 if (!pd_pdev) {
470 of_node_put(np);
471 return -ENOMEM;
472 }
473
474 ret = platform_device_add_data(pd_pdev,
475 &imx_gpc_domains[domain_index],
476 sizeof(imx_gpc_domains[domain_index]));
477 if (ret) {
478 platform_device_put(pd_pdev);
479 of_node_put(np);
480 return ret;
481 }
482 domain = pd_pdev->dev.platform_data;
483 domain->regmap = regmap;
484 domain->ipg_rate_mhz = ipg_rate_mhz;
485
486 pd_pdev->dev.parent = &pdev->dev;
487 pd_pdev->dev.of_node = np;
488
489 ret = platform_device_add(pd_pdev);
490 if (ret) {
491 platform_device_put(pd_pdev);
492 of_node_put(np);
493 return ret;
494 }
495 }
496 }
497
498 return 0;
499}
500
501static int imx_gpc_remove(struct platform_device *pdev)
502{
503 struct device_node *pgc_node;
504 int ret;
505
506 pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
507
508
509 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
510 !pgc_node)
511 return 0;
512
513
514
515
516
517 if (!pgc_node) {
518 of_genpd_del_provider(pdev->dev.of_node);
519
520 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
521 if (ret)
522 return ret;
523 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
524
525 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
526 if (ret)
527 return ret;
528 }
529
530 return 0;
531}
532
533static struct platform_driver imx_gpc_driver = {
534 .driver = {
535 .name = "imx-gpc",
536 .of_match_table = imx_gpc_dt_ids,
537 },
538 .probe = imx_gpc_probe,
539 .remove = imx_gpc_remove,
540};
541builtin_platform_driver(imx_gpc_driver)
542
