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36#include <linux/module.h>
37#include <linux/delay.h>
38#include <linux/dma-mapping.h>
39#include <linux/spinlock.h>
40#include <linux/platform_device.h>
41
42#include <linux/mmc/host.h>
43#include <linux/mmc/mmc.h>
44#include <linux/mmc/sd.h>
45#include <linux/mmc/sdio.h>
46
47#include <asm/mach-ralink/ralink_regs.h>
48
49#include "board.h"
50#include "dbg.h"
51#include "mt6575_sd.h"
52
53
54#ifdef CONFIG_SOC_MT7621
55#define RALINK_SYSCTL_BASE 0xbe000000
56#define RALINK_MSDC_BASE 0xbe130000
57#else
58#define RALINK_SYSCTL_BASE 0xb0000000
59#define RALINK_MSDC_BASE 0xb0130000
60#endif
61#define IRQ_SDC 22
62
63#define DRV_NAME "mtk-sd"
64
65#if defined(CONFIG_SOC_MT7620)
66#define HOST_MAX_MCLK (48000000)
67#elif defined(CONFIG_SOC_MT7621)
68#define HOST_MAX_MCLK (50000000)
69#endif
70#define HOST_MIN_MCLK (260000)
71
72#define HOST_MAX_BLKSZ (2048)
73
74#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
75
76#define GPIO_PULL_DOWN (0)
77#define GPIO_PULL_UP (1)
78
79#if 0
80#define MSDC_CLKSRC_REG (0xf100000C)
81#define PDN_REG (0xF1000010)
82#endif
83
84#define DEFAULT_DEBOUNCE (8)
85#define DEFAULT_DTOC (40)
86
87#define CMD_TIMEOUT (HZ / 10)
88#define DAT_TIMEOUT (HZ / 2 * 5)
89
90#define MAX_DMA_CNT (64 * 1024 - 512)
91
92#define MAX_GPD_NUM (1 + 1)
93#define MAX_BD_NUM (1024)
94#define MAX_BD_PER_GPD (MAX_BD_NUM)
95
96#define MAX_HW_SGMTS (MAX_BD_NUM)
97#define MAX_PHY_SGMTS (MAX_BD_NUM)
98#define MAX_SGMT_SZ (MAX_DMA_CNT)
99#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
100
101static int cd_active_low = 1;
102
103
104#define PERI_MSDC0_PDN (15)
105
106
107
108
109#if 0
110
111static int g_clk_gate = 0;
112#define msdc_gate_clock(id) \
113 do { \
114 g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
115 } while (0)
116
117#define msdc_ungate_clock(id) \
118 do { \
119 g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
120 } while (0)
121
122
123void msdc_clk_status(int *status)
124{
125 *status = g_clk_gate;
126}
127#endif
128
129
130struct msdc_hw msdc0_hw = {
131 .clk_src = 0,
132 .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE,
133
134};
135
136
137
138static int msdc_rsp[] = {
139 0,
140 1,
141 2,
142 3,
143 4,
144 1,
145 1,
146 1,
147 7,
148};
149
150#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
151#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
152#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
153#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
154#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
155#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
156
157#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
158
159#define msdc_retry(expr, retry, cnt) \
160 do { \
161 int backup = cnt; \
162 while (retry) { \
163 if (!(expr)) \
164 break; \
165 if (cnt-- == 0) { \
166 retry--; mdelay(1); cnt = backup; \
167 } \
168 } \
169 WARN_ON(retry == 0); \
170 } while (0)
171
172static void msdc_reset_hw(struct msdc_host *host)
173{
174 void __iomem *base = host->base;
175
176 sdr_set_bits(MSDC_CFG, MSDC_CFG_RST);
177 while (sdr_read32(MSDC_CFG) & MSDC_CFG_RST)
178 cpu_relax();
179}
180
181#define msdc_clr_int() \
182 do { \
183 volatile u32 val = sdr_read32(MSDC_INT); \
184 sdr_write32(MSDC_INT, val); \
185 } while (0)
186
187#define msdc_clr_fifo() \
188 do { \
189 int retry = 3, cnt = 1000; \
190 sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
191 msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
192 } while (0)
193
194#define msdc_irq_save(val) \
195 do { \
196 val = sdr_read32(MSDC_INTEN); \
197 sdr_clr_bits(MSDC_INTEN, val); \
198 } while (0)
199
200#define msdc_irq_restore(val) \
201 do { \
202 sdr_set_bits(MSDC_INTEN, val); \
203 } while (0)
204
205
206#if defined(CONFIG_SOC_MT7620)
207static u32 hclks[] = {48000000};
208#elif defined(CONFIG_SOC_MT7621)
209static u32 hclks[] = {50000000};
210#endif
211
212
213
214
215
216#define msdc_vcore_on(host) \
217 do { \
218 INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
219 (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
220 } while (0)
221#define msdc_vcore_off(host) \
222 do { \
223 INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
224 (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
225 } while (0)
226
227
228
229
230
231#define msdc_vdd_on(host) \
232 do { \
233 (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
234 } while (0)
235#define msdc_vdd_off(host) \
236 do { \
237 (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
238 } while (0)
239
240#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
241#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
242
243#define sdc_send_cmd(cmd, arg) \
244 do { \
245 sdr_write32(SDC_ARG, (arg)); \
246 sdr_write32(SDC_CMD, (cmd)); \
247 } while (0)
248
249
250
251#define is_card_present(h) (((struct msdc_host *)(h))->card_inserted)
252
253
254#ifndef __ASSEMBLY__
255#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
256#else
257#define PHYSADDR(a) ((a) & 0x1fffffff)
258#endif
259
260static unsigned int msdc_do_command(struct msdc_host *host,
261 struct mmc_command *cmd,
262 int tune,
263 unsigned long timeout);
264
265static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);
266
267#ifdef MT6575_SD_DEBUG
268static void msdc_dump_card_status(struct msdc_host *host, u32 status)
269{
270
271#if 0
272 static char *state[] = {
273 "Idle",
274 "Ready",
275 "Ident",
276 "Stby",
277 "Tran",
278 "Data",
279 "Rcv",
280 "Prg",
281 "Dis",
282 "Reserved",
283 "Reserved",
284 "Reserved",
285 "Reserved",
286 "Reserved",
287 "Reserved",
288 "I/O mode",
289 };
290#endif
291 if (status & R1_OUT_OF_RANGE)
292 N_MSG(RSP, "[CARD_STATUS] Out of Range");
293 if (status & R1_ADDRESS_ERROR)
294 N_MSG(RSP, "[CARD_STATUS] Address Error");
295 if (status & R1_BLOCK_LEN_ERROR)
296 N_MSG(RSP, "[CARD_STATUS] Block Len Error");
297 if (status & R1_ERASE_SEQ_ERROR)
298 N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
299 if (status & R1_ERASE_PARAM)
300 N_MSG(RSP, "[CARD_STATUS] Erase Param");
301 if (status & R1_WP_VIOLATION)
302 N_MSG(RSP, "[CARD_STATUS] WP Violation");
303 if (status & R1_CARD_IS_LOCKED)
304 N_MSG(RSP, "[CARD_STATUS] Card is Locked");
305 if (status & R1_LOCK_UNLOCK_FAILED)
306 N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
307 if (status & R1_COM_CRC_ERROR)
308 N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
309 if (status & R1_ILLEGAL_COMMAND)
310 N_MSG(RSP, "[CARD_STATUS] Illegal Command");
311 if (status & R1_CARD_ECC_FAILED)
312 N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
313 if (status & R1_CC_ERROR)
314 N_MSG(RSP, "[CARD_STATUS] CC Error");
315 if (status & R1_ERROR)
316 N_MSG(RSP, "[CARD_STATUS] Error");
317 if (status & R1_UNDERRUN)
318 N_MSG(RSP, "[CARD_STATUS] Underrun");
319 if (status & R1_OVERRUN)
320 N_MSG(RSP, "[CARD_STATUS] Overrun");
321 if (status & R1_CID_CSD_OVERWRITE)
322 N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
323 if (status & R1_WP_ERASE_SKIP)
324 N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
325 if (status & R1_CARD_ECC_DISABLED)
326 N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
327 if (status & R1_ERASE_RESET)
328 N_MSG(RSP, "[CARD_STATUS] Erase Reset");
329 if (status & R1_READY_FOR_DATA)
330 N_MSG(RSP, "[CARD_STATUS] Ready for Data");
331 if (status & R1_SWITCH_ERROR)
332 N_MSG(RSP, "[CARD_STATUS] Switch error");
333 if (status & R1_APP_CMD)
334 N_MSG(RSP, "[CARD_STATUS] App Command");
335
336 N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
337}
338
339static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
340{
341 if (resp & (1 << 7))
342 N_MSG(RSP, "[OCR] Low Voltage Range");
343 if (resp & (1 << 15))
344 N_MSG(RSP, "[OCR] 2.7-2.8 volt");
345 if (resp & (1 << 16))
346 N_MSG(RSP, "[OCR] 2.8-2.9 volt");
347 if (resp & (1 << 17))
348 N_MSG(RSP, "[OCR] 2.9-3.0 volt");
349 if (resp & (1 << 18))
350 N_MSG(RSP, "[OCR] 3.0-3.1 volt");
351 if (resp & (1 << 19))
352 N_MSG(RSP, "[OCR] 3.1-3.2 volt");
353 if (resp & (1 << 20))
354 N_MSG(RSP, "[OCR] 3.2-3.3 volt");
355 if (resp & (1 << 21))
356 N_MSG(RSP, "[OCR] 3.3-3.4 volt");
357 if (resp & (1 << 22))
358 N_MSG(RSP, "[OCR] 3.4-3.5 volt");
359 if (resp & (1 << 23))
360 N_MSG(RSP, "[OCR] 3.5-3.6 volt");
361 if (resp & (1 << 24))
362 N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
363 if (resp & (1 << 30))
364 N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
365 if (resp & (1 << 31))
366 N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
367 else
368 N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
369}
370
371static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
372{
373 u32 status = (((resp >> 15) & 0x1) << 23) |
374 (((resp >> 14) & 0x1) << 22) |
375 (((resp >> 13) & 0x1) << 19) |
376 (resp & 0x1fff);
377
378 N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
379 msdc_dump_card_status(host, status);
380}
381
382static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
383{
384 u32 flags = (resp >> 8) & 0xFF;
385#if 0
386 char *state[] = {"DIS", "CMD", "TRN", "RFU"};
387#endif
388 if (flags & (1 << 7))
389 N_MSG(RSP, "[IO] COM_CRC_ERR");
390 if (flags & (1 << 6))
391 N_MSG(RSP, "[IO] Illegal command");
392 if (flags & (1 << 3))
393 N_MSG(RSP, "[IO] Error");
394 if (flags & (1 << 2))
395 N_MSG(RSP, "[IO] RFU");
396 if (flags & (1 << 1))
397 N_MSG(RSP, "[IO] Function number error");
398 if (flags & (1 << 0))
399 N_MSG(RSP, "[IO] Out of range");
400
401 N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
402}
403#endif
404
405static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
406{
407 void __iomem *base = host->base;
408 u32 timeout, clk_ns;
409
410 host->timeout_ns = ns;
411 host->timeout_clks = clks;
412
413 clk_ns = 1000000000UL / host->sclk;
414 timeout = ns / clk_ns + clks;
415 timeout = timeout >> 16;
416 timeout = timeout > 1 ? timeout - 1 : 0;
417 timeout = timeout > 255 ? 255 : timeout;
418
419 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
420
421 N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
422 ns, clks, timeout + 1);
423}
424
425static void msdc_tasklet_card(struct work_struct *work)
426{
427 struct msdc_host *host = (struct msdc_host *)container_of(work,
428 struct msdc_host, card_delaywork.work);
429 void __iomem *base = host->base;
430 u32 inserted;
431 u32 status = 0;
432
433
434 spin_lock(&host->lock);
435
436 status = sdr_read32(MSDC_PS);
437 if (cd_active_low)
438 inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
439 else
440 inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
441
442#if 0
443 change = host->card_inserted ^ inserted;
444 host->card_inserted = inserted;
445
446 if (change && !host->suspend) {
447 if (inserted)
448 host->mmc->f_max = HOST_MAX_MCLK;
449 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
450 }
451#else
452 host->card_inserted = inserted;
453
454 if (!host->suspend) {
455 host->mmc->f_max = HOST_MAX_MCLK;
456 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
457 }
458
459 IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
460#endif
461
462 spin_unlock(&host->lock);
463}
464
465#if 0
466
467static u8 clk_src_bit[4] = {
468 0, 3, 5, 7
469};
470
471static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)
472{
473 u32 val;
474 void __iomem *base = host->base;
475
476 BUG_ON(clksrc > 3);
477 INIT_MSG("set clock source to <%d>", clksrc);
478
479 val = sdr_read32(MSDC_CLKSRC_REG);
480 if (sdr_read32(MSDC_ECO_VER) >= 4) {
481 val &= ~(0x3 << clk_src_bit[host->id]);
482 val |= clksrc << clk_src_bit[host->id];
483 } else {
484 val &= ~0x3; val |= clksrc;
485 }
486 sdr_write32(MSDC_CLKSRC_REG, val);
487
488 host->hclk = hclks[clksrc];
489 host->hw->clk_src = clksrc;
490}
491#endif
492
493static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
494{
495
496 void __iomem *base = host->base;
497 u32 mode;
498 u32 flags;
499 u32 div;
500 u32 sclk;
501 u32 hclk = host->hclk;
502
503
504 if (!hz) {
505
506 msdc_reset_hw(host);
507 return;
508 }
509
510 msdc_irq_save(flags);
511
512 if (ddr) {
513 mode = 0x2;
514 if (hz >= (hclk >> 2)) {
515 div = 1;
516 sclk = hclk >> 2;
517 } else {
518 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
519 sclk = (hclk >> 2) / div;
520 }
521 } else if (hz >= hclk) {
522 mode = 0x1;
523 div = 0;
524 sclk = hclk;
525 } else {
526 mode = 0x0;
527 if (hz >= (hclk >> 1)) {
528 div = 0;
529 sclk = hclk >> 1;
530 } else {
531 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
532 sclk = (hclk >> 2) / div;
533 }
534 }
535
536
537 sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
538 sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
539
540
541 while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB))
542 cpu_relax();
543
544 host->sclk = sclk;
545 host->mclk = hz;
546 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
547
548 INIT_MSG("================");
549 INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz / 1000, hclk / 1000, sclk / 1000);
550 INIT_MSG("================");
551
552 msdc_irq_restore(flags);
553}
554
555
556static void msdc_abort_data(struct msdc_host *host)
557{
558 void __iomem *base = host->base;
559 struct mmc_command *stop = host->mrq->stop;
560
561 ERR_MSG("Need to Abort.");
562
563 msdc_reset_hw(host);
564 msdc_clr_fifo();
565 msdc_clr_int();
566
567
568
569 if (stop) {
570 ERR_MSG("stop when abort CMD<%d>", stop->opcode);
571 (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
572 }
573
574
575
576
577}
578
579#if 0
580static void msdc_pin_config(struct msdc_host *host, int mode)
581{
582 struct msdc_hw *hw = host->hw;
583 void __iomem *base = host->base;
584 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
585
586
587 if (hw->flags & MSDC_WP_PIN_EN) {
588 if (hw->config_gpio_pin)
589 hw->config_gpio_pin(MSDC_WP_PIN, pull);
590 }
591
592 switch (mode) {
593 case MSDC_PIN_PULL_UP:
594
595
596 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
597 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
598 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
599 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
600 break;
601 case MSDC_PIN_PULL_DOWN:
602
603
604 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
605 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
606 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
607 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
608 break;
609 case MSDC_PIN_PULL_NONE:
610 default:
611
612
613 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
614 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
615 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
616 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
617 break;
618 }
619
620 N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
621 mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
622}
623
624void msdc_pin_reset(struct msdc_host *host, int mode)
625{
626 struct msdc_hw *hw = (struct msdc_hw *)host->hw;
627 void __iomem *base = host->base;
628 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
629
630
631 if (hw->flags & MSDC_RST_PIN_EN) {
632 if (hw->config_gpio_pin)
633 hw->config_gpio_pin(MSDC_RST_PIN, pull);
634
635 if (mode == MSDC_PIN_PULL_UP)
636 sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
637 else
638 sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
639 }
640}
641
642static void msdc_core_power(struct msdc_host *host, int on)
643{
644 N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
645 on ? "on" : "off", "core", host->core_power, on);
646
647 if (on && host->core_power == 0) {
648 msdc_vcore_on(host);
649 host->core_power = 1;
650 msleep(1);
651 } else if (!on && host->core_power == 1) {
652 msdc_vcore_off(host);
653 host->core_power = 0;
654 msleep(1);
655 }
656}
657
658static void msdc_host_power(struct msdc_host *host, int on)
659{
660 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
661
662 if (on) {
663
664 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
665 } else {
666 msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
667
668 }
669}
670
671static void msdc_card_power(struct msdc_host *host, int on)
672{
673 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
674
675 if (on) {
676 msdc_pin_config(host, MSDC_PIN_PULL_UP);
677
678 msleep(1);
679 } else {
680
681 msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
682 msleep(1);
683 }
684}
685
686static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
687{
688 N_MSG(CFG, "Set power mode(%d)", mode);
689
690 if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
691 msdc_host_power(host, 1);
692 msdc_card_power(host, 1);
693 } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
694 msdc_card_power(host, 0);
695 msdc_host_power(host, 0);
696 }
697 host->power_mode = mode;
698}
699#endif
700
701#ifdef CONFIG_PM
702
703
704
705
706static void msdc_pm(pm_message_t state, void *data)
707{
708 struct msdc_host *host = (struct msdc_host *)data;
709 int evt = state.event;
710
711 if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
712 INIT_MSG("USR_%s: suspend<%d> power<%d>",
713 evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
714 host->suspend, host->power_mode);
715 }
716
717 if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
718 if (host->suspend)
719 return;
720
721
722 if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
723 return;
724
725 host->suspend = 1;
726 host->pm_state = state;
727
728 } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
729 if (!host->suspend) {
730
731 return;
732 }
733
734
735 if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
736 ERR_MSG("PM Resume when in USR Suspend");
737 return;
738 }
739
740 host->suspend = 0;
741 host->pm_state = state;
742
743 }
744}
745#endif
746
747
748
749
750static unsigned int msdc_command_start(struct msdc_host *host,
751 struct mmc_command *cmd,
752 int tune,
753 unsigned long timeout)
754{
755 void __iomem *base = host->base;
756 u32 opcode = cmd->opcode;
757 u32 rawcmd;
758 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
759 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
760 MSDC_INT_ACMD19_DONE;
761
762 u32 resp;
763 unsigned long tmo;
764
765
766
767
768 if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) {
769 resp = RESP_R3;
770 } else if (opcode == MMC_SET_RELATIVE_ADDR) {
771 resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
772 } else if (opcode == MMC_FAST_IO) {
773 resp = RESP_R4;
774 } else if (opcode == MMC_GO_IRQ_STATE) {
775 resp = RESP_R5;
776 } else if (opcode == MMC_SELECT_CARD) {
777 resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
778 } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {
779 resp = RESP_R1;
780 } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {
781 resp = RESP_R1;
782 } else {
783 switch (mmc_resp_type(cmd)) {
784 case MMC_RSP_R1:
785 resp = RESP_R1;
786 break;
787 case MMC_RSP_R1B:
788 resp = RESP_R1B;
789 break;
790 case MMC_RSP_R2:
791 resp = RESP_R2;
792 break;
793 case MMC_RSP_R3:
794 resp = RESP_R3;
795 break;
796 case MMC_RSP_NONE:
797 default:
798 resp = RESP_NONE;
799 break;
800 }
801 }
802
803 cmd->error = 0;
804
805
806
807
808 rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
809
810 if (opcode == MMC_READ_MULTIPLE_BLOCK) {
811 rawcmd |= (2 << 11);
812 } else if (opcode == MMC_READ_SINGLE_BLOCK) {
813 rawcmd |= (1 << 11);
814 } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
815 rawcmd |= ((2 << 11) | (1 << 13));
816 } else if (opcode == MMC_WRITE_BLOCK) {
817 rawcmd |= ((1 << 11) | (1 << 13));
818 } else if (opcode == SD_IO_RW_EXTENDED) {
819 if (cmd->data->flags & MMC_DATA_WRITE)
820 rawcmd |= (1 << 13);
821 if (cmd->data->blocks > 1)
822 rawcmd |= (2 << 11);
823 else
824 rawcmd |= (1 << 11);
825 } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
826 rawcmd |= (1 << 14);
827 } else if ((opcode == SD_APP_SEND_SCR) ||
828 (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
829 (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
830 (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
831 (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
832 rawcmd |= (1 << 11);
833 } else if (opcode == MMC_STOP_TRANSMISSION) {
834 rawcmd |= (1 << 14);
835 rawcmd &= ~(0x0FFF << 16);
836 }
837
838 N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode, rawcmd, cmd->arg);
839
840 tmo = jiffies + timeout;
841
842 if (opcode == MMC_SEND_STATUS) {
843 for (;;) {
844 if (!sdc_is_cmd_busy())
845 break;
846
847 if (time_after(jiffies, tmo)) {
848 ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
849 cmd->error = -ETIMEDOUT;
850 msdc_reset_hw(host);
851 goto end;
852 }
853 }
854 } else {
855 for (;;) {
856 if (!sdc_is_busy())
857 break;
858 if (time_after(jiffies, tmo)) {
859 ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
860 cmd->error = -ETIMEDOUT;
861 msdc_reset_hw(host);
862 goto end;
863 }
864 }
865 }
866
867
868 host->cmd = cmd;
869 host->cmd_rsp = resp;
870
871 init_completion(&host->cmd_done);
872
873 sdr_set_bits(MSDC_INTEN, wints);
874 sdc_send_cmd(rawcmd, cmd->arg);
875
876end:
877 return cmd->error;
878}
879
880static unsigned int msdc_command_resp(struct msdc_host *host,
881 struct mmc_command *cmd,
882 int tune,
883 unsigned long timeout)
884 __must_hold(&host->lock)
885{
886 void __iomem *base = host->base;
887 u32 opcode = cmd->opcode;
888
889 u32 resp;
890 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
891 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
892 MSDC_INT_ACMD19_DONE;
893
894 resp = host->cmd_rsp;
895
896 BUG_ON(in_interrupt());
897
898
899
900 spin_unlock(&host->lock);
901 if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {
902 ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
903 cmd->error = -ETIMEDOUT;
904 msdc_reset_hw(host);
905 }
906 spin_lock(&host->lock);
907
908 sdr_clr_bits(MSDC_INTEN, wints);
909 host->cmd = NULL;
910
911
912#ifdef MT6575_SD_DEBUG
913 switch (resp) {
914 case RESP_NONE:
915 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
916 break;
917 case RESP_R2:
918 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
919 opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
920 cmd->resp[2], cmd->resp[3]);
921 break;
922 default:
923 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
924 opcode, cmd->error, resp, cmd->resp[0]);
925 if (cmd->error == 0) {
926 switch (resp) {
927 case RESP_R1:
928 case RESP_R1B:
929 msdc_dump_card_status(host, cmd->resp[0]);
930 break;
931 case RESP_R3:
932 msdc_dump_ocr_reg(host, cmd->resp[0]);
933 break;
934 case RESP_R5:
935 msdc_dump_io_resp(host, cmd->resp[0]);
936 break;
937 case RESP_R6:
938 msdc_dump_rca_resp(host, cmd->resp[0]);
939 break;
940 }
941 }
942 break;
943 }
944#endif
945
946
947
948 if (!tune)
949 return cmd->error;
950
951
952 if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) {
953 if (sdr_read32(SDC_CMD) & 0x1800) {
954 msdc_abort_data(host);
955 } else {
956
957 msdc_reset_hw(host);
958 msdc_clr_fifo();
959 msdc_clr_int();
960 }
961 cmd->error = msdc_tune_cmdrsp(host, cmd);
962 }
963
964
965
966
967
968
969
970 return cmd->error;
971}
972
973static unsigned int msdc_do_command(struct msdc_host *host,
974 struct mmc_command *cmd,
975 int tune,
976 unsigned long timeout)
977{
978 if (msdc_command_start(host, cmd, tune, timeout))
979 goto end;
980
981 if (msdc_command_resp(host, cmd, tune, timeout))
982 goto end;
983
984end:
985
986 N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
987 return cmd->error;
988}
989
990#if 0
991
992static void msdc_dma_resume(struct msdc_host *host)
993{
994 void __iomem *base = host->base;
995
996 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
997
998 N_MSG(DMA, "DMA resume");
999}
1000#endif
1001
1002static void msdc_dma_start(struct msdc_host *host)
1003{
1004 void __iomem *base = host->base;
1005 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1006
1007 sdr_set_bits(MSDC_INTEN, wints);
1008
1009 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1010
1011 N_MSG(DMA, "DMA start");
1012}
1013
1014static void msdc_dma_stop(struct msdc_host *host)
1015{
1016 void __iomem *base = host->base;
1017
1018 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1019
1020 N_MSG(DMA, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG));
1021
1022
1023 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
1024 while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1025 ;
1026
1027
1028 sdr_clr_bits(MSDC_INTEN, wints);
1029
1030 N_MSG(DMA, "DMA stop");
1031}
1032
1033
1034static u8 msdc_dma_calcs(u8 *buf, u32 len)
1035{
1036 u32 i, sum = 0;
1037
1038 for (i = 0; i < len; i++)
1039 sum += buf[i];
1040 return 0xFF - (u8)sum;
1041}
1042
1043
1044static void msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
1045{
1046 void __iomem *base = host->base;
1047
1048 u32 j, num;
1049 struct scatterlist *sg;
1050 struct gpd *gpd;
1051 struct bd *bd;
1052
1053 switch (dma->mode) {
1054 case MSDC_MODE_DMA_BASIC:
1055 BUG_ON(host->xfer_size > 65535);
1056 BUG_ON(dma->sglen != 1);
1057 sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
1058 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
1059
1060 if (ralink_soc == MT762X_SOC_MT7620A)
1061 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
1062
1063 else
1064 sdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg));
1065
1066 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1067 MSDC_BRUST_64B);
1068 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
1069 break;
1070 case MSDC_MODE_DMA_DESC:
1071
1072
1073 num = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
1074 BUG_ON(num != 1);
1075
1076 gpd = dma->gpd;
1077 bd = dma->bd;
1078
1079
1080
1081 gpd->hwo = 1;
1082 gpd->bdp = 1;
1083 gpd->chksum = 0;
1084 gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);
1085
1086
1087 for_each_sg(dma->sg, sg, dma->sglen, j) {
1088 bd[j].blkpad = 0;
1089 bd[j].dwpad = 0;
1090 bd[j].ptr = (void *)sg_dma_address(sg);
1091 bd[j].buflen = sg_dma_len(sg);
1092
1093 if (j == dma->sglen - 1)
1094 bd[j].eol = 1;
1095 else
1096 bd[j].eol = 0;
1097
1098 bd[j].chksum = 0;
1099 bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);
1100 }
1101
1102 sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
1103 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1104 MSDC_BRUST_64B);
1105 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
1106
1107 sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
1108 break;
1109
1110 default:
1111 break;
1112 }
1113
1114 N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1115 N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1116 N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1117
1118}
1119
1120static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
1121 struct scatterlist *sg, unsigned int sglen)
1122{
1123 BUG_ON(sglen > MAX_BD_NUM);
1124
1125 dma->sg = sg;
1126 dma->sglen = sglen;
1127
1128 dma->mode = MSDC_MODE_DMA_DESC;
1129
1130 N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen,
1131 host->xfer_size);
1132
1133 msdc_dma_config(host, dma);
1134}
1135
1136static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)
1137 __must_hold(&host->lock)
1138{
1139 struct msdc_host *host = mmc_priv(mmc);
1140 struct mmc_command *cmd;
1141 struct mmc_data *data;
1142 void __iomem *base = host->base;
1143
1144 int read = 1, send_type = 0;
1145
1146#define SND_DAT 0
1147#define SND_CMD 1
1148
1149 BUG_ON(mmc == NULL);
1150 BUG_ON(mrq == NULL);
1151
1152 host->error = 0;
1153
1154 cmd = mrq->cmd;
1155 data = mrq->cmd->data;
1156
1157#if 0
1158
1159 N_MSG(OPS, "enable clock!");
1160 msdc_ungate_clock(host->id);
1161
1162#endif
1163
1164 if (!data) {
1165 send_type = SND_CMD;
1166 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
1167 goto done;
1168 } else {
1169 BUG_ON(data->blksz > HOST_MAX_BLKSZ);
1170 send_type = SND_DAT;
1171
1172 data->error = 0;
1173 read = data->flags & MMC_DATA_READ ? 1 : 0;
1174 host->data = data;
1175 host->xfer_size = data->blocks * data->blksz;
1176 host->blksz = data->blksz;
1177
1178 if (read) {
1179 if ((host->timeout_ns != data->timeout_ns) ||
1180 (host->timeout_clks != data->timeout_clks)) {
1181 msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
1182 }
1183 }
1184
1185 sdr_write32(SDC_BLK_NUM, data->blocks);
1186
1187
1188 msdc_dma_on();
1189 init_completion(&host->xfer_done);
1190
1191
1192 if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
1193 goto done;
1194
1195 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,
1196 data->sg_len,
1197 mmc_get_dma_dir(data));
1198 msdc_dma_setup(host, &host->dma, data->sg,
1199 data->sg_count);
1200
1201
1202 if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
1203 goto done;
1204
1205
1206
1207
1208 msdc_dma_start(host);
1209
1210 spin_unlock(&host->lock);
1211 if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
1212 ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
1213 ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1214 ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
1215 ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1216 ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1217 data->error = -ETIMEDOUT;
1218
1219 msdc_reset_hw(host);
1220 msdc_clr_fifo();
1221 msdc_clr_int();
1222 }
1223 spin_lock(&host->lock);
1224 msdc_dma_stop(host);
1225
1226
1227 if (data->stop) {
1228 if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)
1229 goto done;
1230 }
1231 }
1232
1233done:
1234 if (data != NULL) {
1235 host->data = NULL;
1236 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1237 mmc_get_dma_dir(data));
1238 host->blksz = 0;
1239
1240#if 0
1241 if (host->hw->flags & MSDC_REMOVABLE && data->error) {
1242 msdc_abort_data(host);
1243
1244 }
1245#endif
1246
1247 N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd->opcode, (dma ? "dma" : "pio"),
1248 (read ? "read " : "write"), data->blksz, data->blocks, data->error);
1249 }
1250
1251#if 0
1252#if 1
1253
1254 if (send_type == SND_CMD) {
1255 if (cmd->opcode == MMC_SEND_STATUS) {
1256 if ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) {
1257 N_MSG(OPS, "disable clock, CMD13 IDLE");
1258 msdc_gate_clock(host->id);
1259 }
1260 } else {
1261 N_MSG(OPS, "disable clock, CMD<%d>", cmd->opcode);
1262 msdc_gate_clock(host->id);
1263 }
1264 } else {
1265 if (read) {
1266 N_MSG(OPS, "disable clock!!! Read CMD<%d>", cmd->opcode);
1267 msdc_gate_clock(host->id);
1268 }
1269 }
1270
1271#else
1272 msdc_gate_clock(host->id);
1273#endif
1274#endif
1275
1276 if (mrq->cmd->error)
1277 host->error = 0x001;
1278 if (mrq->data && mrq->data->error)
1279 host->error |= 0x010;
1280 if (mrq->stop && mrq->stop->error)
1281 host->error |= 0x100;
1282
1283
1284
1285 return host->error;
1286}
1287
1288static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
1289{
1290 struct mmc_command cmd;
1291 struct mmc_request mrq;
1292 u32 err;
1293
1294 memset(&cmd, 0, sizeof(struct mmc_command));
1295 cmd.opcode = MMC_APP_CMD;
1296#if 0
1297 cmd.arg = mmc->card->rca << 16;
1298#else
1299 cmd.arg = host->app_cmd_arg;
1300#endif
1301 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
1302
1303 memset(&mrq, 0, sizeof(struct mmc_request));
1304 mrq.cmd = &cmd; cmd.mrq = &mrq;
1305 cmd.data = NULL;
1306
1307 err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
1308 return err;
1309}
1310
1311static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)
1312{
1313 int result = -1;
1314 void __iomem *base = host->base;
1315 u32 rsmpl, cur_rsmpl, orig_rsmpl;
1316 u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
1317 u32 skip = 1;
1318
1319
1320
1321
1322
1323
1324
1325 sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl);
1326 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, &orig_rrdly);
1327
1328 rrdly = 0;
1329 do {
1330 for (rsmpl = 0; rsmpl < 2; rsmpl++) {
1331
1332 cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
1333 if (skip == 1) {
1334 skip = 0;
1335 continue;
1336 }
1337 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
1338
1339 if (host->app_cmd) {
1340 result = msdc_app_cmd(host->mmc, host);
1341 if (result) {
1342 ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
1343 host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
1344 continue;
1345 }
1346 }
1347 result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT);
1348 ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
1349 (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
1350
1351 if (result == 0)
1352 return 0;
1353 if (result != -EIO) {
1354 ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
1355 return result;
1356 }
1357
1358
1359 if (sdr_read32(SDC_CMD) & 0x1800) {
1360 msdc_abort_data(host);
1361 }
1362 }
1363
1364
1365 cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
1366 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
1367 } while (++rrdly < 32);
1368
1369 return result;
1370}
1371
1372
1373static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
1374{
1375 struct msdc_host *host = mmc_priv(mmc);
1376 void __iomem *base = host->base;
1377 u32 ddr = 0;
1378 u32 dcrc = 0;
1379 u32 rxdly, cur_rxdly0, cur_rxdly1;
1380 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1381 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1382 u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
1383 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1384 u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
1385 int result = -1;
1386 u32 skip = 1;
1387
1388 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1389
1390
1391 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1392
1393 rxdly = 0;
1394 do {
1395 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1396 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1397 if (skip == 1) {
1398 skip = 0;
1399 continue;
1400 }
1401 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1402
1403 if (host->app_cmd) {
1404 result = msdc_app_cmd(host->mmc, host);
1405 if (result) {
1406 ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
1407 continue;
1408 }
1409 }
1410 result = msdc_do_request(mmc, mrq);
1411
1412 sdr_get_field(SDC_DCRC_STS,
1413 SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG,
1414 &dcrc);
1415 if (!ddr)
1416 dcrc &= ~SDC_DCRC_STS_NEG;
1417 ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
1418 (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
1419 sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
1420
1421
1422 if (result == 0 && dcrc == 0) {
1423 goto done;
1424 } else {
1425
1426 if (mrq->data->error != 0 &&
1427 mrq->data->error != -EIO) {
1428 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1429 result, mrq->cmd->error, mrq->data->error);
1430 goto done;
1431 }
1432 }
1433 }
1434
1435 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1436 cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
1437
1438
1439 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1440 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1441 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1442 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1443 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1444 orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
1445 orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
1446 orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
1447 orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
1448 } else {
1449 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1450 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1451 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1452 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1453 orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
1454 orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
1455 orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
1456 orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
1457 }
1458
1459 if (ddr) {
1460 cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1461 cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1462 cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1463 cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1464 } else {
1465 cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1466 cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1467 cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1468 cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1469 }
1470 cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
1471 cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
1472 cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
1473 cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
1474
1475 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1476 cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
1477
1478 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1479 sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
1480
1481 } while (++rxdly < 32);
1482
1483done:
1484 return result;
1485}
1486
1487static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)
1488{
1489 struct msdc_host *host = mmc_priv(mmc);
1490 void __iomem *base = host->base;
1491
1492 u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
1493 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1494 u32 rxdly, cur_rxdly0;
1495 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1496 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1497 int result = -1;
1498 u32 skip = 1;
1499
1500
1501
1502 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, &orig_wrrdly);
1503 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1504
1505
1506 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1507 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1508
1509
1510 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1511 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1512 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1513 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1514 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1515 } else {
1516 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1517 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1518 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1519 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1520 }
1521
1522 rxdly = 0;
1523 do {
1524 wrrdly = 0;
1525 do {
1526 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1527 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1528 if (skip == 1) {
1529 skip = 0;
1530 continue;
1531 }
1532 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1533
1534 if (host->app_cmd) {
1535 result = msdc_app_cmd(host->mmc, host);
1536 if (result) {
1537 ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
1538 continue;
1539 }
1540 }
1541 result = msdc_do_request(mmc, mrq);
1542
1543 ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
1544 result == 0 ? "PASS" : "FAIL",
1545 cur_dsmpl, cur_wrrdly, cur_rxdly0);
1546
1547 if (result == 0) {
1548 goto done;
1549 } else {
1550
1551 if (mrq->data->error != -EIO) {
1552 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1553 result, mrq->cmd->error, mrq->data->error);
1554 goto done;
1555 }
1556 }
1557 }
1558 cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
1559 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
1560 } while (++wrrdly < 32);
1561
1562 cur_dat0 = (orig_dat0 + rxdly) % 32;
1563 cur_dat1 = orig_dat1;
1564 cur_dat2 = orig_dat2;
1565 cur_dat3 = orig_dat3;
1566
1567 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1568 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1569 } while (++rxdly < 32);
1570
1571done:
1572 return result;
1573}
1574
1575static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
1576{
1577 struct mmc_command cmd;
1578 struct mmc_request mrq;
1579 u32 err;
1580
1581 memset(&cmd, 0, sizeof(struct mmc_command));
1582 cmd.opcode = MMC_SEND_STATUS;
1583 if (mmc->card) {
1584 cmd.arg = mmc->card->rca << 16;
1585 } else {
1586 ERR_MSG("cmd13 mmc card is null");
1587 cmd.arg = host->app_cmd_arg;
1588 }
1589 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
1590
1591 memset(&mrq, 0, sizeof(struct mmc_request));
1592 mrq.cmd = &cmd; cmd.mrq = &mrq;
1593 cmd.data = NULL;
1594
1595 err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
1596
1597 if (status)
1598 *status = cmd.resp[0];
1599
1600 return err;
1601}
1602
1603static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
1604{
1605 u32 err = 0;
1606 u32 status = 0;
1607
1608 do {
1609 err = msdc_get_card_status(mmc, host, &status);
1610 if (err)
1611 return err;
1612
1613 ERR_MSG("cmd<13> resp<0x%x>", status);
1614 } while (R1_CURRENT_STATE(status) == 7);
1615
1616 return err;
1617}
1618
1619
1620static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
1621{
1622 struct msdc_host *host = mmc_priv(mmc);
1623 struct mmc_command *cmd;
1624 struct mmc_data *data;
1625
1626 int ret = 0, read;
1627
1628 cmd = mrq->cmd;
1629 data = mrq->cmd->data;
1630
1631 read = data->flags & MMC_DATA_READ ? 1 : 0;
1632
1633 if (read) {
1634 if (data->error == -EIO)
1635 ret = msdc_tune_bread(mmc, mrq);
1636 } else {
1637 ret = msdc_check_busy(mmc, host);
1638 if (ret) {
1639 ERR_MSG("XXX cmd13 wait program done failed");
1640 return ret;
1641 }
1642
1643
1644 ret = msdc_tune_bwrite(mmc, mrq);
1645 }
1646
1647 return ret;
1648}
1649
1650
1651static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1652{
1653 struct msdc_host *host = mmc_priv(mmc);
1654
1655
1656#if 0
1657 u32 old_H32, old_L32, new_H32, new_L32;
1658 u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
1659#endif
1660
1661 WARN_ON(host->mrq);
1662
1663
1664 spin_lock(&host->lock);
1665#if 0
1666 if (sdio_pro_enable) {
1667 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53)
1668 GPT_GetCounter64(&old_L32, &old_H32);
1669 }
1670#endif
1671
1672 host->mrq = mrq;
1673
1674 if (msdc_do_request(mmc, mrq)) {
1675 if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)
1676 msdc_tune_request(mmc, mrq);
1677 }
1678
1679
1680 if (mrq->cmd->opcode == MMC_APP_CMD) {
1681 host->app_cmd = 1;
1682 host->app_cmd_arg = mrq->cmd->arg;
1683 } else {
1684 host->app_cmd = 0;
1685
1686 }
1687
1688 host->mrq = NULL;
1689
1690#if 0
1691
1692 if (sdio_pro_enable) {
1693 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
1694 GPT_GetCounter64(&new_L32, &new_H32);
1695 ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
1696
1697 opcode = mrq->cmd->opcode;
1698 if (mrq->cmd->data) {
1699 sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
1700 bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0;
1701 } else {
1702 bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
1703 }
1704
1705 if (!mrq->cmd->error)
1706 msdc_performance(opcode, sizes, bRx, ticks);
1707 }
1708 }
1709#endif
1710 spin_unlock(&host->lock);
1711
1712 mmc_request_done(mmc, mrq);
1713
1714 return;
1715}
1716
1717
1718static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1719{
1720 void __iomem *base = host->base;
1721 u32 val = sdr_read32(SDC_CFG);
1722
1723 val &= ~SDC_CFG_BUSWIDTH;
1724
1725 switch (width) {
1726 default:
1727 case MMC_BUS_WIDTH_1:
1728 width = 1;
1729 val |= (MSDC_BUS_1BITS << 16);
1730 break;
1731 case MMC_BUS_WIDTH_4:
1732 val |= (MSDC_BUS_4BITS << 16);
1733 break;
1734 case MMC_BUS_WIDTH_8:
1735 val |= (MSDC_BUS_8BITS << 16);
1736 break;
1737 }
1738
1739 sdr_write32(SDC_CFG, val);
1740
1741 N_MSG(CFG, "Bus Width = %d", width);
1742}
1743
1744
1745static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1746{
1747 struct msdc_host *host = mmc_priv(mmc);
1748 void __iomem *base = host->base;
1749 u32 ddr = 0;
1750
1751#ifdef MT6575_SD_DEBUG
1752 static char *vdd[] = {
1753 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
1754 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
1755 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
1756 "3.40v", "3.50v", "3.60v"
1757 };
1758 static char *power_mode[] = {
1759 "OFF", "UP", "ON"
1760 };
1761 static char *bus_mode[] = {
1762 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
1763 };
1764 static char *timing[] = {
1765 "LEGACY", "MMC_HS", "SD_HS"
1766 };
1767
1768 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
1769 ios->clock / 1000, bus_mode[ios->bus_mode],
1770 (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
1771 power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
1772#endif
1773
1774 msdc_set_buswidth(host, ios->bus_width);
1775
1776
1777 switch (ios->power_mode) {
1778 case MMC_POWER_OFF:
1779 case MMC_POWER_UP:
1780
1781 break;
1782 case MMC_POWER_ON:
1783 host->power_mode = MMC_POWER_ON;
1784 break;
1785 default:
1786 break;
1787 }
1788
1789
1790 if (host->mclk != ios->clock) {
1791 if (ios->clock > 25000000) {
1792
1793 INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING);
1794 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL,
1795 MSDC_SMPL_FALLING);
1796 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
1797 MSDC_SMPL_FALLING);
1798
1799 } else {
1800 sdr_write32(MSDC_IOCON, 0x00000000);
1801
1802 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);
1803 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
1804
1805 sdr_write32(MSDC_PAD_TUNE, 0x84101010);
1806 }
1807 msdc_set_mclk(host, ddr, ios->clock);
1808 }
1809}
1810
1811
1812static int msdc_ops_get_ro(struct mmc_host *mmc)
1813{
1814 struct msdc_host *host = mmc_priv(mmc);
1815 void __iomem *base = host->base;
1816 unsigned long flags;
1817 int ro = 0;
1818
1819 if (host->hw->flags & MSDC_WP_PIN_EN) {
1820 spin_lock_irqsave(&host->lock, flags);
1821 ro = (sdr_read32(MSDC_PS) >> 31);
1822 spin_unlock_irqrestore(&host->lock, flags);
1823 }
1824 return ro;
1825}
1826
1827
1828static int msdc_ops_get_cd(struct mmc_host *mmc)
1829{
1830 struct msdc_host *host = mmc_priv(mmc);
1831 void __iomem *base = host->base;
1832 unsigned long flags;
1833 int present = 1;
1834
1835
1836 if (!(host->hw->flags & MSDC_REMOVABLE)) {
1837
1838#if 1
1839 host->card_inserted = 1;
1840 return 1;
1841#else
1842 host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
1843 INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
1844 return host->card_inserted;
1845#endif
1846 }
1847
1848
1849 if (host->hw->flags & MSDC_CD_PIN_EN) {
1850 spin_lock_irqsave(&host->lock, flags);
1851#if 0
1852 present = host->card_inserted;
1853#else
1854
1855 if (cd_active_low)
1856 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
1857 else
1858 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
1859 host->card_inserted = present;
1860#endif
1861 spin_unlock_irqrestore(&host->lock, flags);
1862 } else {
1863 present = 0;
1864 }
1865
1866 INIT_MSG("ops_get_cd return<%d>", present);
1867 return present;
1868}
1869
1870static struct mmc_host_ops mt_msdc_ops = {
1871 .request = msdc_ops_request,
1872 .set_ios = msdc_ops_set_ios,
1873 .get_ro = msdc_ops_get_ro,
1874 .get_cd = msdc_ops_get_cd,
1875};
1876
1877
1878
1879
1880static irqreturn_t msdc_irq(int irq, void *dev_id)
1881{
1882 struct msdc_host *host = (struct msdc_host *)dev_id;
1883 struct mmc_data *data = host->data;
1884 struct mmc_command *cmd = host->cmd;
1885 void __iomem *base = host->base;
1886
1887 u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
1888 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
1889 MSDC_INT_ACMD19_DONE;
1890 u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;
1891
1892 u32 intsts = sdr_read32(MSDC_INT);
1893 u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
1894
1895 sdr_write32(MSDC_INT, intsts);
1896
1897
1898
1899 if (intsts & MSDC_INT_CDSC) {
1900 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
1901 return IRQ_HANDLED;
1902 IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
1903 schedule_delayed_work(&host->card_delaywork, HZ);
1904
1905 }
1906
1907
1908 if (intsts & MSDC_INT_SDIOIRQ) {
1909 IRQ_MSG("XXX MSDC_INT_SDIOIRQ");
1910
1911 }
1912
1913
1914 if (data != NULL) {
1915 if (inten & MSDC_INT_XFER_COMPL) {
1916 data->bytes_xfered = host->xfer_size;
1917 complete(&host->xfer_done);
1918 }
1919
1920 if (intsts & datsts) {
1921
1922 msdc_reset_hw(host);
1923 msdc_clr_fifo();
1924 msdc_clr_int();
1925
1926 if (intsts & MSDC_INT_DATTMO) {
1927 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
1928 data->error = -ETIMEDOUT;
1929 } else if (intsts & MSDC_INT_DATCRCERR) {
1930 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
1931 data->error = -EIO;
1932 }
1933
1934
1935 complete(&host->xfer_done);
1936 }
1937 }
1938
1939
1940 if ((cmd != NULL) && (intsts & cmdsts)) {
1941 if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
1942 (intsts & MSDC_INT_ACMD19_DONE)) {
1943 u32 *rsp = &cmd->resp[0];
1944
1945 switch (host->cmd_rsp) {
1946 case RESP_NONE:
1947 break;
1948 case RESP_R2:
1949 *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
1950 *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
1951 break;
1952 default:
1953 if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))
1954 *rsp = sdr_read32(SDC_ACMD_RESP);
1955 else
1956 *rsp = sdr_read32(SDC_RESP0);
1957 break;
1958 }
1959 } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
1960 if (intsts & MSDC_INT_ACMDCRCERR)
1961 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd->opcode);
1962 else
1963 IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd->opcode);
1964 cmd->error = -EIO;
1965 } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
1966 if (intsts & MSDC_INT_ACMDTMO)
1967 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd->opcode);
1968 else
1969 IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode);
1970 cmd->error = -ETIMEDOUT;
1971 msdc_reset_hw(host);
1972 msdc_clr_fifo();
1973 msdc_clr_int();
1974 }
1975 complete(&host->cmd_done);
1976 }
1977
1978
1979 if (intsts & MSDC_INT_MMCIRQ)
1980 printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
1981
1982#ifdef MT6575_SD_DEBUG
1983 {
1984
1985 N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
1986 intsts,
1987 int_reg->mmcirq,
1988 int_reg->cdsc,
1989 int_reg->atocmdrdy,
1990 int_reg->atocmdtmo,
1991 int_reg->atocmdcrc,
1992 int_reg->atocmd19done);
1993 N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
1994 intsts,
1995 int_reg->sdioirq,
1996 int_reg->cmdrdy,
1997 int_reg->cmdtmo,
1998 int_reg->rspcrc,
1999 int_reg->csta);
2000 N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
2001 intsts,
2002 int_reg->xfercomp,
2003 int_reg->dxferdone,
2004 int_reg->dattmo,
2005 int_reg->datcrc,
2006 int_reg->dmaqempty);
2007 }
2008#endif
2009
2010 return IRQ_HANDLED;
2011}
2012
2013
2014
2015
2016
2017static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
2018{
2019 struct msdc_hw *hw = host->hw;
2020 void __iomem *base = host->base;
2021
2022
2023 if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
2024
2025
2026
2027
2028
2029 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2030 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2031 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2032 return;
2033 }
2034
2035 N_MSG(CFG, "CD IRQ Enable(%d)", enable);
2036
2037 if (enable) {
2038
2039
2040
2041
2042
2043
2044 if (hw->config_gpio_pin)
2045 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
2046
2047 sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
2048 sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
2049 sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2050 sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP);
2051 } else {
2052 if (hw->config_gpio_pin)
2053 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2054
2055 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2056 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2057 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2058
2059
2060
2061
2062
2063 }
2064}
2065
2066
2067static void msdc_init_hw(struct msdc_host *host)
2068{
2069 void __iomem *base = host->base;
2070
2071
2072#if 0
2073 msdc_vcore_on(host);
2074 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2075 msdc_select_clksrc(host, hw->clk_src);
2076 enable_clock(PERI_MSDC0_PDN + host->id, "SD");
2077 msdc_vdd_on(host);
2078#endif
2079
2080 sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
2081
2082
2083 msdc_reset_hw(host);
2084 msdc_clr_fifo();
2085
2086
2087 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2088
2089
2090 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2091 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2092
2093#if 1
2094
2095 sdr_write32(MSDC_PAD_CTL0, 0x00090000);
2096 sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
2097 sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
2098
2099 sdr_write32(MSDC_PAD_TUNE, 0x84101010);
2100
2101 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);
2102 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2103 sdr_write32(MSDC_IOCON, 0x00000000);
2104#if 0
2105 sdr_write32(MSDC_PATCH_BIT0, 0x003C000F);
2106#endif
2107
2108 if (sdr_read32(MSDC_ECO_VER) >= 4) {
2109 if (host->id == 1) {
2110 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
2111 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
2112
2113
2114 sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
2115 }
2116 }
2117#endif
2118
2119
2120
2121
2122
2123 sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
2124
2125
2126 sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
2127
2128
2129 sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
2130 sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
2131 sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
2132
2133#if 1
2134
2135 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4);
2136 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4);
2137 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);
2138 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);
2139 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);
2140 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);
2141#else
2142 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
2143 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
2144 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
2145 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
2146 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
2147 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
2148#endif
2149
2150
2151
2152
2153 sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
2154
2155
2156 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
2157
2158 msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
2159
2160 N_MSG(FUC, "init hardware done!");
2161}
2162
2163
2164static void msdc_deinit_hw(struct msdc_host *host)
2165{
2166 void __iomem *base = host->base;
2167
2168
2169 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2170 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2171
2172
2173 msdc_enable_cd_irq(host, 0);
2174
2175}
2176
2177
2178static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2179{
2180 struct gpd *gpd = dma->gpd;
2181 struct bd *bd = dma->bd;
2182 int i;
2183
2184
2185
2186
2187
2188 memset(gpd, 0, sizeof(struct gpd) * 2);
2189
2190 gpd->bdp = 1;
2191 gpd->ptr = (void *)dma->bd_addr;
2192 gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));
2193
2194 memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);
2195 for (i = 0; i < (MAX_BD_NUM - 1); i++)
2196 bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));
2197}
2198
2199static int msdc_drv_probe(struct platform_device *pdev)
2200{
2201 struct resource *res;
2202 __iomem void *base;
2203 struct mmc_host *mmc;
2204 struct msdc_host *host;
2205 struct msdc_hw *hw;
2206 int ret;
2207
2208 hw = &msdc0_hw;
2209
2210 if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
2211 msdc0_hw.flags |= MSDC_WP_PIN_EN;
2212
2213
2214 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2215 if (!mmc)
2216 return -ENOMEM;
2217
2218 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2219 base = devm_ioremap_resource(&pdev->dev, res);
2220 if (IS_ERR(base)) {
2221 ret = PTR_ERR(base);
2222 goto host_free;
2223 }
2224
2225
2226 mmc->ops = &mt_msdc_ops;
2227 mmc->f_min = HOST_MIN_MCLK;
2228 mmc->f_max = HOST_MAX_MCLK;
2229 mmc->ocr_avail = MSDC_OCR_AVAIL;
2230
2231 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
2232
2233
2234 mmc->caps |= MMC_CAP_4_BIT_DATA;
2235
2236 cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
2237
2238 if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll"))
2239 mmc->caps |= MMC_CAP_NEEDS_POLL;
2240
2241
2242 mmc->max_segs = MAX_HW_SGMTS;
2243
2244 mmc->max_seg_size = MAX_SGMT_SZ;
2245 mmc->max_blk_size = HOST_MAX_BLKSZ;
2246 mmc->max_req_size = MAX_REQ_SZ;
2247 mmc->max_blk_count = mmc->max_req_size;
2248
2249 host = mmc_priv(mmc);
2250 host->hw = hw;
2251 host->mmc = mmc;
2252 host->id = pdev->id;
2253 if (host->id < 0 || host->id >= 4)
2254 host->id = 0;
2255 host->error = 0;
2256
2257 host->irq = platform_get_irq(pdev, 0);
2258 if (host->irq < 0) {
2259 ret = -EINVAL;
2260 goto host_free;
2261 }
2262
2263 host->base = base;
2264 host->mclk = 0;
2265 host->hclk = hclks[hw->clk_src];
2266 host->sclk = 0;
2267 host->pm_state = PMSG_RESUME;
2268 host->suspend = 0;
2269 host->core_clkon = 0;
2270 host->card_clkon = 0;
2271 host->core_power = 0;
2272 host->power_mode = MMC_POWER_OFF;
2273
2274 host->timeout_ns = 0;
2275 host->timeout_clks = DEFAULT_DTOC * 65536;
2276
2277 host->mrq = NULL;
2278
2279
2280 mmc_dev(mmc)->dma_mask = NULL;
2281
2282
2283 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2284 MAX_GPD_NUM * sizeof(struct gpd),
2285 &host->dma.gpd_addr, GFP_KERNEL);
2286 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2287 MAX_BD_NUM * sizeof(struct bd),
2288 &host->dma.bd_addr, GFP_KERNEL);
2289 if (!host->dma.gpd || !host->dma.bd) {
2290 ret = -ENOMEM;
2291 goto release_mem;
2292 }
2293 msdc_init_gpd_bd(host, &host->dma);
2294
2295 INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
2296 spin_lock_init(&host->lock);
2297 msdc_init_hw(host);
2298
2299
2300
2301
2302
2303
2304
2305
2306 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,
2307 host);
2308 if (ret)
2309 goto release;
2310
2311 platform_set_drvdata(pdev, mmc);
2312
2313 ret = mmc_add_host(mmc);
2314 if (ret)
2315 goto release;
2316
2317
2318 if (hw->flags & MSDC_CD_PIN_EN) {
2319 msdc_enable_cd_irq(host, 1);
2320 } else {
2321 msdc_enable_cd_irq(host, 0);
2322 }
2323
2324 return 0;
2325
2326release:
2327 platform_set_drvdata(pdev, NULL);
2328 msdc_deinit_hw(host);
2329 cancel_delayed_work_sync(&host->card_delaywork);
2330
2331release_mem:
2332 if (host->dma.gpd)
2333 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2334 host->dma.gpd, host->dma.gpd_addr);
2335 if (host->dma.bd)
2336 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2337 host->dma.bd, host->dma.bd_addr);
2338host_free:
2339 mmc_free_host(mmc);
2340
2341 return ret;
2342}
2343
2344
2345static int msdc_drv_remove(struct platform_device *pdev)
2346{
2347 struct mmc_host *mmc;
2348 struct msdc_host *host;
2349
2350 mmc = platform_get_drvdata(pdev);
2351 BUG_ON(!mmc);
2352
2353 host = mmc_priv(mmc);
2354 BUG_ON(!host);
2355
2356 ERR_MSG("removed !!!");
2357
2358 platform_set_drvdata(pdev, NULL);
2359 mmc_remove_host(host->mmc);
2360 msdc_deinit_hw(host);
2361
2362 cancel_delayed_work_sync(&host->card_delaywork);
2363
2364 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2365 host->dma.gpd, host->dma.gpd_addr);
2366 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2367 host->dma.bd, host->dma.bd_addr);
2368
2369 mmc_free_host(host->mmc);
2370
2371 return 0;
2372}
2373
2374
2375#ifdef CONFIG_PM
2376
2377static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)
2378{
2379 struct mmc_host *mmc = platform_get_drvdata(pdev);
2380 if (mmc) {
2381 struct msdc_host *host = mmc_priv(mmc);
2382 msdc_pm(state, (void *)host);
2383 }
2384}
2385
2386static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
2387{
2388 if (state.event == PM_EVENT_SUSPEND)
2389 msdc_drv_pm(pdev, state);
2390 return 0;
2391}
2392
2393static int msdc_drv_resume(struct platform_device *pdev)
2394{
2395 struct pm_message state;
2396
2397 state.event = PM_EVENT_RESUME;
2398 msdc_drv_pm(pdev, state);
2399 return 0;
2400}
2401#endif
2402
2403static const struct of_device_id mt7620_sdhci_match[] = {
2404 { .compatible = "ralink,mt7620-sdhci" },
2405 {},
2406};
2407MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
2408
2409static struct platform_driver mt_msdc_driver = {
2410 .probe = msdc_drv_probe,
2411 .remove = msdc_drv_remove,
2412#ifdef CONFIG_PM
2413 .suspend = msdc_drv_suspend,
2414 .resume = msdc_drv_resume,
2415#endif
2416 .driver = {
2417 .name = DRV_NAME,
2418 .of_match_table = mt7620_sdhci_match,
2419 },
2420};
2421
2422
2423
2424
2425static int __init mt_msdc_init(void)
2426{
2427 int ret;
2428 u32 reg;
2429
2430
2431
2432 reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
2433 sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60), reg);
2434
2435 ret = platform_driver_register(&mt_msdc_driver);
2436 if (ret) {
2437 printk(KERN_ERR DRV_NAME ": Can't register driver");
2438 return ret;
2439 }
2440
2441#if defined(MT6575_SD_DEBUG)
2442 msdc_debug_proc_init();
2443#endif
2444 return 0;
2445}
2446
2447static void __exit mt_msdc_exit(void)
2448{
2449 platform_driver_unregister(&mt_msdc_driver);
2450}
2451
2452module_init(mt_msdc_init);
2453module_exit(mt_msdc_exit);
2454MODULE_LICENSE("GPL");
2455MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
2456MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
2457
