LXR linux/drivers/tty/serial/stm32-usart.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) Maxime Coquelin 2015
   4 * Copyright (C) STMicroelectronics SA 2017
   5 * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6 *           Gerald Baeza <gerald_baeza@yahoo.fr>
   7 */
   8
   9#define DRIVER_NAME "stm32-usart"
  10
  11struct stm32_usart_offsets {
  12        u8 cr1;
  13        u8 cr2;
  14        u8 cr3;
  15        u8 brr;
  16        u8 gtpr;
  17        u8 rtor;
  18        u8 rqr;
  19        u8 isr;
  20        u8 icr;
  21        u8 rdr;
  22        u8 tdr;
  23};
  24
  25struct stm32_usart_config {
  26        u8 uart_enable_bit; /* USART_CR1_UE */
  27        bool has_7bits_data;
  28        bool has_wakeup;
  29        bool has_fifo;
  30};
  31
  32struct stm32_usart_info {
  33        struct stm32_usart_offsets ofs;
  34        struct stm32_usart_config cfg;
  35};
  36
  37#define UNDEF_REG 0xff
  38
  39/* Register offsets */
  40struct stm32_usart_info stm32f4_info = {
  41        .ofs = {
  42                .isr    = 0x00,
  43                .rdr    = 0x04,
  44                .tdr    = 0x04,
  45                .brr    = 0x08,
  46                .cr1    = 0x0c,
  47                .cr2    = 0x10,
  48                .cr3    = 0x14,
  49                .gtpr   = 0x18,
  50                .rtor   = UNDEF_REG,
  51                .rqr    = UNDEF_REG,
  52                .icr    = UNDEF_REG,
  53        },
  54        .cfg = {
  55                .uart_enable_bit = 13,
  56                .has_7bits_data = false,
  57        }
  58};
  59
  60struct stm32_usart_info stm32f7_info = {
  61        .ofs = {
  62                .cr1    = 0x00,
  63                .cr2    = 0x04,
  64                .cr3    = 0x08,
  65                .brr    = 0x0c,
  66                .gtpr   = 0x10,
  67                .rtor   = 0x14,
  68                .rqr    = 0x18,
  69                .isr    = 0x1c,
  70                .icr    = 0x20,
  71                .rdr    = 0x24,
  72                .tdr    = 0x28,
  73        },
  74        .cfg = {
  75                .uart_enable_bit = 0,
  76                .has_7bits_data = true,
  77        }
  78};
  79
  80struct stm32_usart_info stm32h7_info = {
  81        .ofs = {
  82                .cr1    = 0x00,
  83                .cr2    = 0x04,
  84                .cr3    = 0x08,
  85                .brr    = 0x0c,
  86                .gtpr   = 0x10,
  87                .rtor   = 0x14,
  88                .rqr    = 0x18,
  89                .isr    = 0x1c,
  90                .icr    = 0x20,
  91                .rdr    = 0x24,
  92                .tdr    = 0x28,
  93        },
  94        .cfg = {
  95                .uart_enable_bit = 0,
  96                .has_7bits_data = true,
  97                .has_wakeup = true,
  98                .has_fifo = true,
  99        }
 100};
 101
 102/* USART_SR (F4) / USART_ISR (F7) */
 103#define USART_SR_PE             BIT(0)
 104#define USART_SR_FE             BIT(1)
 105#define USART_SR_NF             BIT(2)
 106#define USART_SR_ORE            BIT(3)
 107#define USART_SR_IDLE           BIT(4)
 108#define USART_SR_RXNE           BIT(5)
 109#define USART_SR_TC             BIT(6)
 110#define USART_SR_TXE            BIT(7)
 111#define USART_SR_LBD            BIT(8)
 112#define USART_SR_CTSIF          BIT(9)
 113#define USART_SR_CTS            BIT(10)         /* F7 */
 114#define USART_SR_RTOF           BIT(11)         /* F7 */
 115#define USART_SR_EOBF           BIT(12)         /* F7 */
 116#define USART_SR_ABRE           BIT(14)         /* F7 */
 117#define USART_SR_ABRF           BIT(15)         /* F7 */
 118#define USART_SR_BUSY           BIT(16)         /* F7 */
 119#define USART_SR_CMF            BIT(17)         /* F7 */
 120#define USART_SR_SBKF           BIT(18)         /* F7 */
 121#define USART_SR_WUF            BIT(20)         /* H7 */
 122#define USART_SR_TEACK          BIT(21)         /* F7 */
 123#define USART_SR_ERR_MASK       (USART_SR_LBD | USART_SR_ORE | \
 124                                 USART_SR_FE | USART_SR_PE)
 125/* Dummy bits */
 126#define USART_SR_DUMMY_RX       BIT(16)
 127
 128/* USART_ICR (F7) */
 129#define USART_CR_TC             BIT(6)
 130
 131/* USART_DR */
 132#define USART_DR_MASK           GENMASK(8, 0)
 133
 134/* USART_BRR */
 135#define USART_BRR_DIV_F_MASK    GENMASK(3, 0)
 136#define USART_BRR_DIV_M_MASK    GENMASK(15, 4)
 137#define USART_BRR_DIV_M_SHIFT   4
 138#define USART_BRR_04_R_SHIFT    1
 139
 140/* USART_CR1 */
 141#define USART_CR1_SBK           BIT(0)
 142#define USART_CR1_RWU           BIT(1)          /* F4 */
 143#define USART_CR1_UESM          BIT(1)          /* H7 */
 144#define USART_CR1_RE            BIT(2)
 145#define USART_CR1_TE            BIT(3)
 146#define USART_CR1_IDLEIE        BIT(4)
 147#define USART_CR1_RXNEIE        BIT(5)
 148#define USART_CR1_TCIE          BIT(6)
 149#define USART_CR1_TXEIE         BIT(7)
 150#define USART_CR1_PEIE          BIT(8)
 151#define USART_CR1_PS            BIT(9)
 152#define USART_CR1_PCE           BIT(10)
 153#define USART_CR1_WAKE          BIT(11)
 154#define USART_CR1_M             BIT(12)
 155#define USART_CR1_M0            BIT(12)         /* F7 */
 156#define USART_CR1_MME           BIT(13)         /* F7 */
 157#define USART_CR1_CMIE          BIT(14)         /* F7 */
 158#define USART_CR1_OVER8         BIT(15)
 159#define USART_CR1_DEDT_MASK     GENMASK(20, 16) /* F7 */
 160#define USART_CR1_DEAT_MASK     GENMASK(25, 21) /* F7 */
 161#define USART_CR1_RTOIE         BIT(26)         /* F7 */
 162#define USART_CR1_EOBIE         BIT(27)         /* F7 */
 163#define USART_CR1_M1            BIT(28)         /* F7 */
 164#define USART_CR1_IE_MASK       (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
 165#define USART_CR1_FIFOEN        BIT(29)         /* H7 */
 166#define USART_CR1_DEAT_SHIFT 21
 167#define USART_CR1_DEDT_SHIFT 16
 168
 169/* USART_CR2 */
 170#define USART_CR2_ADD_MASK      GENMASK(3, 0)   /* F4 */
 171#define USART_CR2_ADDM7         BIT(4)          /* F7 */
 172#define USART_CR2_LBDL          BIT(5)
 173#define USART_CR2_LBDIE         BIT(6)
 174#define USART_CR2_LBCL          BIT(8)
 175#define USART_CR2_CPHA          BIT(9)
 176#define USART_CR2_CPOL          BIT(10)
 177#define USART_CR2_CLKEN         BIT(11)
 178#define USART_CR2_STOP_2B       BIT(13)
 179#define USART_CR2_STOP_MASK     GENMASK(13, 12)
 180#define USART_CR2_LINEN         BIT(14)
 181#define USART_CR2_SWAP          BIT(15)         /* F7 */
 182#define USART_CR2_RXINV         BIT(16)         /* F7 */
 183#define USART_CR2_TXINV         BIT(17)         /* F7 */
 184#define USART_CR2_DATAINV       BIT(18)         /* F7 */
 185#define USART_CR2_MSBFIRST      BIT(19)         /* F7 */
 186#define USART_CR2_ABREN         BIT(20)         /* F7 */
 187#define USART_CR2_ABRMOD_MASK   GENMASK(22, 21) /* F7 */
 188#define USART_CR2_RTOEN         BIT(23)         /* F7 */
 189#define USART_CR2_ADD_F7_MASK   GENMASK(31, 24) /* F7 */
 190
 191/* USART_CR3 */
 192#define USART_CR3_EIE           BIT(0)
 193#define USART_CR3_IREN          BIT(1)
 194#define USART_CR3_IRLP          BIT(2)
 195#define USART_CR3_HDSEL         BIT(3)
 196#define USART_CR3_NACK          BIT(4)
 197#define USART_CR3_SCEN          BIT(5)
 198#define USART_CR3_DMAR          BIT(6)
 199#define USART_CR3_DMAT          BIT(7)
 200#define USART_CR3_RTSE          BIT(8)
 201#define USART_CR3_CTSE          BIT(9)
 202#define USART_CR3_CTSIE         BIT(10)
 203#define USART_CR3_ONEBIT        BIT(11)
 204#define USART_CR3_OVRDIS        BIT(12)         /* F7 */
 205#define USART_CR3_DDRE          BIT(13)         /* F7 */
 206#define USART_CR3_DEM           BIT(14)         /* F7 */
 207#define USART_CR3_DEP           BIT(15)         /* F7 */
 208#define USART_CR3_SCARCNT_MASK  GENMASK(19, 17) /* F7 */
 209#define USART_CR3_WUS_MASK      GENMASK(21, 20) /* H7 */
 210#define USART_CR3_WUS_START_BIT BIT(21)         /* H7 */
 211#define USART_CR3_WUFIE         BIT(22)         /* H7 */
 212
 213/* USART_GTPR */
 214#define USART_GTPR_PSC_MASK     GENMASK(7, 0)
 215#define USART_GTPR_GT_MASK      GENMASK(15, 8)
 216
 217/* USART_RTOR */
 218#define USART_RTOR_RTO_MASK     GENMASK(23, 0)  /* F7 */
 219#define USART_RTOR_BLEN_MASK    GENMASK(31, 24) /* F7 */
 220
 221/* USART_RQR */
 222#define USART_RQR_ABRRQ         BIT(0)          /* F7 */
 223#define USART_RQR_SBKRQ         BIT(1)          /* F7 */
 224#define USART_RQR_MMRQ          BIT(2)          /* F7 */
 225#define USART_RQR_RXFRQ         BIT(3)          /* F7 */
 226#define USART_RQR_TXFRQ         BIT(4)          /* F7 */
 227
 228/* USART_ICR */
 229#define USART_ICR_PECF          BIT(0)          /* F7 */
 230#define USART_ICR_FFECF         BIT(1)          /* F7 */
 231#define USART_ICR_NCF           BIT(2)          /* F7 */
 232#define USART_ICR_ORECF         BIT(3)          /* F7 */
 233#define USART_ICR_IDLECF        BIT(4)          /* F7 */
 234#define USART_ICR_TCCF          BIT(6)          /* F7 */
 235#define USART_ICR_LBDCF         BIT(8)          /* F7 */
 236#define USART_ICR_CTSCF         BIT(9)          /* F7 */
 237#define USART_ICR_RTOCF         BIT(11)         /* F7 */
 238#define USART_ICR_EOBCF         BIT(12)         /* F7 */
 239#define USART_ICR_CMCF          BIT(17)         /* F7 */
 240#define USART_ICR_WUCF          BIT(20)         /* H7 */
 241
 242#define STM32_SERIAL_NAME "ttySTM"
 243#define STM32_MAX_PORTS 8
 244
 245#define RX_BUF_L 200             /* dma rx buffer length     */
 246#define RX_BUF_P RX_BUF_L        /* dma rx buffer period     */
 247#define TX_BUF_L 200             /* dma tx buffer length     */
 248
 249struct stm32_port {
 250        struct uart_port port;
 251        struct clk *clk;
 252        struct stm32_usart_info *info;
 253        struct dma_chan *rx_ch;  /* dma rx channel            */
 254        dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
 255        unsigned char *rx_buf;   /* dma rx buffer cpu address */
 256        struct dma_chan *tx_ch;  /* dma tx channel            */
 257        dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
 258        unsigned char *tx_buf;   /* dma tx buffer cpu address */
 259        int last_res;
 260        bool tx_dma_busy;        /* dma tx busy               */
 261        bool hw_flow_control;
 262        bool fifoen;
 263        int wakeirq;
 264};
 265
 266static struct stm32_port stm32_ports[STM32_MAX_PORTS];
 267static struct uart_driver stm32_usart_driver;
 268