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16#ifndef __LINUX_MTD_RAWNAND_H
17#define __LINUX_MTD_RAWNAND_H
18
19#include <linux/wait.h>
20#include <linux/spinlock.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/flashchip.h>
23#include <linux/mtd/bbm.h>
24#include <linux/types.h>
25
26struct mtd_info;
27struct nand_flash_dev;
28struct device_node;
29
30
31int nand_scan_with_ids(struct mtd_info *mtd, int max_chips,
32 struct nand_flash_dev *ids);
33
34static inline int nand_scan(struct mtd_info *mtd, int max_chips)
35{
36 return nand_scan_with_ids(mtd, max_chips, NULL);
37}
38
39
40
41
42
43int nand_scan_ident(struct mtd_info *mtd, int max_chips,
44 struct nand_flash_dev *table);
45int nand_scan_tail(struct mtd_info *mtd);
46
47
48void nand_release(struct mtd_info *mtd);
49
50
51void nand_wait_ready(struct mtd_info *mtd);
52
53
54#define NAND_MAX_CHIPS 8
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61
62
63#define NAND_NCE 0x01
64
65#define NAND_CLE 0x02
66
67#define NAND_ALE 0x04
68
69#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71#define NAND_CTRL_CHANGE 0x80
72
73
74
75
76#define NAND_CMD_READ0 0
77#define NAND_CMD_READ1 1
78#define NAND_CMD_RNDOUT 5
79#define NAND_CMD_PAGEPROG 0x10
80#define NAND_CMD_READOOB 0x50
81#define NAND_CMD_ERASE1 0x60
82#define NAND_CMD_STATUS 0x70
83#define NAND_CMD_SEQIN 0x80
84#define NAND_CMD_RNDIN 0x85
85#define NAND_CMD_READID 0x90
86#define NAND_CMD_ERASE2 0xd0
87#define NAND_CMD_PARAM 0xec
88#define NAND_CMD_GET_FEATURES 0xee
89#define NAND_CMD_SET_FEATURES 0xef
90#define NAND_CMD_RESET 0xff
91
92
93#define NAND_CMD_READSTART 0x30
94#define NAND_CMD_RNDOUTSTART 0xE0
95#define NAND_CMD_CACHEDPROG 0x15
96
97#define NAND_CMD_NONE -1
98
99
100#define NAND_STATUS_FAIL 0x01
101#define NAND_STATUS_FAIL_N1 0x02
102#define NAND_STATUS_TRUE_READY 0x20
103#define NAND_STATUS_READY 0x40
104#define NAND_STATUS_WP 0x80
105
106#define NAND_DATA_IFACE_CHECK_ONLY -1
107
108
109
110
111typedef enum {
112 NAND_ECC_NONE,
113 NAND_ECC_SOFT,
114 NAND_ECC_HW,
115 NAND_ECC_HW_SYNDROME,
116 NAND_ECC_HW_OOB_FIRST,
117 NAND_ECC_ON_DIE,
118} nand_ecc_modes_t;
119
120enum nand_ecc_algo {
121 NAND_ECC_UNKNOWN,
122 NAND_ECC_HAMMING,
123 NAND_ECC_BCH,
124};
125
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129
130#define NAND_ECC_READ 0
131
132#define NAND_ECC_WRITE 1
133
134#define NAND_ECC_READSYN 2
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141
142#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
143#define NAND_ECC_MAXIMIZE BIT(1)
144
145
146#define NAND_GET_DEVICE 0x80
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153
154#define NAND_BUSWIDTH_16 0x00000002
155
156#define NAND_CACHEPRG 0x00000008
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161
162#define NAND_NEED_READRDY 0x00000100
163
164
165#define NAND_NO_SUBPAGE_WRITE 0x00000200
166
167
168#define NAND_BROKEN_XD 0x00000400
169
170
171#define NAND_ROM 0x00000800
172
173
174#define NAND_SUBPAGE_READ 0x00001000
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179
180#define NAND_NEED_SCRAMBLING 0x00002000
181
182
183#define NAND_ROW_ADDR_3 0x00004000
184
185
186#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
187
188
189#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
190#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
191#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
192
193
194
195#define NAND_SKIP_BBTSCAN 0x00010000
196
197#define NAND_SCAN_SILENT_NODEV 0x00040000
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204#define NAND_BUSWIDTH_AUTO 0x00080000
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209#define NAND_USE_BOUNCE_BUFFER 0x00100000
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219#define NAND_WAIT_TCCS 0x00200000
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223#define NAND_CONTROLLER_ALLOC 0x80000000
224
225
226#define NAND_CI_CHIPNR_MSK 0x03
227#define NAND_CI_CELLTYPE_MSK 0x0C
228#define NAND_CI_CELLTYPE_SHIFT 2
229
230
231struct nand_chip;
232
233
234#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
235#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
236
237
238#define ONFI_TIMING_MODE_0 (1 << 0)
239#define ONFI_TIMING_MODE_1 (1 << 1)
240#define ONFI_TIMING_MODE_2 (1 << 2)
241#define ONFI_TIMING_MODE_3 (1 << 3)
242#define ONFI_TIMING_MODE_4 (1 << 4)
243#define ONFI_TIMING_MODE_5 (1 << 5)
244#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
245
246
247#define ONFI_FEATURE_NUMBER 256
248#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
249
250
251#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
252#define ONFI_FEATURE_ON_DIE_ECC 0x90
253#define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
254
255
256#define ONFI_SUBFEATURE_PARAM_LEN 4
257
258
259#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
260
261struct nand_onfi_params {
262
263
264 u8 sig[4];
265 __le16 revision;
266 __le16 features;
267 __le16 opt_cmd;
268 u8 reserved0[2];
269 __le16 ext_param_page_length;
270 u8 num_of_param_pages;
271 u8 reserved1[17];
272
273
274 char manufacturer[12];
275 char model[20];
276 u8 jedec_id;
277 __le16 date_code;
278 u8 reserved2[13];
279
280
281 __le32 byte_per_page;
282 __le16 spare_bytes_per_page;
283 __le32 data_bytes_per_ppage;
284 __le16 spare_bytes_per_ppage;
285 __le32 pages_per_block;
286 __le32 blocks_per_lun;
287 u8 lun_count;
288 u8 addr_cycles;
289 u8 bits_per_cell;
290 __le16 bb_per_lun;
291 __le16 block_endurance;
292 u8 guaranteed_good_blocks;
293 __le16 guaranteed_block_endurance;
294 u8 programs_per_page;
295 u8 ppage_attr;
296 u8 ecc_bits;
297 u8 interleaved_bits;
298 u8 interleaved_ops;
299 u8 reserved3[13];
300
301
302 u8 io_pin_capacitance_max;
303 __le16 async_timing_mode;
304 __le16 program_cache_timing_mode;
305 __le16 t_prog;
306 __le16 t_bers;
307 __le16 t_r;
308 __le16 t_ccs;
309 __le16 src_sync_timing_mode;
310 u8 src_ssync_features;
311 __le16 clk_pin_capacitance_typ;
312 __le16 io_pin_capacitance_typ;
313 __le16 input_pin_capacitance_typ;
314 u8 input_pin_capacitance_max;
315 u8 driver_strength_support;
316 __le16 t_int_r;
317 __le16 t_adl;
318 u8 reserved4[8];
319
320
321 __le16 vendor_revision;
322 u8 vendor[88];
323
324 __le16 crc;
325} __packed;
326
327#define ONFI_CRC_BASE 0x4F4E
328
329
330struct onfi_ext_ecc_info {
331 u8 ecc_bits;
332 u8 codeword_size;
333 __le16 bb_per_lun;
334 __le16 block_endurance;
335 u8 reserved[2];
336} __packed;
337
338#define ONFI_SECTION_TYPE_0 0
339#define ONFI_SECTION_TYPE_1 1
340#define ONFI_SECTION_TYPE_2 2
341struct onfi_ext_section {
342 u8 type;
343 u8 length;
344} __packed;
345
346#define ONFI_EXT_SECTION_MAX 8
347
348
349struct onfi_ext_param_page {
350 __le16 crc;
351 u8 sig[4];
352 u8 reserved0[10];
353 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
354
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360
361} __packed;
362
363struct jedec_ecc_info {
364 u8 ecc_bits;
365 u8 codeword_size;
366 __le16 bb_per_lun;
367 __le16 block_endurance;
368 u8 reserved[2];
369} __packed;
370
371
372#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
373
374struct nand_jedec_params {
375
376
377 u8 sig[4];
378 __le16 revision;
379 __le16 features;
380 u8 opt_cmd[3];
381 __le16 sec_cmd;
382 u8 num_of_param_pages;
383 u8 reserved0[18];
384
385
386 char manufacturer[12];
387 char model[20];
388 u8 jedec_id[6];
389 u8 reserved1[10];
390
391
392 __le32 byte_per_page;
393 __le16 spare_bytes_per_page;
394 u8 reserved2[6];
395 __le32 pages_per_block;
396 __le32 blocks_per_lun;
397 u8 lun_count;
398 u8 addr_cycles;
399 u8 bits_per_cell;
400 u8 programs_per_page;
401 u8 multi_plane_addr;
402 u8 multi_plane_op_attr;
403 u8 reserved3[38];
404
405
406 __le16 async_sdr_speed_grade;
407 __le16 toggle_ddr_speed_grade;
408 __le16 sync_ddr_speed_grade;
409 u8 async_sdr_features;
410 u8 toggle_ddr_features;
411 u8 sync_ddr_features;
412 __le16 t_prog;
413 __le16 t_bers;
414 __le16 t_r;
415 __le16 t_r_multi_plane;
416 __le16 t_ccs;
417 __le16 io_pin_capacitance_typ;
418 __le16 input_pin_capacitance_typ;
419 __le16 clk_pin_capacitance_typ;
420 u8 driver_strength_support;
421 __le16 t_adl;
422 u8 reserved4[36];
423
424
425 u8 guaranteed_good_blocks;
426 __le16 guaranteed_block_endurance;
427 struct jedec_ecc_info ecc_info[4];
428 u8 reserved5[29];
429
430
431 u8 reserved6[148];
432
433
434 __le16 vendor_rev_num;
435 u8 reserved7[88];
436
437
438 __le16 crc;
439} __packed;
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452struct onfi_params {
453 int version;
454 u16 tPROG;
455 u16 tBERS;
456 u16 tR;
457 u16 tCCS;
458 u16 async_timing_mode;
459 u16 vendor_revision;
460 u8 vendor[88];
461};
462
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471struct nand_parameters {
472
473 char model[100];
474 bool supports_set_get_features;
475 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
476 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
477
478
479 struct onfi_params onfi;
480};
481
482
483#define NAND_MAX_ID_LEN 8
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490struct nand_id {
491 u8 data[NAND_MAX_ID_LEN];
492 int len;
493};
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503struct nand_hw_control {
504 spinlock_t lock;
505 struct nand_chip *active;
506 wait_queue_head_t wq;
507};
508
509static inline void nand_hw_control_init(struct nand_hw_control *nfc)
510{
511 nfc->active = NULL;
512 spin_lock_init(&nfc->lock);
513 init_waitqueue_head(&nfc->wq);
514}
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522struct nand_ecc_step_info {
523 int stepsize;
524 const int *strengths;
525 int nstrengths;
526};
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534struct nand_ecc_caps {
535 const struct nand_ecc_step_info *stepinfos;
536 int nstepinfos;
537 int (*calc_ecc_bytes)(int step_size, int strength);
538};
539
540
541#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
542static const int __name##_strengths[] = { __VA_ARGS__ }; \
543static const struct nand_ecc_step_info __name##_stepinfo = { \
544 .stepsize = __step, \
545 .strengths = __name##_strengths, \
546 .nstrengths = ARRAY_SIZE(__name##_strengths), \
547}; \
548static const struct nand_ecc_caps __name = { \
549 .stepinfos = &__name##_stepinfo, \
550 .nstepinfos = 1, \
551 .calc_ecc_bytes = __calc, \
552}
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607struct nand_ecc_ctrl {
608 nand_ecc_modes_t mode;
609 enum nand_ecc_algo algo;
610 int steps;
611 int size;
612 int bytes;
613 int total;
614 int strength;
615 int prepad;
616 int postpad;
617 unsigned int options;
618 void *priv;
619 u8 *calc_buf;
620 u8 *code_buf;
621 void (*hwctl)(struct mtd_info *mtd, int mode);
622 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
623 uint8_t *ecc_code);
624 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
625 uint8_t *calc_ecc);
626 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
627 uint8_t *buf, int oob_required, int page);
628 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
629 const uint8_t *buf, int oob_required, int page);
630 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
631 uint8_t *buf, int oob_required, int page);
632 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
633 uint32_t offs, uint32_t len, uint8_t *buf, int page);
634 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
635 uint32_t offset, uint32_t data_len,
636 const uint8_t *data_buf, int oob_required, int page);
637 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
638 const uint8_t *buf, int oob_required, int page);
639 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
640 int page);
641 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
642 int page);
643 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
644 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
645 int page);
646};
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699struct nand_sdr_timings {
700 u64 tBERS_max;
701 u32 tCCS_min;
702 u64 tPROG_max;
703 u64 tR_max;
704 u32 tALH_min;
705 u32 tADL_min;
706 u32 tALS_min;
707 u32 tAR_min;
708 u32 tCEA_max;
709 u32 tCEH_min;
710 u32 tCH_min;
711 u32 tCHZ_max;
712 u32 tCLH_min;
713 u32 tCLR_min;
714 u32 tCLS_min;
715 u32 tCOH_min;
716 u32 tCS_min;
717 u32 tDH_min;
718 u32 tDS_min;
719 u32 tFEAT_max;
720 u32 tIR_min;
721 u32 tITC_max;
722 u32 tRC_min;
723 u32 tREA_max;
724 u32 tREH_min;
725 u32 tRHOH_min;
726 u32 tRHW_min;
727 u32 tRHZ_max;
728 u32 tRLOH_min;
729 u32 tRP_min;
730 u32 tRR_min;
731 u64 tRST_max;
732 u32 tWB_max;
733 u32 tWC_min;
734 u32 tWH_min;
735 u32 tWHR_min;
736 u32 tWP_min;
737 u32 tWW_min;
738};
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744enum nand_data_interface_type {
745 NAND_SDR_IFACE,
746};
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754struct nand_data_interface {
755 enum nand_data_interface_type type;
756 union {
757 struct nand_sdr_timings sdr;
758 } timings;
759};
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764
765static inline const struct nand_sdr_timings *
766nand_get_sdr_timings(const struct nand_data_interface *conf)
767{
768 if (conf->type != NAND_SDR_IFACE)
769 return ERR_PTR(-EINVAL);
770
771 return &conf->timings.sdr;
772}
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781
782struct nand_manufacturer_ops {
783 void (*detect)(struct nand_chip *chip);
784 int (*init)(struct nand_chip *chip);
785 void (*cleanup)(struct nand_chip *chip);
786};
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792struct nand_op_cmd_instr {
793 u8 opcode;
794};
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801struct nand_op_addr_instr {
802 unsigned int naddrs;
803 const u8 *addrs;
804};
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818struct nand_op_data_instr {
819 unsigned int len;
820 union {
821 void *in;
822 const void *out;
823 } buf;
824 bool force_8bit;
825};
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831struct nand_op_waitrdy_instr {
832 unsigned int timeout_ms;
833};
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843enum nand_op_instr_type {
844 NAND_OP_CMD_INSTR,
845 NAND_OP_ADDR_INSTR,
846 NAND_OP_DATA_IN_INSTR,
847 NAND_OP_DATA_OUT_INSTR,
848 NAND_OP_WAITRDY_INSTR,
849};
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866struct nand_op_instr {
867 enum nand_op_instr_type type;
868 union {
869 struct nand_op_cmd_instr cmd;
870 struct nand_op_addr_instr addr;
871 struct nand_op_data_instr data;
872 struct nand_op_waitrdy_instr waitrdy;
873 } ctx;
874 unsigned int delay_ns;
875};
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890#define __DIVIDE(dividend, divisor) ({ \
891 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
892 DIV_ROUND_UP(dividend, divisor) : \
893 DIV_ROUND_UP_ULL(dividend, divisor)); \
894 })
895#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
896#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
897
898#define NAND_OP_CMD(id, ns) \
899 { \
900 .type = NAND_OP_CMD_INSTR, \
901 .ctx.cmd.opcode = id, \
902 .delay_ns = ns, \
903 }
904
905#define NAND_OP_ADDR(ncycles, cycles, ns) \
906 { \
907 .type = NAND_OP_ADDR_INSTR, \
908 .ctx.addr = { \
909 .naddrs = ncycles, \
910 .addrs = cycles, \
911 }, \
912 .delay_ns = ns, \
913 }
914
915#define NAND_OP_DATA_IN(l, b, ns) \
916 { \
917 .type = NAND_OP_DATA_IN_INSTR, \
918 .ctx.data = { \
919 .len = l, \
920 .buf.in = b, \
921 .force_8bit = false, \
922 }, \
923 .delay_ns = ns, \
924 }
925
926#define NAND_OP_DATA_OUT(l, b, ns) \
927 { \
928 .type = NAND_OP_DATA_OUT_INSTR, \
929 .ctx.data = { \
930 .len = l, \
931 .buf.out = b, \
932 .force_8bit = false, \
933 }, \
934 .delay_ns = ns, \
935 }
936
937#define NAND_OP_8BIT_DATA_IN(l, b, ns) \
938 { \
939 .type = NAND_OP_DATA_IN_INSTR, \
940 .ctx.data = { \
941 .len = l, \
942 .buf.in = b, \
943 .force_8bit = true, \
944 }, \
945 .delay_ns = ns, \
946 }
947
948#define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
949 { \
950 .type = NAND_OP_DATA_OUT_INSTR, \
951 .ctx.data = { \
952 .len = l, \
953 .buf.out = b, \
954 .force_8bit = true, \
955 }, \
956 .delay_ns = ns, \
957 }
958
959#define NAND_OP_WAIT_RDY(tout_ms, ns) \
960 { \
961 .type = NAND_OP_WAITRDY_INSTR, \
962 .ctx.waitrdy.timeout_ms = tout_ms, \
963 .delay_ns = ns, \
964 }
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982struct nand_subop {
983 const struct nand_op_instr *instrs;
984 unsigned int ninstrs;
985 unsigned int first_instr_start_off;
986 unsigned int last_instr_end_off;
987};
988
989int nand_subop_get_addr_start_off(const struct nand_subop *subop,
990 unsigned int op_id);
991int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
992 unsigned int op_id);
993int nand_subop_get_data_start_off(const struct nand_subop *subop,
994 unsigned int op_id);
995int nand_subop_get_data_len(const struct nand_subop *subop,
996 unsigned int op_id);
997
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1003struct nand_op_parser_addr_constraints {
1004 unsigned int maxcycles;
1005};
1006
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1011struct nand_op_parser_data_constraints {
1012 unsigned int maxlen;
1013};
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1023struct nand_op_parser_pattern_elem {
1024 enum nand_op_instr_type type;
1025 bool optional;
1026 union {
1027 struct nand_op_parser_addr_constraints addr;
1028 struct nand_op_parser_data_constraints data;
1029 } ctx;
1030};
1031
1032#define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
1033 { \
1034 .type = NAND_OP_CMD_INSTR, \
1035 .optional = _opt, \
1036 }
1037
1038#define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
1039 { \
1040 .type = NAND_OP_ADDR_INSTR, \
1041 .optional = _opt, \
1042 .ctx.addr.maxcycles = _maxcycles, \
1043 }
1044
1045#define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
1046 { \
1047 .type = NAND_OP_DATA_IN_INSTR, \
1048 .optional = _opt, \
1049 .ctx.data.maxlen = _maxlen, \
1050 }
1051
1052#define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
1053 { \
1054 .type = NAND_OP_DATA_OUT_INSTR, \
1055 .optional = _opt, \
1056 .ctx.data.maxlen = _maxlen, \
1057 }
1058
1059#define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
1060 { \
1061 .type = NAND_OP_WAITRDY_INSTR, \
1062 .optional = _opt, \
1063 }
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1083struct nand_op_parser_pattern {
1084 const struct nand_op_parser_pattern_elem *elems;
1085 unsigned int nelems;
1086 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
1087};
1088
1089#define NAND_OP_PARSER_PATTERN(_exec, ...) \
1090 { \
1091 .exec = _exec, \
1092 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
1093 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
1094 sizeof(struct nand_op_parser_pattern_elem), \
1095 }
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1111struct nand_op_parser {
1112 const struct nand_op_parser_pattern *patterns;
1113 unsigned int npatterns;
1114};
1115
1116#define NAND_OP_PARSER(...) \
1117 { \
1118 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
1119 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
1120 sizeof(struct nand_op_parser_pattern), \
1121 }
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1129
1130struct nand_operation {
1131 const struct nand_op_instr *instrs;
1132 unsigned int ninstrs;
1133};
1134
1135#define NAND_OPERATION(_instrs) \
1136 { \
1137 .instrs = _instrs, \
1138 .ninstrs = ARRAY_SIZE(_instrs), \
1139 }
1140
1141int nand_op_parser_exec_op(struct nand_chip *chip,
1142 const struct nand_op_parser *parser,
1143 const struct nand_operation *op, bool check_only);
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1252struct nand_chip {
1253 struct mtd_info mtd;
1254 void __iomem *IO_ADDR_R;
1255 void __iomem *IO_ADDR_W;
1256
1257 uint8_t (*read_byte)(struct mtd_info *mtd);
1258 u16 (*read_word)(struct mtd_info *mtd);
1259 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
1260 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1261 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1262 void (*select_chip)(struct mtd_info *mtd, int chip);
1263 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
1264 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
1265 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1266 int (*dev_ready)(struct mtd_info *mtd);
1267 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
1268 int page_addr);
1269 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
1270 int (*exec_op)(struct nand_chip *chip,
1271 const struct nand_operation *op,
1272 bool check_only);
1273 int (*erase)(struct mtd_info *mtd, int page);
1274 int (*scan_bbt)(struct mtd_info *mtd);
1275 int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip,
1276 int feature_addr, uint8_t *subfeature_para);
1277 int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip,
1278 int feature_addr, uint8_t *subfeature_para);
1279 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
1280 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
1281 const struct nand_data_interface *conf);
1282
1283 int chip_delay;
1284 unsigned int options;
1285 unsigned int bbt_options;
1286
1287 int page_shift;
1288 int phys_erase_shift;
1289 int bbt_erase_shift;
1290 int chip_shift;
1291 int numchips;
1292 uint64_t chipsize;
1293 int pagemask;
1294 u8 *data_buf;
1295 int pagebuf;
1296 unsigned int pagebuf_bitflips;
1297 int subpagesize;
1298 uint8_t bits_per_cell;
1299 uint16_t ecc_strength_ds;
1300 uint16_t ecc_step_ds;
1301 int onfi_timing_mode_default;
1302 int badblockpos;
1303 int badblockbits;
1304
1305 struct nand_id id;
1306 struct nand_parameters parameters;
1307 u16 max_bb_per_die;
1308 u32 blocks_per_die;
1309
1310 struct nand_data_interface data_interface;
1311
1312 int read_retries;
1313
1314 flstate_t state;
1315
1316 uint8_t *oob_poi;
1317 struct nand_hw_control *controller;
1318
1319 struct nand_ecc_ctrl ecc;
1320 unsigned long buf_align;
1321 struct nand_hw_control hwcontrol;
1322
1323 uint8_t *bbt;
1324 struct nand_bbt_descr *bbt_td;
1325 struct nand_bbt_descr *bbt_md;
1326
1327 struct nand_bbt_descr *badblock_pattern;
1328
1329 void *priv;
1330
1331 struct {
1332 const struct nand_manufacturer *desc;
1333 void *priv;
1334 } manufacturer;
1335};
1336
1337static inline int nand_exec_op(struct nand_chip *chip,
1338 const struct nand_operation *op)
1339{
1340 if (!chip->exec_op)
1341 return -ENOTSUPP;
1342
1343 return chip->exec_op(chip, op, false);
1344}
1345
1346extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1347extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1348
1349static inline void nand_set_flash_node(struct nand_chip *chip,
1350 struct device_node *np)
1351{
1352 mtd_set_of_node(&chip->mtd, np);
1353}
1354
1355static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1356{
1357 return mtd_get_of_node(&chip->mtd);
1358}
1359
1360static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1361{
1362 return container_of(mtd, struct nand_chip, mtd);
1363}
1364
1365static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1366{
1367 return &chip->mtd;
1368}
1369
1370static inline void *nand_get_controller_data(struct nand_chip *chip)
1371{
1372 return chip->priv;
1373}
1374
1375static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1376{
1377 chip->priv = priv;
1378}
1379
1380static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1381 void *priv)
1382{
1383 chip->manufacturer.priv = priv;
1384}
1385
1386static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1387{
1388 return chip->manufacturer.priv;
1389}
1390
1391
1392
1393
1394#define NAND_MFR_TOSHIBA 0x98
1395#define NAND_MFR_ESMT 0xc8
1396#define NAND_MFR_SAMSUNG 0xec
1397#define NAND_MFR_FUJITSU 0x04
1398#define NAND_MFR_NATIONAL 0x8f
1399#define NAND_MFR_RENESAS 0x07
1400#define NAND_MFR_STMICRO 0x20
1401#define NAND_MFR_HYNIX 0xad
1402#define NAND_MFR_MICRON 0x2c
1403#define NAND_MFR_AMD 0x01
1404#define NAND_MFR_MACRONIX 0xc2
1405#define NAND_MFR_EON 0x92
1406#define NAND_MFR_SANDISK 0x45
1407#define NAND_MFR_INTEL 0x89
1408#define NAND_MFR_ATO 0x9b
1409#define NAND_MFR_WINBOND 0xef
1410
1411
1412
1413
1414
1415
1416
1417#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1418 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1419 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1420
1421
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1430
1431#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1432 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1433 .options = (opts) }
1434
1435#define NAND_ECC_INFO(_strength, _step) \
1436 { .strength_ds = (_strength), .step_ds = (_step) }
1437#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1438#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1439
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1469struct nand_flash_dev {
1470 char *name;
1471 union {
1472 struct {
1473 uint8_t mfr_id;
1474 uint8_t dev_id;
1475 };
1476 uint8_t id[NAND_MAX_ID_LEN];
1477 };
1478 unsigned int pagesize;
1479 unsigned int chipsize;
1480 unsigned int erasesize;
1481 unsigned int options;
1482 uint16_t id_len;
1483 uint16_t oobsize;
1484 struct {
1485 uint16_t strength_ds;
1486 uint16_t step_ds;
1487 } ecc;
1488 int onfi_timing_mode_default;
1489};
1490
1491
1492
1493
1494
1495
1496
1497struct nand_manufacturer {
1498 int id;
1499 char *name;
1500 const struct nand_manufacturer_ops *ops;
1501};
1502
1503const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1504
1505static inline const char *
1506nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1507{
1508 return manufacturer ? manufacturer->name : "Unknown";
1509}
1510
1511extern struct nand_flash_dev nand_flash_ids[];
1512
1513extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1514extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1515extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1516extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1517extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1518extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1519
1520int nand_default_bbt(struct mtd_info *mtd);
1521int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1522int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1523int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1524int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1525 int allowbbt);
1526int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1527 size_t *retlen, uint8_t *buf);
1528
1529
1530
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1534
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1538
1539
1540struct platform_nand_chip {
1541 int nr_chips;
1542 int chip_offset;
1543 int nr_partitions;
1544 struct mtd_partition *partitions;
1545 int chip_delay;
1546 unsigned int options;
1547 unsigned int bbt_options;
1548 const char **part_probe_types;
1549};
1550
1551
1552struct platform_device;
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
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1564
1565
1566
1567
1568
1569
1570struct platform_nand_ctrl {
1571 int (*probe)(struct platform_device *pdev);
1572 void (*remove)(struct platform_device *pdev);
1573 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1574 int (*dev_ready)(struct mtd_info *mtd);
1575 void (*select_chip)(struct mtd_info *mtd, int chip);
1576 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1577 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1578 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1579 unsigned char (*read_byte)(struct mtd_info *mtd);
1580 void *priv;
1581};
1582
1583
1584
1585
1586
1587
1588struct platform_nand_data {
1589 struct platform_nand_chip chip;
1590 struct platform_nand_ctrl ctrl;
1591};
1592
1593
1594static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1595{
1596 if (!chip->parameters.onfi.version)
1597 return ONFI_TIMING_MODE_UNKNOWN;
1598
1599 return chip->parameters.onfi.async_timing_mode;
1600}
1601
1602int onfi_fill_data_interface(struct nand_chip *chip,
1603 enum nand_data_interface_type type,
1604 int timing_mode);
1605
1606
1607
1608
1609
1610
1611static inline bool nand_is_slc(struct nand_chip *chip)
1612{
1613 WARN(chip->bits_per_cell == 0,
1614 "chip->bits_per_cell is used uninitialized\n");
1615 return chip->bits_per_cell == 1;
1616}
1617
1618
1619
1620
1621
1622static inline int nand_opcode_8bits(unsigned int command)
1623{
1624 switch (command) {
1625 case NAND_CMD_READID:
1626 case NAND_CMD_PARAM:
1627 case NAND_CMD_GET_FEATURES:
1628 case NAND_CMD_SET_FEATURES:
1629 return 1;
1630 default:
1631 break;
1632 }
1633 return 0;
1634}
1635
1636
1637const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1638
1639int nand_check_erased_ecc_chunk(void *data, int datalen,
1640 void *ecc, int ecclen,
1641 void *extraoob, int extraooblen,
1642 int threshold);
1643
1644int nand_check_ecc_caps(struct nand_chip *chip,
1645 const struct nand_ecc_caps *caps, int oobavail);
1646
1647int nand_match_ecc_req(struct nand_chip *chip,
1648 const struct nand_ecc_caps *caps, int oobavail);
1649
1650int nand_maximize_ecc(struct nand_chip *chip,
1651 const struct nand_ecc_caps *caps, int oobavail);
1652
1653
1654int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1655
1656
1657int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1658 int page);
1659
1660
1661int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1662
1663
1664int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1665 int page);
1666
1667
1668int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1669int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1670
1671int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1672 int addr, u8 *subfeature_param);
1673
1674
1675int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1676 uint8_t *buf, int oob_required, int page);
1677
1678
1679int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1680 const uint8_t *buf, int oob_required, int page);
1681
1682
1683int nand_reset(struct nand_chip *chip, int chipnr);
1684
1685
1686int nand_reset_op(struct nand_chip *chip);
1687int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1688 unsigned int len);
1689int nand_status_op(struct nand_chip *chip, u8 *status);
1690int nand_exit_status_op(struct nand_chip *chip);
1691int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1692int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1693 unsigned int offset_in_page, void *buf, unsigned int len);
1694int nand_change_read_column_op(struct nand_chip *chip,
1695 unsigned int offset_in_page, void *buf,
1696 unsigned int len, bool force_8bit);
1697int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1698 unsigned int offset_in_page, void *buf, unsigned int len);
1699int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1700 unsigned int offset_in_page, const void *buf,
1701 unsigned int len);
1702int nand_prog_page_end_op(struct nand_chip *chip);
1703int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1704 unsigned int offset_in_page, const void *buf,
1705 unsigned int len);
1706int nand_change_write_column_op(struct nand_chip *chip,
1707 unsigned int offset_in_page, const void *buf,
1708 unsigned int len, bool force_8bit);
1709int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1710 bool force_8bit);
1711int nand_write_data_op(struct nand_chip *chip, const void *buf,
1712 unsigned int len, bool force_8bit);
1713
1714
1715void nand_cleanup(struct nand_chip *chip);
1716
1717
1718void nand_decode_ext_id(struct nand_chip *chip);
1719
1720
1721
1722
1723
1724int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1725
1726#endif
1727