1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#ifndef __MSND_H
16#define __MSND_H
17
18#define DEFSAMPLERATE 44100
19#define DEFSAMPLESIZE SNDRV_PCM_FORMAT_S16
20#define DEFCHANNELS 1
21
22#define SRAM_BANK_SIZE 0x8000
23#define SRAM_CNTL_START 0x7F00
24#define SMA_STRUCT_START 0x7F40
25
26#define DSP_BASE_ADDR 0x4000
27#define DSP_BANK_BASE 0x4000
28
29#define AGND 0x01
30#define SIGNAL 0x02
31
32#define EXT_DSP_BIT_DCAL 0x0001
33#define EXT_DSP_BIT_MIDI_CON 0x0002
34
35#define BUFFSIZE 0x8000
36#define HOSTQ_SIZE 0x40
37
38#define DAP_BUFF_SIZE 0x2400
39
40#define DAPQ_STRUCT_SIZE 0x10
41#define DARQ_STRUCT_SIZE 0x10
42#define DAPQ_BUFF_SIZE (3 * 0x10)
43#define DARQ_BUFF_SIZE (3 * 0x10)
44#define MODQ_BUFF_SIZE 0x400
45
46#define DAPQ_DATA_BUFF 0x6C00
47#define DARQ_DATA_BUFF 0x6C30
48#define MODQ_DATA_BUFF 0x6C60
49#define MIDQ_DATA_BUFF 0x7060
50
51#define DAPQ_OFFSET SRAM_CNTL_START
52#define DARQ_OFFSET (SRAM_CNTL_START + 0x08)
53#define MODQ_OFFSET (SRAM_CNTL_START + 0x10)
54#define MIDQ_OFFSET (SRAM_CNTL_START + 0x18)
55#define DSPQ_OFFSET (SRAM_CNTL_START + 0x20)
56
57#define HP_ICR 0x00
58#define HP_CVR 0x01
59#define HP_ISR 0x02
60#define HP_IVR 0x03
61#define HP_NU 0x04
62#define HP_INFO 0x04
63#define HP_TXH 0x05
64#define HP_RXH 0x05
65#define HP_TXM 0x06
66#define HP_RXM 0x06
67#define HP_TXL 0x07
68#define HP_RXL 0x07
69
70#define HP_ICR_DEF 0x00
71#define HP_CVR_DEF 0x12
72#define HP_ISR_DEF 0x06
73#define HP_IVR_DEF 0x0f
74#define HP_NU_DEF 0x00
75
76#define HP_IRQM 0x09
77
78#define HPR_BLRC 0x08
79#define HPR_SPR1 0x09
80#define HPR_SPR2 0x0A
81#define HPR_TCL0 0x0B
82#define HPR_TCL1 0x0C
83#define HPR_TCL2 0x0D
84#define HPR_TCL3 0x0E
85#define HPR_TCL4 0x0F
86
87#define HPICR_INIT 0x80
88#define HPICR_HM1 0x40
89#define HPICR_HM0 0x20
90#define HPICR_HF1 0x10
91#define HPICR_HF0 0x08
92#define HPICR_TREQ 0x02
93#define HPICR_RREQ 0x01
94
95#define HPCVR_HC 0x80
96
97#define HPISR_HREQ 0x80
98#define HPISR_DMA 0x40
99#define HPISR_HF3 0x10
100#define HPISR_HF2 0x08
101#define HPISR_TRDY 0x04
102#define HPISR_TXDE 0x02
103#define HPISR_RXDF 0x01
104
105#define HPIO_290 0
106#define HPIO_260 1
107#define HPIO_250 2
108#define HPIO_240 3
109#define HPIO_230 4
110#define HPIO_220 5
111#define HPIO_210 6
112#define HPIO_3E0 7
113
114#define HPMEM_NONE 0
115#define HPMEM_B000 1
116#define HPMEM_C800 2
117#define HPMEM_D000 3
118#define HPMEM_D400 4
119#define HPMEM_D800 5
120#define HPMEM_E000 6
121#define HPMEM_E800 7
122
123#define HPIRQ_NONE 0
124#define HPIRQ_5 1
125#define HPIRQ_7 2
126#define HPIRQ_9 3
127#define HPIRQ_10 4
128#define HPIRQ_11 5
129#define HPIRQ_12 6
130#define HPIRQ_15 7
131
132#define HIMT_PLAY_DONE 0x00
133#define HIMT_RECORD_DONE 0x01
134#define HIMT_MIDI_EOS 0x02
135#define HIMT_MIDI_OUT 0x03
136
137#define HIMT_MIDI_IN_UCHAR 0x0E
138#define HIMT_DSP 0x0F
139
140#define HDEX_BASE 0x92
141#define HDEX_PLAY_START (0 + HDEX_BASE)
142#define HDEX_PLAY_STOP (1 + HDEX_BASE)
143#define HDEX_PLAY_PAUSE (2 + HDEX_BASE)
144#define HDEX_PLAY_RESUME (3 + HDEX_BASE)
145#define HDEX_RECORD_START (4 + HDEX_BASE)
146#define HDEX_RECORD_STOP (5 + HDEX_BASE)
147#define HDEX_MIDI_IN_START (6 + HDEX_BASE)
148#define HDEX_MIDI_IN_STOP (7 + HDEX_BASE)
149#define HDEX_MIDI_OUT_START (8 + HDEX_BASE)
150#define HDEX_MIDI_OUT_STOP (9 + HDEX_BASE)
151#define HDEX_AUX_REQ (10 + HDEX_BASE)
152
153#define HDEXAR_CLEAR_PEAKS 1
154#define HDEXAR_IN_SET_POTS 2
155#define HDEXAR_AUX_SET_POTS 3
156#define HDEXAR_CAL_A_TO_D 4
157#define HDEXAR_RD_EXT_DSP_BITS 5
158
159
160#define HDEXAR_SET_ANA_IN 0
161#define HDEXAR_SET_SYNTH_IN 4
162#define HDEXAR_READ_DAT_IN 5
163#define HDEXAR_MIC_SET_POTS 6
164#define HDEXAR_SET_DAT_IN 7
165
166#define HDEXAR_SET_SYNTH_48 8
167#define HDEXAR_SET_SYNTH_44 9
168
169#define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF))
170#define LOWORD(l) ((u16)(u32)(l))
171#define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF))
172#define LOBYTE(w) ((u8)(w))
173#define MAKELONG(low, hi) ((long)(((u16)(low))|(((u32)((u16)(hi)))<<16)))
174#define MAKEWORD(low, hi) ((u16)(((u8)(low))|(((u16)((u8)(hi)))<<8)))
175
176#define PCTODSP_OFFSET(w) (u16)((w)/2)
177#define PCTODSP_BASED(w) (u16)(((w)/2) + DSP_BASE_ADDR)
178#define DSPTOPC_BASED(w) (((w) - DSP_BASE_ADDR) * 2)
179
180#ifdef SLOWIO
181# undef outb
182# undef inb
183# define outb outb_p
184# define inb inb_p
185#endif
186
187
188#define JQS_wStart 0x00
189#define JQS_wSize 0x02
190#define JQS_wHead 0x04
191#define JQS_wTail 0x06
192#define JQS__size 0x08
193
194
195#define DAQDS_wStart 0x00
196#define DAQDS_wSize 0x02
197#define DAQDS_wFormat 0x04
198#define DAQDS_wSampleSize 0x06
199#define DAQDS_wChannels 0x08
200#define DAQDS_wSampleRate 0x0A
201#define DAQDS_wIntMsg 0x0C
202#define DAQDS_wFlags 0x0E
203#define DAQDS__size 0x10
204
205#include <sound/pcm.h>
206
207struct snd_msnd {
208 void __iomem *mappedbase;
209 int play_period_bytes;
210 int playLimit;
211 int playPeriods;
212 int playDMAPos;
213 int banksPlayed;
214 int captureDMAPos;
215 int capturePeriodBytes;
216 int captureLimit;
217 int capturePeriods;
218 struct snd_card *card;
219 void *msndmidi_mpu;
220 struct snd_rawmidi *rmidi;
221
222
223 long io;
224 int memid, irqid;
225 int irq, irq_ref;
226 unsigned long base;
227
228
229 void __iomem *SMA;
230 void __iomem *DAPQ;
231 void __iomem *DARQ;
232 void __iomem *MODQ;
233 void __iomem *MIDQ;
234 void __iomem *DSPQ;
235 int dspq_data_buff, dspq_buff_size;
236
237
238 enum { msndClassic, msndPinnacle } type;
239 fmode_t mode;
240 unsigned long flags;
241#define F_RESETTING 0
242#define F_HAVEDIGITAL 1
243#define F_AUDIO_WRITE_INUSE 2
244#define F_WRITING 3
245#define F_WRITEBLOCK 4
246#define F_WRITEFLUSH 5
247#define F_AUDIO_READ_INUSE 6
248#define F_READING 7
249#define F_READBLOCK 8
250#define F_EXT_MIDI_INUSE 9
251#define F_HDR_MIDI_INUSE 10
252#define F_DISABLE_WRITE_NDELAY 11
253 spinlock_t lock;
254 spinlock_t mixer_lock;
255 int nresets;
256 unsigned recsrc;
257#define LEVEL_ENTRIES 32
258 int left_levels[LEVEL_ENTRIES];
259 int right_levels[LEVEL_ENTRIES];
260 int calibrate_signal;
261 int play_sample_size, play_sample_rate, play_channels;
262 int play_ndelay;
263 int capture_sample_size, capture_sample_rate, capture_channels;
264 int capture_ndelay;
265 u8 bCurrentMidiPatch;
266
267 int last_playbank, last_recbank;
268 struct snd_pcm_substream *playback_substream;
269 struct snd_pcm_substream *capture_substream;
270
271};
272
273void snd_msnd_init_queue(void __iomem *base, int start, int size);
274
275int snd_msnd_send_dsp_cmd(struct snd_msnd *chip, u8 cmd);
276int snd_msnd_send_word(struct snd_msnd *chip,
277 unsigned char high,
278 unsigned char mid,
279 unsigned char low);
280int snd_msnd_upload_host(struct snd_msnd *chip,
281 const u8 *bin, int len);
282int snd_msnd_enable_irq(struct snd_msnd *chip);
283int snd_msnd_disable_irq(struct snd_msnd *chip);
284void snd_msnd_dsp_halt(struct snd_msnd *chip, struct file *file);
285int snd_msnd_DAPQ(struct snd_msnd *chip, int start);
286int snd_msnd_DARQ(struct snd_msnd *chip, int start);
287int snd_msnd_pcm(struct snd_card *card, int device);
288
289int snd_msndmidi_new(struct snd_card *card, int device);
290void snd_msndmidi_input_read(void *mpu);
291
292void snd_msndmix_setup(struct snd_msnd *chip);
293int snd_msndmix_new(struct snd_card *card);
294int snd_msndmix_force_recsrc(struct snd_msnd *chip, int recsrc);
295#endif
296
