1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_UCTLX_DEFS_H__ 29#define __CVMX_UCTLX_DEFS_H__ 30 31#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) 32#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) 33#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull)) 34#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull)) 35#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull)) 36#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull)) 37#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull)) 38#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull)) 39#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull)) 40#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull)) 41#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull)) 42#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull)) 43#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 44 45union cvmx_uctlx_bist_status { 46 uint64_t u64; 47 struct cvmx_uctlx_bist_status_s { 48#ifdef __BIG_ENDIAN_BITFIELD 49 uint64_t reserved_6_63:58; 50 uint64_t data_bis:1; 51 uint64_t desc_bis:1; 52 uint64_t erbm_bis:1; 53 uint64_t orbm_bis:1; 54 uint64_t wrbm_bis:1; 55 uint64_t ppaf_bis:1; 56#else 57 uint64_t ppaf_bis:1; 58 uint64_t wrbm_bis:1; 59 uint64_t orbm_bis:1; 60 uint64_t erbm_bis:1; 61 uint64_t desc_bis:1; 62 uint64_t data_bis:1; 63 uint64_t reserved_6_63:58; 64#endif 65 } s; 66 struct cvmx_uctlx_bist_status_s cn61xx; 67 struct cvmx_uctlx_bist_status_s cn63xx; 68 struct cvmx_uctlx_bist_status_s cn63xxp1; 69 struct cvmx_uctlx_bist_status_s cn66xx; 70 struct cvmx_uctlx_bist_status_s cn68xx; 71 struct cvmx_uctlx_bist_status_s cn68xxp1; 72 struct cvmx_uctlx_bist_status_s cnf71xx; 73}; 74 75union cvmx_uctlx_clk_rst_ctl { 76 uint64_t u64; 77 struct cvmx_uctlx_clk_rst_ctl_s { 78#ifdef __BIG_ENDIAN_BITFIELD 79 uint64_t reserved_25_63:39; 80 uint64_t clear_bist:1; 81 uint64_t start_bist:1; 82 uint64_t ehci_sm:1; 83 uint64_t ohci_clkcktrst:1; 84 uint64_t ohci_sm:1; 85 uint64_t ohci_susp_lgcy:1; 86 uint64_t app_start_clk:1; 87 uint64_t o_clkdiv_rst:1; 88 uint64_t h_clkdiv_byp:1; 89 uint64_t h_clkdiv_rst:1; 90 uint64_t h_clkdiv_en:1; 91 uint64_t o_clkdiv_en:1; 92 uint64_t h_div:4; 93 uint64_t p_refclk_sel:2; 94 uint64_t p_refclk_div:2; 95 uint64_t reserved_4_4:1; 96 uint64_t p_com_on:1; 97 uint64_t p_por:1; 98 uint64_t p_prst:1; 99 uint64_t hrst:1; 100#else 101 uint64_t hrst:1; 102 uint64_t p_prst:1; 103 uint64_t p_por:1; 104 uint64_t p_com_on:1; 105 uint64_t reserved_4_4:1; 106 uint64_t p_refclk_div:2; 107 uint64_t p_refclk_sel:2; 108 uint64_t h_div:4; 109 uint64_t o_clkdiv_en:1; 110 uint64_t h_clkdiv_en:1; 111 uint64_t h_clkdiv_rst:1; 112 uint64_t h_clkdiv_byp:1; 113 uint64_t o_clkdiv_rst:1; 114 uint64_t app_start_clk:1; 115 uint64_t ohci_susp_lgcy:1; 116 uint64_t ohci_sm:1; 117 uint64_t ohci_clkcktrst:1; 118 uint64_t ehci_sm:1; 119 uint64_t start_bist:1; 120 uint64_t clear_bist:1; 121 uint64_t reserved_25_63:39; 122#endif 123 } s; 124 struct cvmx_uctlx_clk_rst_ctl_s cn61xx; 125 struct cvmx_uctlx_clk_rst_ctl_s cn63xx; 126 struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; 127 struct cvmx_uctlx_clk_rst_ctl_s cn66xx; 128 struct cvmx_uctlx_clk_rst_ctl_s cn68xx; 129 struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1; 130 struct cvmx_uctlx_clk_rst_ctl_s cnf71xx; 131}; 132 133union cvmx_uctlx_ehci_ctl { 134 uint64_t u64; 135 struct cvmx_uctlx_ehci_ctl_s { 136#ifdef __BIG_ENDIAN_BITFIELD 137 uint64_t reserved_20_63:44; 138 uint64_t desc_rbm:1; 139 uint64_t reg_nb:1; 140 uint64_t l2c_dc:1; 141 uint64_t l2c_bc:1; 142 uint64_t l2c_0pag:1; 143 uint64_t l2c_stt:1; 144 uint64_t l2c_buff_emod:2; 145 uint64_t l2c_desc_emod:2; 146 uint64_t inv_reg_a2:1; 147 uint64_t ehci_64b_addr_en:1; 148 uint64_t l2c_addr_msb:8; 149#else 150 uint64_t l2c_addr_msb:8; 151 uint64_t ehci_64b_addr_en:1; 152 uint64_t inv_reg_a2:1; 153 uint64_t l2c_desc_emod:2; 154 uint64_t l2c_buff_emod:2; 155 uint64_t l2c_stt:1; 156 uint64_t l2c_0pag:1; 157 uint64_t l2c_bc:1; 158 uint64_t l2c_dc:1; 159 uint64_t reg_nb:1; 160 uint64_t desc_rbm:1; 161 uint64_t reserved_20_63:44; 162#endif 163 } s; 164 struct cvmx_uctlx_ehci_ctl_s cn61xx; 165 struct cvmx_uctlx_ehci_ctl_s cn63xx; 166 struct cvmx_uctlx_ehci_ctl_s cn63xxp1; 167 struct cvmx_uctlx_ehci_ctl_s cn66xx; 168 struct cvmx_uctlx_ehci_ctl_s cn68xx; 169 struct cvmx_uctlx_ehci_ctl_s cn68xxp1; 170 struct cvmx_uctlx_ehci_ctl_s cnf71xx; 171}; 172 173union cvmx_uctlx_ehci_fla { 174 uint64_t u64; 175 struct cvmx_uctlx_ehci_fla_s { 176#ifdef __BIG_ENDIAN_BITFIELD 177 uint64_t reserved_6_63:58; 178 uint64_t fla:6; 179#else 180 uint64_t fla:6; 181 uint64_t reserved_6_63:58; 182#endif 183 } s; 184 struct cvmx_uctlx_ehci_fla_s cn61xx; 185 struct cvmx_uctlx_ehci_fla_s cn63xx; 186 struct cvmx_uctlx_ehci_fla_s cn63xxp1; 187 struct cvmx_uctlx_ehci_fla_s cn66xx; 188 struct cvmx_uctlx_ehci_fla_s cn68xx; 189 struct cvmx_uctlx_ehci_fla_s cn68xxp1; 190 struct cvmx_uctlx_ehci_fla_s cnf71xx; 191}; 192 193union cvmx_uctlx_erto_ctl { 194 uint64_t u64; 195 struct cvmx_uctlx_erto_ctl_s { 196#ifdef __BIG_ENDIAN_BITFIELD 197 uint64_t reserved_32_63:32; 198 uint64_t to_val:27; 199 uint64_t reserved_0_4:5; 200#else 201 uint64_t reserved_0_4:5; 202 uint64_t to_val:27; 203 uint64_t reserved_32_63:32; 204#endif 205 } s; 206 struct cvmx_uctlx_erto_ctl_s cn61xx; 207 struct cvmx_uctlx_erto_ctl_s cn63xx; 208 struct cvmx_uctlx_erto_ctl_s cn63xxp1; 209 struct cvmx_uctlx_erto_ctl_s cn66xx; 210 struct cvmx_uctlx_erto_ctl_s cn68xx; 211 struct cvmx_uctlx_erto_ctl_s cn68xxp1; 212 struct cvmx_uctlx_erto_ctl_s cnf71xx; 213}; 214 215union cvmx_uctlx_if_ena { 216 uint64_t u64; 217 struct cvmx_uctlx_if_ena_s { 218#ifdef __BIG_ENDIAN_BITFIELD 219 uint64_t reserved_1_63:63; 220 uint64_t en:1; 221#else 222 uint64_t en:1; 223 uint64_t reserved_1_63:63; 224#endif 225 } s; 226 struct cvmx_uctlx_if_ena_s cn61xx; 227 struct cvmx_uctlx_if_ena_s cn63xx; 228 struct cvmx_uctlx_if_ena_s cn63xxp1; 229 struct cvmx_uctlx_if_ena_s cn66xx; 230 struct cvmx_uctlx_if_ena_s cn68xx; 231 struct cvmx_uctlx_if_ena_s cn68xxp1; 232 struct cvmx_uctlx_if_ena_s cnf71xx; 233}; 234 235union cvmx_uctlx_int_ena { 236 uint64_t u64; 237 struct cvmx_uctlx_int_ena_s { 238#ifdef __BIG_ENDIAN_BITFIELD 239 uint64_t reserved_8_63:56; 240 uint64_t ec_ovf_e:1; 241 uint64_t oc_ovf_e:1; 242 uint64_t wb_pop_e:1; 243 uint64_t wb_psh_f:1; 244 uint64_t cf_psh_f:1; 245 uint64_t or_psh_f:1; 246 uint64_t er_psh_f:1; 247 uint64_t pp_psh_f:1; 248#else 249 uint64_t pp_psh_f:1; 250 uint64_t er_psh_f:1; 251 uint64_t or_psh_f:1; 252 uint64_t cf_psh_f:1; 253 uint64_t wb_psh_f:1; 254 uint64_t wb_pop_e:1; 255 uint64_t oc_ovf_e:1; 256 uint64_t ec_ovf_e:1; 257 uint64_t reserved_8_63:56; 258#endif 259 } s; 260 struct cvmx_uctlx_int_ena_s cn61xx; 261 struct cvmx_uctlx_int_ena_s cn63xx; 262 struct cvmx_uctlx_int_ena_s cn63xxp1; 263 struct cvmx_uctlx_int_ena_s cn66xx; 264 struct cvmx_uctlx_int_ena_s cn68xx; 265 struct cvmx_uctlx_int_ena_s cn68xxp1; 266 struct cvmx_uctlx_int_ena_s cnf71xx; 267}; 268 269union cvmx_uctlx_int_reg { 270 uint64_t u64; 271 struct cvmx_uctlx_int_reg_s { 272#ifdef __BIG_ENDIAN_BITFIELD 273 uint64_t reserved_8_63:56; 274 uint64_t ec_ovf_e:1; 275 uint64_t oc_ovf_e:1; 276 uint64_t wb_pop_e:1; 277 uint64_t wb_psh_f:1; 278 uint64_t cf_psh_f:1; 279 uint64_t or_psh_f:1; 280 uint64_t er_psh_f:1; 281 uint64_t pp_psh_f:1; 282#else 283 uint64_t pp_psh_f:1; 284 uint64_t er_psh_f:1; 285 uint64_t or_psh_f:1; 286 uint64_t cf_psh_f:1; 287 uint64_t wb_psh_f:1; 288 uint64_t wb_pop_e:1; 289 uint64_t oc_ovf_e:1; 290 uint64_t ec_ovf_e:1; 291 uint64_t reserved_8_63:56; 292#endif 293 } s; 294 struct cvmx_uctlx_int_reg_s cn61xx; 295 struct cvmx_uctlx_int_reg_s cn63xx; 296 struct cvmx_uctlx_int_reg_s cn63xxp1; 297 struct cvmx_uctlx_int_reg_s cn66xx; 298 struct cvmx_uctlx_int_reg_s cn68xx; 299 struct cvmx_uctlx_int_reg_s cn68xxp1; 300 struct cvmx_uctlx_int_reg_s cnf71xx; 301}; 302 303union cvmx_uctlx_ohci_ctl { 304 uint64_t u64; 305 struct cvmx_uctlx_ohci_ctl_s { 306#ifdef __BIG_ENDIAN_BITFIELD 307 uint64_t reserved_19_63:45; 308 uint64_t reg_nb:1; 309 uint64_t l2c_dc:1; 310 uint64_t l2c_bc:1; 311 uint64_t l2c_0pag:1; 312 uint64_t l2c_stt:1; 313 uint64_t l2c_buff_emod:2; 314 uint64_t l2c_desc_emod:2; 315 uint64_t inv_reg_a2:1; 316 uint64_t reserved_8_8:1; 317 uint64_t l2c_addr_msb:8; 318#else 319 uint64_t l2c_addr_msb:8; 320 uint64_t reserved_8_8:1; 321 uint64_t inv_reg_a2:1; 322 uint64_t l2c_desc_emod:2; 323 uint64_t l2c_buff_emod:2; 324 uint64_t l2c_stt:1; 325 uint64_t l2c_0pag:1; 326 uint64_t l2c_bc:1; 327 uint64_t l2c_dc:1; 328 uint64_t reg_nb:1; 329 uint64_t reserved_19_63:45; 330#endif 331 } s; 332 struct cvmx_uctlx_ohci_ctl_s cn61xx; 333 struct cvmx_uctlx_ohci_ctl_s cn63xx; 334 struct cvmx_uctlx_ohci_ctl_s cn63xxp1; 335 struct cvmx_uctlx_ohci_ctl_s cn66xx; 336 struct cvmx_uctlx_ohci_ctl_s cn68xx; 337 struct cvmx_uctlx_ohci_ctl_s cn68xxp1; 338 struct cvmx_uctlx_ohci_ctl_s cnf71xx; 339}; 340 341union cvmx_uctlx_orto_ctl { 342 uint64_t u64; 343 struct cvmx_uctlx_orto_ctl_s { 344#ifdef __BIG_ENDIAN_BITFIELD 345 uint64_t reserved_32_63:32; 346 uint64_t to_val:24; 347 uint64_t reserved_0_7:8; 348#else 349 uint64_t reserved_0_7:8; 350 uint64_t to_val:24; 351 uint64_t reserved_32_63:32; 352#endif 353 } s; 354 struct cvmx_uctlx_orto_ctl_s cn61xx; 355 struct cvmx_uctlx_orto_ctl_s cn63xx; 356 struct cvmx_uctlx_orto_ctl_s cn63xxp1; 357 struct cvmx_uctlx_orto_ctl_s cn66xx; 358 struct cvmx_uctlx_orto_ctl_s cn68xx; 359 struct cvmx_uctlx_orto_ctl_s cn68xxp1; 360 struct cvmx_uctlx_orto_ctl_s cnf71xx; 361}; 362 363union cvmx_uctlx_ppaf_wm { 364 uint64_t u64; 365 struct cvmx_uctlx_ppaf_wm_s { 366#ifdef __BIG_ENDIAN_BITFIELD 367 uint64_t reserved_5_63:59; 368 uint64_t wm:5; 369#else 370 uint64_t wm:5; 371 uint64_t reserved_5_63:59; 372#endif 373 } s; 374 struct cvmx_uctlx_ppaf_wm_s cn61xx; 375 struct cvmx_uctlx_ppaf_wm_s cn63xx; 376 struct cvmx_uctlx_ppaf_wm_s cn63xxp1; 377 struct cvmx_uctlx_ppaf_wm_s cn66xx; 378 struct cvmx_uctlx_ppaf_wm_s cnf71xx; 379}; 380 381union cvmx_uctlx_uphy_ctl_status { 382 uint64_t u64; 383 struct cvmx_uctlx_uphy_ctl_status_s { 384#ifdef __BIG_ENDIAN_BITFIELD 385 uint64_t reserved_10_63:54; 386 uint64_t bist_done:1; 387 uint64_t bist_err:1; 388 uint64_t hsbist:1; 389 uint64_t fsbist:1; 390 uint64_t lsbist:1; 391 uint64_t siddq:1; 392 uint64_t vtest_en:1; 393 uint64_t uphy_bist:1; 394 uint64_t bist_en:1; 395 uint64_t ate_reset:1; 396#else 397 uint64_t ate_reset:1; 398 uint64_t bist_en:1; 399 uint64_t uphy_bist:1; 400 uint64_t vtest_en:1; 401 uint64_t siddq:1; 402 uint64_t lsbist:1; 403 uint64_t fsbist:1; 404 uint64_t hsbist:1; 405 uint64_t bist_err:1; 406 uint64_t bist_done:1; 407 uint64_t reserved_10_63:54; 408#endif 409 } s; 410 struct cvmx_uctlx_uphy_ctl_status_s cn61xx; 411 struct cvmx_uctlx_uphy_ctl_status_s cn63xx; 412 struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; 413 struct cvmx_uctlx_uphy_ctl_status_s cn66xx; 414 struct cvmx_uctlx_uphy_ctl_status_s cn68xx; 415 struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1; 416 struct cvmx_uctlx_uphy_ctl_status_s cnf71xx; 417}; 418 419union cvmx_uctlx_uphy_portx_ctl_status { 420 uint64_t u64; 421 struct cvmx_uctlx_uphy_portx_ctl_status_s { 422#ifdef __BIG_ENDIAN_BITFIELD 423 uint64_t reserved_43_63:21; 424 uint64_t tdata_out:4; 425 uint64_t txbiststuffenh:1; 426 uint64_t txbiststuffen:1; 427 uint64_t dmpulldown:1; 428 uint64_t dppulldown:1; 429 uint64_t vbusvldext:1; 430 uint64_t portreset:1; 431 uint64_t txhsvxtune:2; 432 uint64_t txvreftune:4; 433 uint64_t txrisetune:1; 434 uint64_t txpreemphasistune:1; 435 uint64_t txfslstune:4; 436 uint64_t sqrxtune:3; 437 uint64_t compdistune:3; 438 uint64_t loop_en:1; 439 uint64_t tclk:1; 440 uint64_t tdata_sel:1; 441 uint64_t taddr_in:4; 442 uint64_t tdata_in:8; 443#else 444 uint64_t tdata_in:8; 445 uint64_t taddr_in:4; 446 uint64_t tdata_sel:1; 447 uint64_t tclk:1; 448 uint64_t loop_en:1; 449 uint64_t compdistune:3; 450 uint64_t sqrxtune:3; 451 uint64_t txfslstune:4; 452 uint64_t txpreemphasistune:1; 453 uint64_t txrisetune:1; 454 uint64_t txvreftune:4; 455 uint64_t txhsvxtune:2; 456 uint64_t portreset:1; 457 uint64_t vbusvldext:1; 458 uint64_t dppulldown:1; 459 uint64_t dmpulldown:1; 460 uint64_t txbiststuffen:1; 461 uint64_t txbiststuffenh:1; 462 uint64_t tdata_out:4; 463 uint64_t reserved_43_63:21; 464#endif 465 } s; 466 struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx; 467 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; 468 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; 469 struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx; 470 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx; 471 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1; 472 struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx; 473}; 474 475#endif 476