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16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__
18
19struct clk_omap_divider {
20 struct clk_hw hw;
21 struct clk_omap_reg reg;
22 u8 shift;
23 u8 width;
24 u8 flags;
25 s8 latch;
26 const struct clk_div_table *table;
27};
28
29#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
30
31struct clk_omap_mux {
32 struct clk_hw hw;
33 struct clk_omap_reg reg;
34 u32 *table;
35 u32 mask;
36 u8 shift;
37 s8 latch;
38 u8 flags;
39};
40
41#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
42
43enum {
44 TI_CLK_FIXED,
45 TI_CLK_MUX,
46 TI_CLK_DIVIDER,
47 TI_CLK_COMPOSITE,
48 TI_CLK_FIXED_FACTOR,
49 TI_CLK_GATE,
50 TI_CLK_DPLL,
51};
52
53
54#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
55#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
56#define CLKF_SET_RATE_PARENT (1 << 2)
57#define CLKF_OMAP3 (1 << 3)
58#define CLKF_AM35XX (1 << 4)
59
60
61#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
62#define CLKF_INTERFACE (1 << 6)
63#define CLKF_SSI (1 << 7)
64#define CLKF_DSS (1 << 8)
65#define CLKF_HSOTGUSB (1 << 9)
66#define CLKF_WAIT (1 << 10)
67#define CLKF_NO_WAIT (1 << 11)
68#define CLKF_HSDIV (1 << 12)
69#define CLKF_CLKDM (1 << 13)
70
71
72#define CLKF_LOW_POWER_STOP (1 << 5)
73#define CLKF_LOCK (1 << 6)
74#define CLKF_LOW_POWER_BYPASS (1 << 7)
75#define CLKF_PER (1 << 8)
76#define CLKF_CORE (1 << 9)
77#define CLKF_J_TYPE (1 << 10)
78
79
80#define CLKF_SW_SUP BIT(5)
81#define CLKF_HW_SUP BIT(6)
82#define CLKF_NO_IDLEST BIT(7)
83
84#define CLK(dev, con, ck) \
85 { \
86 .lk = { \
87 .dev_id = dev, \
88 .con_id = con, \
89 }, \
90 .clk = ck, \
91 }
92
93struct ti_clk {
94 const char *name;
95 const char *clkdm_name;
96 int type;
97 void *data;
98 struct ti_clk *patch;
99 struct clk *clk;
100};
101
102struct ti_clk_mux {
103 u8 bit_shift;
104 int num_parents;
105 u16 reg;
106 u8 module;
107 const char * const *parents;
108 u16 flags;
109};
110
111struct ti_clk_divider {
112 const char *parent;
113 u8 bit_shift;
114 u16 max_div;
115 u16 reg;
116 u8 module;
117 int *dividers;
118 int num_dividers;
119 u16 flags;
120};
121
122struct ti_clk_gate {
123 const char *parent;
124 u8 bit_shift;
125 u16 reg;
126 u8 module;
127 u16 flags;
128};
129
130
131enum {
132 CLK_COMPONENT_TYPE_GATE = 0,
133 CLK_COMPONENT_TYPE_DIVIDER,
134 CLK_COMPONENT_TYPE_MUX,
135 CLK_COMPONENT_TYPE_MAX,
136};
137
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142
143struct ti_dt_clk {
144 struct clk_lookup lk;
145 char *node_name;
146};
147
148#define DT_CLK(dev, con, name) \
149 { \
150 .lk = { \
151 .dev_id = dev, \
152 .con_id = con, \
153 }, \
154 .node_name = name, \
155 }
156
157
158struct omap_clkctrl_div_data {
159 const int *dividers;
160 int max_div;
161 u32 flags;
162};
163
164struct omap_clkctrl_bit_data {
165 u8 bit;
166 u8 type;
167 const char * const *parents;
168 const void *data;
169};
170
171struct omap_clkctrl_reg_data {
172 u16 offset;
173 const struct omap_clkctrl_bit_data *bit_data;
174 u16 flags;
175 const char *parent;
176 const char *clkdm_name;
177};
178
179struct omap_clkctrl_data {
180 u32 addr;
181 const struct omap_clkctrl_reg_data *regs;
182};
183
184extern const struct omap_clkctrl_data omap4_clkctrl_data[];
185extern const struct omap_clkctrl_data omap5_clkctrl_data[];
186extern const struct omap_clkctrl_data dra7_clkctrl_data[];
187extern const struct omap_clkctrl_data am3_clkctrl_data[];
188extern const struct omap_clkctrl_data am4_clkctrl_data[];
189extern const struct omap_clkctrl_data am438x_clkctrl_data[];
190extern const struct omap_clkctrl_data dm814_clkctrl_data[];
191extern const struct omap_clkctrl_data dm816_clkctrl_data[];
192
193typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
194
195struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
196 const char *con);
197int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
198void ti_clk_add_aliases(void);
199
200void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
201
202struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
203
204int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
205 u8 flags, u8 *width,
206 const struct clk_div_table **table);
207
208int ti_clk_get_reg_addr(struct device_node *node, int index,
209 struct clk_omap_reg *reg);
210void ti_dt_clocks_register(struct ti_dt_clk *oclks);
211int ti_clk_retry_init(struct device_node *node, void *user,
212 ti_of_clk_init_cb_t func);
213int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
214
215void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
216int of_ti_clk_autoidle_setup(struct device_node *node);
217void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
218
219extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
220extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
221extern const struct clk_hw_omap_ops clkhwops_wait;
222extern const struct clk_hw_omap_ops clkhwops_iclk;
223extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
224extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
225extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
226extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
227extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
228extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
229extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
230extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
231
232extern const struct clk_ops ti_clk_divider_ops;
233extern const struct clk_ops ti_clk_mux_ops;
234extern const struct clk_ops omap_gate_clk_ops;
235
236void omap2_init_clk_clkdm(struct clk_hw *hw);
237int omap2_clkops_enable_clkdm(struct clk_hw *hw);
238void omap2_clkops_disable_clkdm(struct clk_hw *hw);
239
240int omap2_dflt_clk_enable(struct clk_hw *hw);
241void omap2_dflt_clk_disable(struct clk_hw *hw);
242int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
243void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
244 struct clk_omap_reg *other_reg,
245 u8 *other_bit);
246void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
247 struct clk_omap_reg *idlest_reg,
248 u8 *idlest_bit, u8 *idlest_val);
249
250void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
251void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
252
253u8 omap2_init_dpll_parent(struct clk_hw *hw);
254int omap3_noncore_dpll_enable(struct clk_hw *hw);
255void omap3_noncore_dpll_disable(struct clk_hw *hw);
256int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
257int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
258 unsigned long parent_rate);
259int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
260 unsigned long rate,
261 unsigned long parent_rate,
262 u8 index);
263int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
264 struct clk_rate_request *req);
265long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
266 unsigned long *parent_rate);
267unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
268 unsigned long parent_rate);
269
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274
275#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
276
277unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
278int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
279 unsigned long parent_rate);
280int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
281 unsigned long parent_rate, u8 index);
282int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
283 unsigned long parent_rate);
284void omap3_clk_lock_dpll5(void);
285
286unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
287 unsigned long parent_rate);
288long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
289 unsigned long target_rate,
290 unsigned long *parent_rate);
291int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
292 struct clk_rate_request *req);
293
294extern struct ti_clk_ll_ops *ti_clk_ll_ops;
295
296#endif
297
