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6#include <linux/sched.h>
7#include <linux/device.h>
8#include <linux/dma-mapping.h>
9#include <linux/dmapool.h>
10#include <linux/dmaengine.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/of_device.h>
19#include <linux/of.h>
20#include <linux/clk.h>
21#include <linux/of_dma.h>
22
23#include "virt-dma.h"
24
25#define DRIVER_NAME "k3-dma"
26#define DMA_MAX_SIZE 0x1ffc
27#define DMA_CYCLIC_MAX_PERIOD 0x1000
28#define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
29
30#define INT_STAT 0x00
31#define INT_TC1 0x04
32#define INT_TC2 0x08
33#define INT_ERR1 0x0c
34#define INT_ERR2 0x10
35#define INT_TC1_MASK 0x18
36#define INT_TC2_MASK 0x1c
37#define INT_ERR1_MASK 0x20
38#define INT_ERR2_MASK 0x24
39#define INT_TC1_RAW 0x600
40#define INT_TC2_RAW 0x608
41#define INT_ERR1_RAW 0x610
42#define INT_ERR2_RAW 0x618
43#define CH_PRI 0x688
44#define CH_STAT 0x690
45#define CX_CUR_CNT 0x704
46#define CX_LLI 0x800
47#define CX_CNT1 0x80c
48#define CX_CNT0 0x810
49#define CX_SRC 0x814
50#define CX_DST 0x818
51#define CX_CFG 0x81c
52#define AXI_CFG 0x820
53#define AXI_CFG_DEFAULT 0x201201
54
55#define CX_LLI_CHAIN_EN 0x2
56#define CX_CFG_EN 0x1
57#define CX_CFG_NODEIRQ BIT(1)
58#define CX_CFG_MEM2PER (0x1 << 2)
59#define CX_CFG_PER2MEM (0x2 << 2)
60#define CX_CFG_SRCINCR (0x1 << 31)
61#define CX_CFG_DSTINCR (0x1 << 30)
62
63struct k3_desc_hw {
64 u32 lli;
65 u32 reserved[3];
66 u32 count;
67 u32 saddr;
68 u32 daddr;
69 u32 config;
70} __aligned(32);
71
72struct k3_dma_desc_sw {
73 struct virt_dma_desc vd;
74 dma_addr_t desc_hw_lli;
75 size_t desc_num;
76 size_t size;
77 struct k3_desc_hw *desc_hw;
78};
79
80struct k3_dma_phy;
81
82struct k3_dma_chan {
83 u32 ccfg;
84 struct virt_dma_chan vc;
85 struct k3_dma_phy *phy;
86 struct list_head node;
87 enum dma_transfer_direction dir;
88 dma_addr_t dev_addr;
89 enum dma_status status;
90 bool cyclic;
91};
92
93struct k3_dma_phy {
94 u32 idx;
95 void __iomem *base;
96 struct k3_dma_chan *vchan;
97 struct k3_dma_desc_sw *ds_run;
98 struct k3_dma_desc_sw *ds_done;
99};
100
101struct k3_dma_dev {
102 struct dma_device slave;
103 void __iomem *base;
104 struct tasklet_struct task;
105 spinlock_t lock;
106 struct list_head chan_pending;
107 struct k3_dma_phy *phy;
108 struct k3_dma_chan *chans;
109 struct clk *clk;
110 struct dma_pool *pool;
111 u32 dma_channels;
112 u32 dma_requests;
113 unsigned int irq;
114};
115
116#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
117
118static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
119{
120 return container_of(chan, struct k3_dma_chan, vc.chan);
121}
122
123static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
124{
125 u32 val = 0;
126
127 if (on) {
128 val = readl_relaxed(phy->base + CX_CFG);
129 val |= CX_CFG_EN;
130 writel_relaxed(val, phy->base + CX_CFG);
131 } else {
132 val = readl_relaxed(phy->base + CX_CFG);
133 val &= ~CX_CFG_EN;
134 writel_relaxed(val, phy->base + CX_CFG);
135 }
136}
137
138static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
139{
140 u32 val = 0;
141
142 k3_dma_pause_dma(phy, false);
143
144 val = 0x1 << phy->idx;
145 writel_relaxed(val, d->base + INT_TC1_RAW);
146 writel_relaxed(val, d->base + INT_TC2_RAW);
147 writel_relaxed(val, d->base + INT_ERR1_RAW);
148 writel_relaxed(val, d->base + INT_ERR2_RAW);
149}
150
151static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
152{
153 writel_relaxed(hw->lli, phy->base + CX_LLI);
154 writel_relaxed(hw->count, phy->base + CX_CNT0);
155 writel_relaxed(hw->saddr, phy->base + CX_SRC);
156 writel_relaxed(hw->daddr, phy->base + CX_DST);
157 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
158 writel_relaxed(hw->config, phy->base + CX_CFG);
159}
160
161static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
162{
163 u32 cnt = 0;
164
165 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
166 cnt &= 0xffff;
167 return cnt;
168}
169
170static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
171{
172 return readl_relaxed(phy->base + CX_LLI);
173}
174
175static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
176{
177 return readl_relaxed(d->base + CH_STAT);
178}
179
180static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
181{
182 if (on) {
183
184 writel_relaxed(0x0, d->base + CH_PRI);
185
186
187 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
188 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
189 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
190 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
191 } else {
192
193 writel_relaxed(0x0, d->base + INT_TC1_MASK);
194 writel_relaxed(0x0, d->base + INT_TC2_MASK);
195 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
196 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
197 }
198}
199
200static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
201{
202 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
203 struct k3_dma_phy *p;
204 struct k3_dma_chan *c;
205 u32 stat = readl_relaxed(d->base + INT_STAT);
206 u32 tc1 = readl_relaxed(d->base + INT_TC1);
207 u32 tc2 = readl_relaxed(d->base + INT_TC2);
208 u32 err1 = readl_relaxed(d->base + INT_ERR1);
209 u32 err2 = readl_relaxed(d->base + INT_ERR2);
210 u32 i, irq_chan = 0;
211
212 while (stat) {
213 i = __ffs(stat);
214 stat &= ~BIT(i);
215 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
216 unsigned long flags;
217
218 p = &d->phy[i];
219 c = p->vchan;
220 if (c && (tc1 & BIT(i))) {
221 spin_lock_irqsave(&c->vc.lock, flags);
222 vchan_cookie_complete(&p->ds_run->vd);
223 p->ds_done = p->ds_run;
224 p->ds_run = NULL;
225 spin_unlock_irqrestore(&c->vc.lock, flags);
226 }
227 if (c && (tc2 & BIT(i))) {
228 spin_lock_irqsave(&c->vc.lock, flags);
229 if (p->ds_run != NULL)
230 vchan_cyclic_callback(&p->ds_run->vd);
231 spin_unlock_irqrestore(&c->vc.lock, flags);
232 }
233 irq_chan |= BIT(i);
234 }
235 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
236 dev_warn(d->slave.dev, "DMA ERR\n");
237 }
238
239 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
240 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
241 writel_relaxed(err1, d->base + INT_ERR1_RAW);
242 writel_relaxed(err2, d->base + INT_ERR2_RAW);
243
244 if (irq_chan)
245 tasklet_schedule(&d->task);
246
247 if (irq_chan || err1 || err2)
248 return IRQ_HANDLED;
249
250 return IRQ_NONE;
251}
252
253static int k3_dma_start_txd(struct k3_dma_chan *c)
254{
255 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
256 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
257
258 if (!c->phy)
259 return -EAGAIN;
260
261 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
262 return -EAGAIN;
263
264 if (vd) {
265 struct k3_dma_desc_sw *ds =
266 container_of(vd, struct k3_dma_desc_sw, vd);
267
268
269
270
271 list_del(&ds->vd.node);
272
273 c->phy->ds_run = ds;
274 c->phy->ds_done = NULL;
275
276 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
277 return 0;
278 }
279 c->phy->ds_run = NULL;
280 c->phy->ds_done = NULL;
281 return -EAGAIN;
282}
283
284static void k3_dma_tasklet(unsigned long arg)
285{
286 struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
287 struct k3_dma_phy *p;
288 struct k3_dma_chan *c, *cn;
289 unsigned pch, pch_alloc = 0;
290
291
292 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
293 spin_lock_irq(&c->vc.lock);
294 p = c->phy;
295 if (p && p->ds_done) {
296 if (k3_dma_start_txd(c)) {
297
298 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
299
300 c->phy = NULL;
301 p->vchan = NULL;
302 }
303 }
304 spin_unlock_irq(&c->vc.lock);
305 }
306
307
308 spin_lock_irq(&d->lock);
309 for (pch = 0; pch < d->dma_channels; pch++) {
310 p = &d->phy[pch];
311
312 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
313 c = list_first_entry(&d->chan_pending,
314 struct k3_dma_chan, node);
315
316 list_del_init(&c->node);
317 pch_alloc |= 1 << pch;
318
319 p->vchan = c;
320 c->phy = p;
321 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
322 }
323 }
324 spin_unlock_irq(&d->lock);
325
326 for (pch = 0; pch < d->dma_channels; pch++) {
327 if (pch_alloc & (1 << pch)) {
328 p = &d->phy[pch];
329 c = p->vchan;
330 if (c) {
331 spin_lock_irq(&c->vc.lock);
332 k3_dma_start_txd(c);
333 spin_unlock_irq(&c->vc.lock);
334 }
335 }
336 }
337}
338
339static void k3_dma_free_chan_resources(struct dma_chan *chan)
340{
341 struct k3_dma_chan *c = to_k3_chan(chan);
342 struct k3_dma_dev *d = to_k3_dma(chan->device);
343 unsigned long flags;
344
345 spin_lock_irqsave(&d->lock, flags);
346 list_del_init(&c->node);
347 spin_unlock_irqrestore(&d->lock, flags);
348
349 vchan_free_chan_resources(&c->vc);
350 c->ccfg = 0;
351}
352
353static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
354 dma_cookie_t cookie, struct dma_tx_state *state)
355{
356 struct k3_dma_chan *c = to_k3_chan(chan);
357 struct k3_dma_dev *d = to_k3_dma(chan->device);
358 struct k3_dma_phy *p;
359 struct virt_dma_desc *vd;
360 unsigned long flags;
361 enum dma_status ret;
362 size_t bytes = 0;
363
364 ret = dma_cookie_status(&c->vc.chan, cookie, state);
365 if (ret == DMA_COMPLETE)
366 return ret;
367
368 spin_lock_irqsave(&c->vc.lock, flags);
369 p = c->phy;
370 ret = c->status;
371
372
373
374
375
376 vd = vchan_find_desc(&c->vc, cookie);
377 if (vd && !c->cyclic) {
378 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
379 } else if ((!p) || (!p->ds_run)) {
380 bytes = 0;
381 } else {
382 struct k3_dma_desc_sw *ds = p->ds_run;
383 u32 clli = 0, index = 0;
384
385 bytes = k3_dma_get_curr_cnt(d, p);
386 clli = k3_dma_get_curr_lli(p);
387 index = ((clli - ds->desc_hw_lli) /
388 sizeof(struct k3_desc_hw)) + 1;
389 for (; index < ds->desc_num; index++) {
390 bytes += ds->desc_hw[index].count;
391
392 if (!ds->desc_hw[index].lli)
393 break;
394 }
395 }
396 spin_unlock_irqrestore(&c->vc.lock, flags);
397 dma_set_residue(state, bytes);
398 return ret;
399}
400
401static void k3_dma_issue_pending(struct dma_chan *chan)
402{
403 struct k3_dma_chan *c = to_k3_chan(chan);
404 struct k3_dma_dev *d = to_k3_dma(chan->device);
405 unsigned long flags;
406
407 spin_lock_irqsave(&c->vc.lock, flags);
408
409 if (vchan_issue_pending(&c->vc)) {
410 spin_lock(&d->lock);
411 if (!c->phy) {
412 if (list_empty(&c->node)) {
413
414 list_add_tail(&c->node, &d->chan_pending);
415
416 tasklet_schedule(&d->task);
417 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
418 }
419 }
420 spin_unlock(&d->lock);
421 } else
422 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
423 spin_unlock_irqrestore(&c->vc.lock, flags);
424}
425
426static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
427 dma_addr_t src, size_t len, u32 num, u32 ccfg)
428{
429 if (num != ds->desc_num - 1)
430 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
431 sizeof(struct k3_desc_hw);
432
433 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
434 ds->desc_hw[num].count = len;
435 ds->desc_hw[num].saddr = src;
436 ds->desc_hw[num].daddr = dst;
437 ds->desc_hw[num].config = ccfg;
438}
439
440static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
441 struct dma_chan *chan)
442{
443 struct k3_dma_chan *c = to_k3_chan(chan);
444 struct k3_dma_desc_sw *ds;
445 struct k3_dma_dev *d = to_k3_dma(chan->device);
446 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
447
448 if (num > lli_limit) {
449 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
450 &c->vc, num, lli_limit);
451 return NULL;
452 }
453
454 ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
455 if (!ds)
456 return NULL;
457
458 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
459 if (!ds->desc_hw) {
460 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
461 kfree(ds);
462 return NULL;
463 }
464 ds->desc_num = num;
465 return ds;
466}
467
468static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
469 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
470 size_t len, unsigned long flags)
471{
472 struct k3_dma_chan *c = to_k3_chan(chan);
473 struct k3_dma_desc_sw *ds;
474 size_t copy = 0;
475 int num = 0;
476
477 if (!len)
478 return NULL;
479
480 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
481
482 ds = k3_dma_alloc_desc_resource(num, chan);
483 if (!ds)
484 return NULL;
485
486 c->cyclic = 0;
487 ds->size = len;
488 num = 0;
489
490 if (!c->ccfg) {
491
492 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
493 c->ccfg |= (0xf << 20) | (0xf << 24);
494 c->ccfg |= (0x3 << 12) | (0x3 << 16);
495 }
496
497 do {
498 copy = min_t(size_t, len, DMA_MAX_SIZE);
499 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
500
501 if (c->dir == DMA_MEM_TO_DEV) {
502 src += copy;
503 } else if (c->dir == DMA_DEV_TO_MEM) {
504 dst += copy;
505 } else {
506 src += copy;
507 dst += copy;
508 }
509 len -= copy;
510 } while (len);
511
512 ds->desc_hw[num-1].lli = 0;
513 return vchan_tx_prep(&c->vc, &ds->vd, flags);
514}
515
516static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
517 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
518 enum dma_transfer_direction dir, unsigned long flags, void *context)
519{
520 struct k3_dma_chan *c = to_k3_chan(chan);
521 struct k3_dma_desc_sw *ds;
522 size_t len, avail, total = 0;
523 struct scatterlist *sg;
524 dma_addr_t addr, src = 0, dst = 0;
525 int num = sglen, i;
526
527 if (sgl == NULL)
528 return NULL;
529
530 c->cyclic = 0;
531
532 for_each_sg(sgl, sg, sglen, i) {
533 avail = sg_dma_len(sg);
534 if (avail > DMA_MAX_SIZE)
535 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
536 }
537
538 ds = k3_dma_alloc_desc_resource(num, chan);
539 if (!ds)
540 return NULL;
541 num = 0;
542
543 for_each_sg(sgl, sg, sglen, i) {
544 addr = sg_dma_address(sg);
545 avail = sg_dma_len(sg);
546 total += avail;
547
548 do {
549 len = min_t(size_t, avail, DMA_MAX_SIZE);
550
551 if (dir == DMA_MEM_TO_DEV) {
552 src = addr;
553 dst = c->dev_addr;
554 } else if (dir == DMA_DEV_TO_MEM) {
555 src = c->dev_addr;
556 dst = addr;
557 }
558
559 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
560
561 addr += len;
562 avail -= len;
563 } while (avail);
564 }
565
566 ds->desc_hw[num-1].lli = 0;
567 ds->size = total;
568 return vchan_tx_prep(&c->vc, &ds->vd, flags);
569}
570
571static struct dma_async_tx_descriptor *
572k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
573 size_t buf_len, size_t period_len,
574 enum dma_transfer_direction dir,
575 unsigned long flags)
576{
577 struct k3_dma_chan *c = to_k3_chan(chan);
578 struct k3_dma_desc_sw *ds;
579 size_t len, avail, total = 0;
580 dma_addr_t addr, src = 0, dst = 0;
581 int num = 1, since = 0;
582 size_t modulo = DMA_CYCLIC_MAX_PERIOD;
583 u32 en_tc2 = 0;
584
585 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
586 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
587 buf_len, period_len, (int)dir);
588
589 avail = buf_len;
590 if (avail > modulo)
591 num += DIV_ROUND_UP(avail, modulo) - 1;
592
593 ds = k3_dma_alloc_desc_resource(num, chan);
594 if (!ds)
595 return NULL;
596
597 c->cyclic = 1;
598 addr = buf_addr;
599 avail = buf_len;
600 total = avail;
601 num = 0;
602
603 if (period_len < modulo)
604 modulo = period_len;
605
606 do {
607 len = min_t(size_t, avail, modulo);
608
609 if (dir == DMA_MEM_TO_DEV) {
610 src = addr;
611 dst = c->dev_addr;
612 } else if (dir == DMA_DEV_TO_MEM) {
613 src = c->dev_addr;
614 dst = addr;
615 }
616 since += len;
617 if (since >= period_len) {
618
619 en_tc2 = CX_CFG_NODEIRQ;
620 since -= period_len;
621 } else
622 en_tc2 = 0;
623
624 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
625
626 addr += len;
627 avail -= len;
628 } while (avail);
629
630
631 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
632
633 ds->size = total;
634
635 return vchan_tx_prep(&c->vc, &ds->vd, flags);
636}
637
638static int k3_dma_config(struct dma_chan *chan,
639 struct dma_slave_config *cfg)
640{
641 struct k3_dma_chan *c = to_k3_chan(chan);
642 u32 maxburst = 0, val = 0;
643 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
644
645 if (cfg == NULL)
646 return -EINVAL;
647 c->dir = cfg->direction;
648 if (c->dir == DMA_DEV_TO_MEM) {
649 c->ccfg = CX_CFG_DSTINCR;
650 c->dev_addr = cfg->src_addr;
651 maxburst = cfg->src_maxburst;
652 width = cfg->src_addr_width;
653 } else if (c->dir == DMA_MEM_TO_DEV) {
654 c->ccfg = CX_CFG_SRCINCR;
655 c->dev_addr = cfg->dst_addr;
656 maxburst = cfg->dst_maxburst;
657 width = cfg->dst_addr_width;
658 }
659 switch (width) {
660 case DMA_SLAVE_BUSWIDTH_1_BYTE:
661 case DMA_SLAVE_BUSWIDTH_2_BYTES:
662 case DMA_SLAVE_BUSWIDTH_4_BYTES:
663 case DMA_SLAVE_BUSWIDTH_8_BYTES:
664 val = __ffs(width);
665 break;
666 default:
667 val = 3;
668 break;
669 }
670 c->ccfg |= (val << 12) | (val << 16);
671
672 if ((maxburst == 0) || (maxburst > 16))
673 val = 15;
674 else
675 val = maxburst - 1;
676 c->ccfg |= (val << 20) | (val << 24);
677 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
678
679
680 c->ccfg |= c->vc.chan.chan_id << 4;
681
682 return 0;
683}
684
685static void k3_dma_free_desc(struct virt_dma_desc *vd)
686{
687 struct k3_dma_desc_sw *ds =
688 container_of(vd, struct k3_dma_desc_sw, vd);
689 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
690
691 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
692 kfree(ds);
693}
694
695static int k3_dma_terminate_all(struct dma_chan *chan)
696{
697 struct k3_dma_chan *c = to_k3_chan(chan);
698 struct k3_dma_dev *d = to_k3_dma(chan->device);
699 struct k3_dma_phy *p = c->phy;
700 unsigned long flags;
701 LIST_HEAD(head);
702
703 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
704
705
706 spin_lock(&d->lock);
707 list_del_init(&c->node);
708 spin_unlock(&d->lock);
709
710
711 spin_lock_irqsave(&c->vc.lock, flags);
712 vchan_get_all_descriptors(&c->vc, &head);
713 if (p) {
714
715 k3_dma_terminate_chan(p, d);
716 c->phy = NULL;
717 p->vchan = NULL;
718 if (p->ds_run) {
719 vchan_terminate_vdesc(&p->ds_run->vd);
720 p->ds_run = NULL;
721 }
722 p->ds_done = NULL;
723 }
724 spin_unlock_irqrestore(&c->vc.lock, flags);
725 vchan_dma_desc_free_list(&c->vc, &head);
726
727 return 0;
728}
729
730static void k3_dma_synchronize(struct dma_chan *chan)
731{
732 struct k3_dma_chan *c = to_k3_chan(chan);
733
734 vchan_synchronize(&c->vc);
735}
736
737static int k3_dma_transfer_pause(struct dma_chan *chan)
738{
739 struct k3_dma_chan *c = to_k3_chan(chan);
740 struct k3_dma_dev *d = to_k3_dma(chan->device);
741 struct k3_dma_phy *p = c->phy;
742
743 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
744 if (c->status == DMA_IN_PROGRESS) {
745 c->status = DMA_PAUSED;
746 if (p) {
747 k3_dma_pause_dma(p, false);
748 } else {
749 spin_lock(&d->lock);
750 list_del_init(&c->node);
751 spin_unlock(&d->lock);
752 }
753 }
754
755 return 0;
756}
757
758static int k3_dma_transfer_resume(struct dma_chan *chan)
759{
760 struct k3_dma_chan *c = to_k3_chan(chan);
761 struct k3_dma_dev *d = to_k3_dma(chan->device);
762 struct k3_dma_phy *p = c->phy;
763 unsigned long flags;
764
765 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
766 spin_lock_irqsave(&c->vc.lock, flags);
767 if (c->status == DMA_PAUSED) {
768 c->status = DMA_IN_PROGRESS;
769 if (p) {
770 k3_dma_pause_dma(p, true);
771 } else if (!list_empty(&c->vc.desc_issued)) {
772 spin_lock(&d->lock);
773 list_add_tail(&c->node, &d->chan_pending);
774 spin_unlock(&d->lock);
775 }
776 }
777 spin_unlock_irqrestore(&c->vc.lock, flags);
778
779 return 0;
780}
781
782static const struct of_device_id k3_pdma_dt_ids[] = {
783 { .compatible = "hisilicon,k3-dma-1.0", },
784 {}
785};
786MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
787
788static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
789 struct of_dma *ofdma)
790{
791 struct k3_dma_dev *d = ofdma->of_dma_data;
792 unsigned int request = dma_spec->args[0];
793
794 if (request >= d->dma_requests)
795 return NULL;
796
797 return dma_get_slave_channel(&(d->chans[request].vc.chan));
798}
799
800static int k3_dma_probe(struct platform_device *op)
801{
802 struct k3_dma_dev *d;
803 const struct of_device_id *of_id;
804 struct resource *iores;
805 int i, ret, irq = 0;
806
807 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
808 if (!iores)
809 return -EINVAL;
810
811 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
812 if (!d)
813 return -ENOMEM;
814
815 d->base = devm_ioremap_resource(&op->dev, iores);
816 if (IS_ERR(d->base))
817 return PTR_ERR(d->base);
818
819 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
820 if (of_id) {
821 of_property_read_u32((&op->dev)->of_node,
822 "dma-channels", &d->dma_channels);
823 of_property_read_u32((&op->dev)->of_node,
824 "dma-requests", &d->dma_requests);
825 }
826
827 d->clk = devm_clk_get(&op->dev, NULL);
828 if (IS_ERR(d->clk)) {
829 dev_err(&op->dev, "no dma clk\n");
830 return PTR_ERR(d->clk);
831 }
832
833 irq = platform_get_irq(op, 0);
834 ret = devm_request_irq(&op->dev, irq,
835 k3_dma_int_handler, 0, DRIVER_NAME, d);
836 if (ret)
837 return ret;
838
839 d->irq = irq;
840
841
842 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
843 LLI_BLOCK_SIZE, 32, 0);
844 if (!d->pool)
845 return -ENOMEM;
846
847
848 d->phy = devm_kcalloc(&op->dev,
849 d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL);
850 if (d->phy == NULL)
851 return -ENOMEM;
852
853 for (i = 0; i < d->dma_channels; i++) {
854 struct k3_dma_phy *p = &d->phy[i];
855
856 p->idx = i;
857 p->base = d->base + i * 0x40;
858 }
859
860 INIT_LIST_HEAD(&d->slave.channels);
861 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
862 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
863 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
864 d->slave.dev = &op->dev;
865 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
866 d->slave.device_tx_status = k3_dma_tx_status;
867 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
868 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
869 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
870 d->slave.device_issue_pending = k3_dma_issue_pending;
871 d->slave.device_config = k3_dma_config;
872 d->slave.device_pause = k3_dma_transfer_pause;
873 d->slave.device_resume = k3_dma_transfer_resume;
874 d->slave.device_terminate_all = k3_dma_terminate_all;
875 d->slave.device_synchronize = k3_dma_synchronize;
876 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
877
878
879 d->chans = devm_kcalloc(&op->dev,
880 d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL);
881 if (d->chans == NULL)
882 return -ENOMEM;
883
884 for (i = 0; i < d->dma_requests; i++) {
885 struct k3_dma_chan *c = &d->chans[i];
886
887 c->status = DMA_IN_PROGRESS;
888 INIT_LIST_HEAD(&c->node);
889 c->vc.desc_free = k3_dma_free_desc;
890 vchan_init(&c->vc, &d->slave);
891 }
892
893
894 ret = clk_prepare_enable(d->clk);
895 if (ret < 0) {
896 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
897 return ret;
898 }
899
900 k3_dma_enable_dma(d, true);
901
902 ret = dma_async_device_register(&d->slave);
903 if (ret)
904 goto dma_async_register_fail;
905
906 ret = of_dma_controller_register((&op->dev)->of_node,
907 k3_of_dma_simple_xlate, d);
908 if (ret)
909 goto of_dma_register_fail;
910
911 spin_lock_init(&d->lock);
912 INIT_LIST_HEAD(&d->chan_pending);
913 tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
914 platform_set_drvdata(op, d);
915 dev_info(&op->dev, "initialized\n");
916
917 return 0;
918
919of_dma_register_fail:
920 dma_async_device_unregister(&d->slave);
921dma_async_register_fail:
922 clk_disable_unprepare(d->clk);
923 return ret;
924}
925
926static int k3_dma_remove(struct platform_device *op)
927{
928 struct k3_dma_chan *c, *cn;
929 struct k3_dma_dev *d = platform_get_drvdata(op);
930
931 dma_async_device_unregister(&d->slave);
932 of_dma_controller_free((&op->dev)->of_node);
933
934 devm_free_irq(&op->dev, d->irq, d);
935
936 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
937 list_del(&c->vc.chan.device_node);
938 tasklet_kill(&c->vc.task);
939 }
940 tasklet_kill(&d->task);
941 clk_disable_unprepare(d->clk);
942 return 0;
943}
944
945#ifdef CONFIG_PM_SLEEP
946static int k3_dma_suspend_dev(struct device *dev)
947{
948 struct k3_dma_dev *d = dev_get_drvdata(dev);
949 u32 stat = 0;
950
951 stat = k3_dma_get_chan_stat(d);
952 if (stat) {
953 dev_warn(d->slave.dev,
954 "chan %d is running fail to suspend\n", stat);
955 return -1;
956 }
957 k3_dma_enable_dma(d, false);
958 clk_disable_unprepare(d->clk);
959 return 0;
960}
961
962static int k3_dma_resume_dev(struct device *dev)
963{
964 struct k3_dma_dev *d = dev_get_drvdata(dev);
965 int ret = 0;
966
967 ret = clk_prepare_enable(d->clk);
968 if (ret < 0) {
969 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
970 return ret;
971 }
972 k3_dma_enable_dma(d, true);
973 return 0;
974}
975#endif
976
977static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
978
979static struct platform_driver k3_pdma_driver = {
980 .driver = {
981 .name = DRIVER_NAME,
982 .pm = &k3_dma_pmops,
983 .of_match_table = k3_pdma_dt_ids,
984 },
985 .probe = k3_dma_probe,
986 .remove = k3_dma_remove,
987};
988
989module_platform_driver(k3_pdma_driver);
990
991MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
992MODULE_ALIAS("platform:k3dma");
993MODULE_LICENSE("GPL v2");
994
