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22#include <linux/module.h>
23#include <linux/fdtable.h>
24#include <linux/uaccess.h>
25#include <linux/firmware.h>
26#include "amdgpu.h"
27#include "amdgpu_amdkfd.h"
28#include "amdgpu_amdkfd_arcturus.h"
29#include "sdma0/sdma0_4_2_2_offset.h"
30#include "sdma0/sdma0_4_2_2_sh_mask.h"
31#include "sdma1/sdma1_4_2_2_offset.h"
32#include "sdma1/sdma1_4_2_2_sh_mask.h"
33#include "sdma2/sdma2_4_2_2_offset.h"
34#include "sdma2/sdma2_4_2_2_sh_mask.h"
35#include "sdma3/sdma3_4_2_2_offset.h"
36#include "sdma3/sdma3_4_2_2_sh_mask.h"
37#include "sdma4/sdma4_4_2_2_offset.h"
38#include "sdma4/sdma4_4_2_2_sh_mask.h"
39#include "sdma5/sdma5_4_2_2_offset.h"
40#include "sdma5/sdma5_4_2_2_sh_mask.h"
41#include "sdma6/sdma6_4_2_2_offset.h"
42#include "sdma6/sdma6_4_2_2_sh_mask.h"
43#include "sdma7/sdma7_4_2_2_offset.h"
44#include "sdma7/sdma7_4_2_2_sh_mask.h"
45#include "v9_structs.h"
46#include "soc15.h"
47#include "soc15d.h"
48#include "amdgpu_amdkfd_gfx_v9.h"
49#include "gfxhub_v1_0.h"
50#include "mmhub_v9_4.h"
51
52#define HQD_N_REGS 56
53#define DUMP_REG(addr) do { \
54 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
55 break; \
56 (*dump)[i][0] = (addr) << 2; \
57 (*dump)[i++][1] = RREG32(addr); \
58 } while (0)
59
60static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
61{
62 return (struct amdgpu_device *)kgd;
63}
64
65static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
66{
67 return (struct v9_sdma_mqd *)mqd;
68}
69
70static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
71 unsigned int engine_id,
72 unsigned int queue_id)
73{
74 uint32_t sdma_engine_reg_base = 0;
75 uint32_t sdma_rlc_reg_offset;
76
77 switch (engine_id) {
78 default:
79 dev_warn(adev->dev,
80 "Invalid sdma engine id (%d), using engine id 0\n",
81 engine_id);
82 fallthrough;
83 case 0:
84 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
85 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
86 break;
87 case 1:
88 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
89 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL;
90 break;
91 case 2:
92 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
93 mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
94 break;
95 case 3:
96 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
97 mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL;
98 break;
99 case 4:
100 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
101 mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL;
102 break;
103 case 5:
104 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
105 mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL;
106 break;
107 case 6:
108 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
109 mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL;
110 break;
111 case 7:
112 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
113 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL;
114 break;
115 }
116
117 sdma_rlc_reg_offset = sdma_engine_reg_base
118 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
119
120 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
121 queue_id, sdma_rlc_reg_offset);
122
123 return sdma_rlc_reg_offset;
124}
125
126int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
127 uint32_t __user *wptr, struct mm_struct *mm)
128{
129 struct amdgpu_device *adev = get_amdgpu_device(kgd);
130 struct v9_sdma_mqd *m;
131 uint32_t sdma_rlc_reg_offset;
132 unsigned long end_jiffies;
133 uint32_t data;
134 uint64_t data64;
135 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
136
137 m = get_sdma_mqd(mqd);
138 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
139 m->sdma_queue_id);
140
141 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
142 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
143
144 end_jiffies = msecs_to_jiffies(2000) + jiffies;
145 while (true) {
146 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
147 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
148 break;
149 if (time_after(jiffies, end_jiffies)) {
150 pr_err("SDMA RLC not idle in %s\n", __func__);
151 return -ETIME;
152 }
153 usleep_range(500, 1000);
154 }
155
156 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
157 m->sdmax_rlcx_doorbell_offset);
158
159 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
160 ENABLE, 1);
161 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
162 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
163 m->sdmax_rlcx_rb_rptr);
164 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
165 m->sdmax_rlcx_rb_rptr_hi);
166
167 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
168 if (read_user_wptr(mm, wptr64, data64)) {
169 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
170 lower_32_bits(data64));
171 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
172 upper_32_bits(data64));
173 } else {
174 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
175 m->sdmax_rlcx_rb_rptr);
176 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
177 m->sdmax_rlcx_rb_rptr_hi);
178 }
179 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
180
181 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
182 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
183 m->sdmax_rlcx_rb_base_hi);
184 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
185 m->sdmax_rlcx_rb_rptr_addr_lo);
186 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
187 m->sdmax_rlcx_rb_rptr_addr_hi);
188
189 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
190 RB_ENABLE, 1);
191 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
192
193 return 0;
194}
195
196int kgd_arcturus_hqd_sdma_dump(struct kgd_dev *kgd,
197 uint32_t engine_id, uint32_t queue_id,
198 uint32_t (**dump)[2], uint32_t *n_regs)
199{
200 struct amdgpu_device *adev = get_amdgpu_device(kgd);
201 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
202 engine_id, queue_id);
203 uint32_t i = 0, reg;
204#undef HQD_N_REGS
205#define HQD_N_REGS (19+6+7+10)
206
207 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
208 if (*dump == NULL)
209 return -ENOMEM;
210
211 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
212 DUMP_REG(sdma_rlc_reg_offset + reg);
213 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
214 DUMP_REG(sdma_rlc_reg_offset + reg);
215 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
216 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
217 DUMP_REG(sdma_rlc_reg_offset + reg);
218 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
219 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
220 DUMP_REG(sdma_rlc_reg_offset + reg);
221
222 WARN_ON_ONCE(i != HQD_N_REGS);
223 *n_regs = i;
224
225 return 0;
226}
227
228bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
229{
230 struct amdgpu_device *adev = get_amdgpu_device(kgd);
231 struct v9_sdma_mqd *m;
232 uint32_t sdma_rlc_reg_offset;
233 uint32_t sdma_rlc_rb_cntl;
234
235 m = get_sdma_mqd(mqd);
236 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
237 m->sdma_queue_id);
238
239 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
240
241 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
242 return true;
243
244 return false;
245}
246
247int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
248 unsigned int utimeout)
249{
250 struct amdgpu_device *adev = get_amdgpu_device(kgd);
251 struct v9_sdma_mqd *m;
252 uint32_t sdma_rlc_reg_offset;
253 uint32_t temp;
254 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
255
256 m = get_sdma_mqd(mqd);
257 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
258 m->sdma_queue_id);
259
260 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
261 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
262 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
263
264 while (true) {
265 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
266 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
267 break;
268 if (time_after(jiffies, end_jiffies)) {
269 pr_err("SDMA RLC not idle in %s\n", __func__);
270 return -ETIME;
271 }
272 usleep_range(500, 1000);
273 }
274
275 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
276 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
277 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
278 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
279
280 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
281 m->sdmax_rlcx_rb_rptr_hi =
282 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
283
284 return 0;
285}
286
287const struct kfd2kgd_calls arcturus_kfd2kgd = {
288 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
289 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
290 .init_interrupts = kgd_gfx_v9_init_interrupts,
291 .hqd_load = kgd_gfx_v9_hqd_load,
292 .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
293 .hqd_sdma_load = kgd_arcturus_hqd_sdma_load,
294 .hqd_dump = kgd_gfx_v9_hqd_dump,
295 .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump,
296 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
297 .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
298 .hqd_destroy = kgd_gfx_v9_hqd_destroy,
299 .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
300 .address_watch_disable = kgd_gfx_v9_address_watch_disable,
301 .address_watch_execute = kgd_gfx_v9_address_watch_execute,
302 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
303 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
304 .get_atc_vmid_pasid_mapping_info =
305 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
306 .set_vm_context_page_table_base =
307 kgd_gfx_v9_set_vm_context_page_table_base,
308 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy
309};
310
