LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26
  27#include <drm/drm_edid.h>
  28#include <drm/drm_fb_helper.h>
  29#include <drm/drm_dp_helper.h>
  30#include <drm/drm_probe_helper.h>
  31#include <drm/amdgpu_drm.h>
  32#include "amdgpu.h"
  33#include "atom.h"
  34#include "atombios_encoders.h"
  35#include "atombios_dp.h"
  36#include "amdgpu_connectors.h"
  37#include "amdgpu_i2c.h"
  38#include "amdgpu_display.h"
  39
  40#include <linux/pm_runtime.h>
  41
  42void amdgpu_connector_hotplug(struct drm_connector *connector)
  43{
  44        struct drm_device *dev = connector->dev;
  45        struct amdgpu_device *adev = drm_to_adev(dev);
  46        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  47
  48        /* bail if the connector does not have hpd pin, e.g.,
  49         * VGA, TV, etc.
  50         */
  51        if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  52                return;
  53
  54        amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  55
  56        /* if the connector is already off, don't turn it back on */
  57        if (connector->dpms != DRM_MODE_DPMS_ON)
  58                return;
  59
  60        /* just deal with DP (not eDP) here. */
  61        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  62                struct amdgpu_connector_atom_dig *dig_connector =
  63                        amdgpu_connector->con_priv;
  64
  65                /* if existing sink type was not DP no need to retrain */
  66                if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  67                        return;
  68
  69                /* first get sink type as it may be reset after (un)plug */
  70                dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  71                /* don't do anything if sink is not display port, i.e.,
  72                 * passive dp->(dvi|hdmi) adaptor
  73                 */
  74                if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  75                    amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  76                    amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  77                        /* Don't start link training before we have the DPCD */
  78                        if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  79                                return;
  80
  81                        /* Turn the connector off and back on immediately, which
  82                         * will trigger link training
  83                         */
  84                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  85                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  86                }
  87        }
  88}
  89
  90static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  91{
  92        struct drm_crtc *crtc = encoder->crtc;
  93
  94        if (crtc && crtc->enabled) {
  95                drm_crtc_helper_set_mode(crtc, &crtc->mode,
  96                                         crtc->x, crtc->y, crtc->primary->fb);
  97        }
  98}
  99
 100int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 101{
 102        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 103        struct amdgpu_connector_atom_dig *dig_connector;
 104        int bpc = 8;
 105        unsigned mode_clock, max_tmds_clock;
 106
 107        switch (connector->connector_type) {
 108        case DRM_MODE_CONNECTOR_DVII:
 109        case DRM_MODE_CONNECTOR_HDMIB:
 110                if (amdgpu_connector->use_digital) {
 111                        if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 112                                if (connector->display_info.bpc)
 113                                        bpc = connector->display_info.bpc;
 114                        }
 115                }
 116                break;
 117        case DRM_MODE_CONNECTOR_DVID:
 118        case DRM_MODE_CONNECTOR_HDMIA:
 119                if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 120                        if (connector->display_info.bpc)
 121                                bpc = connector->display_info.bpc;
 122                }
 123                break;
 124        case DRM_MODE_CONNECTOR_DisplayPort:
 125                dig_connector = amdgpu_connector->con_priv;
 126                if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 127                    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 128                    drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 129                        if (connector->display_info.bpc)
 130                                bpc = connector->display_info.bpc;
 131                }
 132                break;
 133        case DRM_MODE_CONNECTOR_eDP:
 134        case DRM_MODE_CONNECTOR_LVDS:
 135                if (connector->display_info.bpc)
 136                        bpc = connector->display_info.bpc;
 137                else {
 138                        const struct drm_connector_helper_funcs *connector_funcs =
 139                                connector->helper_private;
 140                        struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 141                        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 142                        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 143
 144                        if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 145                                bpc = 6;
 146                        else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 147                                bpc = 8;
 148                }
 149                break;
 150        }
 151
 152        if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 153                /*
 154                 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 155                 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 156                 * 12 bpc is always supported on hdmi deep color sinks, as this is
 157                 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 158                 */
 159                if (bpc > 12) {
 160                        DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 161                                  connector->name, bpc);
 162                        bpc = 12;
 163                }
 164
 165                /* Any defined maximum tmds clock limit we must not exceed? */
 166                if (connector->display_info.max_tmds_clock > 0) {
 167                        /* mode_clock is clock in kHz for mode to be modeset on this connector */
 168                        mode_clock = amdgpu_connector->pixelclock_for_modeset;
 169
 170                        /* Maximum allowable input clock in kHz */
 171                        max_tmds_clock = connector->display_info.max_tmds_clock;
 172
 173                        DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 174                                  connector->name, mode_clock, max_tmds_clock);
 175
 176                        /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 177                        if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 178                                if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 179                                    (mode_clock * 5/4 <= max_tmds_clock))
 180                                        bpc = 10;
 181                                else
 182                                        bpc = 8;
 183
 184                                DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 185                                          connector->name, bpc);
 186                        }
 187
 188                        if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 189                                bpc = 8;
 190                                DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 191                                          connector->name, bpc);
 192                        }
 193                } else if (bpc > 8) {
 194                        /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 195                        DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 196                                  connector->name);
 197                        bpc = 8;
 198                }
 199        }
 200
 201        if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 202                DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 203                          connector->name);
 204                bpc = 8;
 205        }
 206
 207        DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 208                  connector->name, connector->display_info.bpc, bpc);
 209
 210        return bpc;
 211}
 212
 213static void
 214amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 215                                      enum drm_connector_status status)
 216{
 217        struct drm_encoder *best_encoder;
 218        struct drm_encoder *encoder;
 219        const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 220        bool connected;
 221
 222        best_encoder = connector_funcs->best_encoder(connector);
 223
 224        drm_connector_for_each_possible_encoder(connector, encoder) {
 225                if ((encoder == best_encoder) && (status == connector_status_connected))
 226                        connected = true;
 227                else
 228                        connected = false;
 229
 230                amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 231        }
 232}
 233
 234static struct drm_encoder *
 235amdgpu_connector_find_encoder(struct drm_connector *connector,
 236                               int encoder_type)
 237{
 238        struct drm_encoder *encoder;
 239
 240        drm_connector_for_each_possible_encoder(connector, encoder) {
 241                if (encoder->encoder_type == encoder_type)
 242                        return encoder;
 243        }
 244
 245        return NULL;
 246}
 247
 248struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 249{
 250        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 251        struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 252
 253        if (amdgpu_connector->edid) {
 254                return amdgpu_connector->edid;
 255        } else if (edid_blob) {
 256                struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 257                if (edid)
 258                        amdgpu_connector->edid = edid;
 259        }
 260        return amdgpu_connector->edid;
 261}
 262
 263static struct edid *
 264amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 265{
 266        struct edid *edid;
 267
 268        if (adev->mode_info.bios_hardcoded_edid) {
 269                edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 270                if (edid) {
 271                        memcpy((unsigned char *)edid,
 272                               (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 273                               adev->mode_info.bios_hardcoded_edid_size);
 274                        return edid;
 275                }
 276        }
 277        return NULL;
 278}
 279
 280static void amdgpu_connector_get_edid(struct drm_connector *connector)
 281{
 282        struct drm_device *dev = connector->dev;
 283        struct amdgpu_device *adev = drm_to_adev(dev);
 284        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 285
 286        if (amdgpu_connector->edid)
 287                return;
 288
 289        /* on hw with routers, select right port */
 290        if (amdgpu_connector->router.ddc_valid)
 291                amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 292
 293        if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 294             ENCODER_OBJECT_ID_NONE) &&
 295            amdgpu_connector->ddc_bus->has_aux) {
 296                amdgpu_connector->edid = drm_get_edid(connector,
 297                                                      &amdgpu_connector->ddc_bus->aux.ddc);
 298        } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 299                   (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 300                struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 301
 302                if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 303                     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 304                    amdgpu_connector->ddc_bus->has_aux)
 305                        amdgpu_connector->edid = drm_get_edid(connector,
 306                                                              &amdgpu_connector->ddc_bus->aux.ddc);
 307                else if (amdgpu_connector->ddc_bus)
 308                        amdgpu_connector->edid = drm_get_edid(connector,
 309                                                              &amdgpu_connector->ddc_bus->adapter);
 310        } else if (amdgpu_connector->ddc_bus) {
 311                amdgpu_connector->edid = drm_get_edid(connector,
 312                                                      &amdgpu_connector->ddc_bus->adapter);
 313        }
 314
 315        if (!amdgpu_connector->edid) {
 316                /* some laptops provide a hardcoded edid in rom for LCDs */
 317                if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 318                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 319                        amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 320        }
 321}
 322
 323static void amdgpu_connector_free_edid(struct drm_connector *connector)
 324{
 325        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 326
 327        kfree(amdgpu_connector->edid);
 328        amdgpu_connector->edid = NULL;
 329}
 330
 331static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 332{
 333        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 334        int ret;
 335
 336        if (amdgpu_connector->edid) {
 337                drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 338                ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 339                return ret;
 340        }
 341        drm_connector_update_edid_property(connector, NULL);
 342        return 0;
 343}
 344
 345static struct drm_encoder *
 346amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 347{
 348        struct drm_encoder *encoder;
 349
 350        /* pick the first one */
 351        drm_connector_for_each_possible_encoder(connector, encoder)
 352                return encoder;
 353
 354        return NULL;
 355}
 356
 357static void amdgpu_get_native_mode(struct drm_connector *connector)
 358{
 359        struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 360        struct amdgpu_encoder *amdgpu_encoder;
 361
 362        if (encoder == NULL)
 363                return;
 364
 365        amdgpu_encoder = to_amdgpu_encoder(encoder);
 366
 367        if (!list_empty(&connector->probed_modes)) {
 368                struct drm_display_mode *preferred_mode =
 369                        list_first_entry(&connector->probed_modes,
 370                                         struct drm_display_mode, head);
 371
 372                amdgpu_encoder->native_mode = *preferred_mode;
 373        } else {
 374                amdgpu_encoder->native_mode.clock = 0;
 375        }
 376}
 377
 378static struct drm_display_mode *
 379amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 380{
 381        struct drm_device *dev = encoder->dev;
 382        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 383        struct drm_display_mode *mode = NULL;
 384        struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 385
 386        if (native_mode->hdisplay != 0 &&
 387            native_mode->vdisplay != 0 &&
 388            native_mode->clock != 0) {
 389                mode = drm_mode_duplicate(dev, native_mode);
 390                if (!mode)
 391                        return NULL;
 392
 393                mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 394                drm_mode_set_name(mode);
 395
 396                DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 397        } else if (native_mode->hdisplay != 0 &&
 398                   native_mode->vdisplay != 0) {
 399                /* mac laptops without an edid */
 400                /* Note that this is not necessarily the exact panel mode,
 401                 * but an approximation based on the cvt formula.  For these
 402                 * systems we should ideally read the mode info out of the
 403                 * registers or add a mode table, but this works and is much
 404                 * simpler.
 405                 */
 406                mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 407                if (!mode)
 408                        return NULL;
 409
 410                mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 411                DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 412        }
 413        return mode;
 414}
 415
 416static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 417                                               struct drm_connector *connector)
 418{
 419        struct drm_device *dev = encoder->dev;
 420        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 421        struct drm_display_mode *mode = NULL;
 422        struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 423        int i;
 424        static const struct mode_size {
 425                int w;
 426                int h;
 427        } common_modes[17] = {
 428                { 640,  480},
 429                { 720,  480},
 430                { 800,  600},
 431                { 848,  480},
 432                {1024,  768},
 433                {1152,  768},
 434                {1280,  720},
 435                {1280,  800},
 436                {1280,  854},
 437                {1280,  960},
 438                {1280, 1024},
 439                {1440,  900},
 440                {1400, 1050},
 441                {1680, 1050},
 442                {1600, 1200},
 443                {1920, 1080},
 444                {1920, 1200}
 445        };
 446
 447        for (i = 0; i < 17; i++) {
 448                if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 449                        if (common_modes[i].w > 1024 ||
 450                            common_modes[i].h > 768)
 451                                continue;
 452                }
 453                if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 454                        if (common_modes[i].w > native_mode->hdisplay ||
 455                            common_modes[i].h > native_mode->vdisplay ||
 456                            (common_modes[i].w == native_mode->hdisplay &&
 457                             common_modes[i].h == native_mode->vdisplay))
 458                                continue;
 459                }
 460                if (common_modes[i].w < 320 || common_modes[i].h < 200)
 461                        continue;
 462
 463                mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 464                drm_mode_probed_add(connector, mode);
 465        }
 466}
 467
 468static int amdgpu_connector_set_property(struct drm_connector *connector,
 469                                          struct drm_property *property,
 470                                          uint64_t val)
 471{
 472        struct drm_device *dev = connector->dev;
 473        struct amdgpu_device *adev = drm_to_adev(dev);
 474        struct drm_encoder *encoder;
 475        struct amdgpu_encoder *amdgpu_encoder;
 476
 477        if (property == adev->mode_info.coherent_mode_property) {
 478                struct amdgpu_encoder_atom_dig *dig;
 479                bool new_coherent_mode;
 480
 481                /* need to find digital encoder on connector */
 482                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 483                if (!encoder)
 484                        return 0;
 485
 486                amdgpu_encoder = to_amdgpu_encoder(encoder);
 487
 488                if (!amdgpu_encoder->enc_priv)
 489                        return 0;
 490
 491                dig = amdgpu_encoder->enc_priv;
 492                new_coherent_mode = val ? true : false;
 493                if (dig->coherent_mode != new_coherent_mode) {
 494                        dig->coherent_mode = new_coherent_mode;
 495                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 496                }
 497        }
 498
 499        if (property == adev->mode_info.audio_property) {
 500                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 501                /* need to find digital encoder on connector */
 502                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 503                if (!encoder)
 504                        return 0;
 505
 506                amdgpu_encoder = to_amdgpu_encoder(encoder);
 507
 508                if (amdgpu_connector->audio != val) {
 509                        amdgpu_connector->audio = val;
 510                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 511                }
 512        }
 513
 514        if (property == adev->mode_info.dither_property) {
 515                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 516                /* need to find digital encoder on connector */
 517                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 518                if (!encoder)
 519                        return 0;
 520
 521                amdgpu_encoder = to_amdgpu_encoder(encoder);
 522
 523                if (amdgpu_connector->dither != val) {
 524                        amdgpu_connector->dither = val;
 525                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 526                }
 527        }
 528
 529        if (property == adev->mode_info.underscan_property) {
 530                /* need to find digital encoder on connector */
 531                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 532                if (!encoder)
 533                        return 0;
 534
 535                amdgpu_encoder = to_amdgpu_encoder(encoder);
 536
 537                if (amdgpu_encoder->underscan_type != val) {
 538                        amdgpu_encoder->underscan_type = val;
 539                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 540                }
 541        }
 542
 543        if (property == adev->mode_info.underscan_hborder_property) {
 544                /* need to find digital encoder on connector */
 545                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 546                if (!encoder)
 547                        return 0;
 548
 549                amdgpu_encoder = to_amdgpu_encoder(encoder);
 550
 551                if (amdgpu_encoder->underscan_hborder != val) {
 552                        amdgpu_encoder->underscan_hborder = val;
 553                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 554                }
 555        }
 556
 557        if (property == adev->mode_info.underscan_vborder_property) {
 558                /* need to find digital encoder on connector */
 559                encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 560                if (!encoder)
 561                        return 0;
 562
 563                amdgpu_encoder = to_amdgpu_encoder(encoder);
 564
 565                if (amdgpu_encoder->underscan_vborder != val) {
 566                        amdgpu_encoder->underscan_vborder = val;
 567                        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 568                }
 569        }
 570
 571        if (property == adev->mode_info.load_detect_property) {
 572                struct amdgpu_connector *amdgpu_connector =
 573                        to_amdgpu_connector(connector);
 574
 575                if (val == 0)
 576                        amdgpu_connector->dac_load_detect = false;
 577                else
 578                        amdgpu_connector->dac_load_detect = true;
 579        }
 580
 581        if (property == dev->mode_config.scaling_mode_property) {
 582                enum amdgpu_rmx_type rmx_type;
 583
 584                if (connector->encoder) {
 585                        amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 586                } else {
 587                        const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 588                        amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 589                }
 590
 591                switch (val) {
 592                default:
 593                case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 594                case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 595                case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 596                case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 597                }
 598                if (amdgpu_encoder->rmx_type == rmx_type)
 599                        return 0;
 600
 601                if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 602                    (amdgpu_encoder->native_mode.clock == 0))
 603                        return 0;
 604
 605                amdgpu_encoder->rmx_type = rmx_type;
 606
 607                amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 608        }
 609
 610        return 0;
 611}
 612
 613static void
 614amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 615                                        struct drm_connector *connector)
 616{
 617        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 618        struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 619        struct drm_display_mode *t, *mode;
 620
 621        /* If the EDID preferred mode doesn't match the native mode, use it */
 622        list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 623                if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 624                        if (mode->hdisplay != native_mode->hdisplay ||
 625                            mode->vdisplay != native_mode->vdisplay)
 626                                memcpy(native_mode, mode, sizeof(*mode));
 627                }
 628        }
 629
 630        /* Try to get native mode details from EDID if necessary */
 631        if (!native_mode->clock) {
 632                list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 633                        if (mode->hdisplay == native_mode->hdisplay &&
 634                            mode->vdisplay == native_mode->vdisplay) {
 635                                *native_mode = *mode;
 636                                drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 637                                DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 638                                break;
 639                        }
 640                }
 641        }
 642
 643        if (!native_mode->clock) {
 644                DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 645                amdgpu_encoder->rmx_type = RMX_OFF;
 646        }
 647}
 648
 649static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 650{
 651        struct drm_encoder *encoder;
 652        int ret = 0;
 653        struct drm_display_mode *mode;
 654
 655        amdgpu_connector_get_edid(connector);
 656        ret = amdgpu_connector_ddc_get_modes(connector);
 657        if (ret > 0) {
 658                encoder = amdgpu_connector_best_single_encoder(connector);
 659                if (encoder) {
 660                        amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 661                        /* add scaled modes */
 662                        amdgpu_connector_add_common_modes(encoder, connector);
 663                }
 664                return ret;
 665        }
 666
 667        encoder = amdgpu_connector_best_single_encoder(connector);
 668        if (!encoder)
 669                return 0;
 670
 671        /* we have no EDID modes */
 672        mode = amdgpu_connector_lcd_native_mode(encoder);
 673        if (mode) {
 674                ret = 1;
 675                drm_mode_probed_add(connector, mode);
 676                /* add the width/height from vbios tables if available */
 677                connector->display_info.width_mm = mode->width_mm;
 678                connector->display_info.height_mm = mode->height_mm;
 679                /* add scaled modes */
 680                amdgpu_connector_add_common_modes(encoder, connector);
 681        }
 682
 683        return ret;
 684}
 685
 686static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 687                                             struct drm_display_mode *mode)
 688{
 689        struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 690
 691        if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 692                return MODE_PANEL;
 693
 694        if (encoder) {
 695                struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 696                struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 697
 698                /* AVIVO hardware supports downscaling modes larger than the panel
 699                 * to the panel size, but I'm not sure this is desirable.
 700                 */
 701                if ((mode->hdisplay > native_mode->hdisplay) ||
 702                    (mode->vdisplay > native_mode->vdisplay))
 703                        return MODE_PANEL;
 704
 705                /* if scaling is disabled, block non-native modes */
 706                if (amdgpu_encoder->rmx_type == RMX_OFF) {
 707                        if ((mode->hdisplay != native_mode->hdisplay) ||
 708                            (mode->vdisplay != native_mode->vdisplay))
 709                                return MODE_PANEL;
 710                }
 711        }
 712
 713        return MODE_OK;
 714}
 715
 716static enum drm_connector_status
 717amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 718{
 719        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 720        struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 721        enum drm_connector_status ret = connector_status_disconnected;
 722        int r;
 723
 724        if (!drm_kms_helper_is_poll_worker()) {
 725                r = pm_runtime_get_sync(connector->dev->dev);
 726                if (r < 0) {
 727                        pm_runtime_put_autosuspend(connector->dev->dev);
 728                        return connector_status_disconnected;
 729                }
 730        }
 731
 732        if (encoder) {
 733                struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 734                struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 735
 736                /* check if panel is valid */
 737                if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 738                        ret = connector_status_connected;
 739
 740        }
 741
 742        /* check for edid as well */
 743        amdgpu_connector_get_edid(connector);
 744        if (amdgpu_connector->edid)
 745                ret = connector_status_connected;
 746        /* check acpi lid status ??? */
 747
 748        amdgpu_connector_update_scratch_regs(connector, ret);
 749
 750        if (!drm_kms_helper_is_poll_worker()) {
 751                pm_runtime_mark_last_busy(connector->dev->dev);
 752                pm_runtime_put_autosuspend(connector->dev->dev);
 753        }
 754
 755        return ret;
 756}
 757
 758static void amdgpu_connector_unregister(struct drm_connector *connector)
 759{
 760        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 761
 762        if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 763                drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 764                amdgpu_connector->ddc_bus->has_aux = false;
 765        }
 766}
 767
 768static void amdgpu_connector_destroy(struct drm_connector *connector)
 769{
 770        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 771
 772        amdgpu_connector_free_edid(connector);
 773        kfree(amdgpu_connector->con_priv);
 774        drm_connector_unregister(connector);
 775        drm_connector_cleanup(connector);
 776        kfree(connector);
 777}
 778
 779static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 780                                              struct drm_property *property,
 781                                              uint64_t value)
 782{
 783        struct drm_device *dev = connector->dev;
 784        struct amdgpu_encoder *amdgpu_encoder;
 785        enum amdgpu_rmx_type rmx_type;
 786
 787        DRM_DEBUG_KMS("\n");
 788        if (property != dev->mode_config.scaling_mode_property)
 789                return 0;
 790
 791        if (connector->encoder)
 792                amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 793        else {
 794                const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 795                amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 796        }
 797
 798        switch (value) {
 799        case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 800        case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 801        case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 802        default:
 803        case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 804        }
 805        if (amdgpu_encoder->rmx_type == rmx_type)
 806                return 0;
 807
 808        amdgpu_encoder->rmx_type = rmx_type;
 809
 810        amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 811        return 0;
 812}
 813
 814
 815static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 816        .get_modes = amdgpu_connector_lvds_get_modes,
 817        .mode_valid = amdgpu_connector_lvds_mode_valid,
 818        .best_encoder = amdgpu_connector_best_single_encoder,
 819};
 820
 821static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 822        .dpms = drm_helper_connector_dpms,
 823        .detect = amdgpu_connector_lvds_detect,
 824        .fill_modes = drm_helper_probe_single_connector_modes,
 825        .early_unregister = amdgpu_connector_unregister,
 826        .destroy = amdgpu_connector_destroy,
 827        .set_property = amdgpu_connector_set_lcd_property,
 828};
 829
 830static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 831{
 832        int ret;
 833
 834        amdgpu_connector_get_edid(connector);
 835        ret = amdgpu_connector_ddc_get_modes(connector);
 836        amdgpu_get_native_mode(connector);
 837
 838        return ret;
 839}
 840
 841static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 842                                            struct drm_display_mode *mode)
 843{
 844        struct drm_device *dev = connector->dev;
 845        struct amdgpu_device *adev = drm_to_adev(dev);
 846
 847        /* XXX check mode bandwidth */
 848
 849        if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 850                return MODE_CLOCK_HIGH;
 851
 852        return MODE_OK;
 853}
 854
 855static enum drm_connector_status
 856amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 857{
 858        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 859        struct drm_encoder *encoder;
 860        const struct drm_encoder_helper_funcs *encoder_funcs;
 861        bool dret = false;
 862        enum drm_connector_status ret = connector_status_disconnected;
 863        int r;
 864
 865        if (!drm_kms_helper_is_poll_worker()) {
 866                r = pm_runtime_get_sync(connector->dev->dev);
 867                if (r < 0) {
 868                        pm_runtime_put_autosuspend(connector->dev->dev);
 869                        return connector_status_disconnected;
 870                }
 871        }
 872
 873        encoder = amdgpu_connector_best_single_encoder(connector);
 874        if (!encoder)
 875                ret = connector_status_disconnected;
 876
 877        if (amdgpu_connector->ddc_bus)
 878                dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 879        if (dret) {
 880                amdgpu_connector->detected_by_load = false;
 881                amdgpu_connector_free_edid(connector);
 882                amdgpu_connector_get_edid(connector);
 883
 884                if (!amdgpu_connector->edid) {
 885                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 886                                        connector->name);
 887                        ret = connector_status_connected;
 888                } else {
 889                        amdgpu_connector->use_digital =
 890                                !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 891
 892                        /* some oems have boards with separate digital and analog connectors
 893                         * with a shared ddc line (often vga + hdmi)
 894                         */
 895                        if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 896                                amdgpu_connector_free_edid(connector);
 897                                ret = connector_status_disconnected;
 898                        } else {
 899                                ret = connector_status_connected;
 900                        }
 901                }
 902        } else {
 903
 904                /* if we aren't forcing don't do destructive polling */
 905                if (!force) {
 906                        /* only return the previous status if we last
 907                         * detected a monitor via load.
 908                         */
 909                        if (amdgpu_connector->detected_by_load)
 910                                ret = connector->status;
 911                        goto out;
 912                }
 913
 914                if (amdgpu_connector->dac_load_detect && encoder) {
 915                        encoder_funcs = encoder->helper_private;
 916                        ret = encoder_funcs->detect(encoder, connector);
 917                        if (ret != connector_status_disconnected)
 918                                amdgpu_connector->detected_by_load = true;
 919                }
 920        }
 921
 922        amdgpu_connector_update_scratch_regs(connector, ret);
 923
 924out:
 925        if (!drm_kms_helper_is_poll_worker()) {
 926                pm_runtime_mark_last_busy(connector->dev->dev);
 927                pm_runtime_put_autosuspend(connector->dev->dev);
 928        }
 929
 930        return ret;
 931}
 932
 933static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 934        .get_modes = amdgpu_connector_vga_get_modes,
 935        .mode_valid = amdgpu_connector_vga_mode_valid,
 936        .best_encoder = amdgpu_connector_best_single_encoder,
 937};
 938
 939static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 940        .dpms = drm_helper_connector_dpms,
 941        .detect = amdgpu_connector_vga_detect,
 942        .fill_modes = drm_helper_probe_single_connector_modes,
 943        .early_unregister = amdgpu_connector_unregister,
 944        .destroy = amdgpu_connector_destroy,
 945        .set_property = amdgpu_connector_set_property,
 946};
 947
 948static bool
 949amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 950{
 951        struct drm_device *dev = connector->dev;
 952        struct amdgpu_device *adev = drm_to_adev(dev);
 953        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 954        enum drm_connector_status status;
 955
 956        if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 957                if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 958                        status = connector_status_connected;
 959                else
 960                        status = connector_status_disconnected;
 961                if (connector->status == status)
 962                        return true;
 963        }
 964
 965        return false;
 966}
 967
 968/*
 969 * DVI is complicated
 970 * Do a DDC probe, if DDC probe passes, get the full EDID so
 971 * we can do analog/digital monitor detection at this point.
 972 * If the monitor is an analog monitor or we got no DDC,
 973 * we need to find the DAC encoder object for this connector.
 974 * If we got no DDC, we do load detection on the DAC encoder object.
 975 * If we got analog DDC or load detection passes on the DAC encoder
 976 * we have to check if this analog encoder is shared with anyone else (TV)
 977 * if its shared we have to set the other connector to disconnected.
 978 */
 979static enum drm_connector_status
 980amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 981{
 982        struct drm_device *dev = connector->dev;
 983        struct amdgpu_device *adev = drm_to_adev(dev);
 984        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 985        const struct drm_encoder_helper_funcs *encoder_funcs;
 986        int r;
 987        enum drm_connector_status ret = connector_status_disconnected;
 988        bool dret = false, broken_edid = false;
 989
 990        if (!drm_kms_helper_is_poll_worker()) {
 991                r = pm_runtime_get_sync(connector->dev->dev);
 992                if (r < 0) {
 993                        pm_runtime_put_autosuspend(connector->dev->dev);
 994                        return connector_status_disconnected;
 995                }
 996        }
 997
 998        if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
 999                ret = connector->status;
1000                goto exit;

1001        }
1002
1003        if (amdgpu_connector->ddc_bus)
1004                dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1005        if (dret) {
1006                amdgpu_connector->detected_by_load = false;
1007                amdgpu_connector_free_edid(connector);
1008                amdgpu_connector_get_edid(connector);
1009
1010                if (!amdgpu_connector->edid) {
1011                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1012                                        connector->name);
1013                        ret = connector_status_connected;
1014                        broken_edid = true; /* defer use_digital to later */
1015                } else {
1016                        amdgpu_connector->use_digital =
1017                                !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1018
1019                        /* some oems have boards with separate digital and analog connectors
1020                         * with a shared ddc line (often vga + hdmi)
1021                         */
1022                        if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1023                                amdgpu_connector_free_edid(connector);
1024                                ret = connector_status_disconnected;
1025                        } else {
1026                                ret = connector_status_connected;
1027                        }
1028
1029                        /* This gets complicated.  We have boards with VGA + HDMI with a
1030                         * shared DDC line and we have boards with DVI-D + HDMI with a shared
1031                         * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1032                         * you don't really know what's connected to which port as both are digital.
1033                         */
1034                        if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1035                                struct drm_connector *list_connector;
1036                                struct drm_connector_list_iter iter;
1037                                struct amdgpu_connector *list_amdgpu_connector;
1038
1039                                drm_connector_list_iter_begin(dev, &iter);
1040                                drm_for_each_connector_iter(list_connector,
1041                                                            &iter) {
1042                                        if (connector == list_connector)
1043                                                continue;
1044                                        list_amdgpu_connector = to_amdgpu_connector(list_connector);
1045                                        if (list_amdgpu_connector->shared_ddc &&
1046                                            (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1047                                             amdgpu_connector->ddc_bus->rec.i2c_id)) {
1048                                                /* cases where both connectors are digital */
1049                                                if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1050                                                        /* hpd is our only option in this case */
1051                                                        if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1052                                                                amdgpu_connector_free_edid(connector);
1053                                                                ret = connector_status_disconnected;
1054                                                        }
1055                                                }
1056                                        }
1057                                }
1058                                drm_connector_list_iter_end(&iter);
1059                        }
1060                }
1061        }
1062
1063        if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1064                goto out;
1065
1066        /* DVI-D and HDMI-A are digital only */
1067        if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1068            (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1069                goto out;
1070
1071        /* if we aren't forcing don't do destructive polling */
1072        if (!force) {
1073                /* only return the previous status if we last
1074                 * detected a monitor via load.
1075                 */
1076                if (amdgpu_connector->detected_by_load)
1077                        ret = connector->status;
1078                goto out;
1079        }
1080
1081        /* find analog encoder */
1082        if (amdgpu_connector->dac_load_detect) {
1083                struct drm_encoder *encoder;
1084
1085                drm_connector_for_each_possible_encoder(connector, encoder) {
1086                        if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1087                            encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1088                                continue;
1089
1090                        encoder_funcs = encoder->helper_private;
1091                        if (encoder_funcs->detect) {
1092                                if (!broken_edid) {
1093                                        if (ret != connector_status_connected) {
1094                                                /* deal with analog monitors without DDC */
1095                                                ret = encoder_funcs->detect(encoder, connector);
1096                                                if (ret == connector_status_connected) {
1097                                                        amdgpu_connector->use_digital = false;
1098                                                }
1099                                                if (ret != connector_status_disconnected)
1100                                                        amdgpu_connector->detected_by_load = true;
1101                                        }
1102                                } else {
1103                                        enum drm_connector_status lret;
1104                                        /* assume digital unless load detected otherwise */
1105                                        amdgpu_connector->use_digital = true;
1106                                        lret = encoder_funcs->detect(encoder, connector);
1107                                        DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1108                                        if (lret == connector_status_connected)
1109                                                amdgpu_connector->use_digital = false;
1110                                }
1111                                break;
1112                        }
1113                }
1114        }
1115
1116out:
1117        /* updated in get modes as well since we need to know if it's analog or digital */
1118        amdgpu_connector_update_scratch_regs(connector, ret);
1119
1120exit:
1121        if (!drm_kms_helper_is_poll_worker()) {
1122                pm_runtime_mark_last_busy(connector->dev->dev);
1123                pm_runtime_put_autosuspend(connector->dev->dev);
1124        }
1125
1126        return ret;
1127}
1128
1129/* okay need to be smart in here about which encoder to pick */
1130static struct drm_encoder *
1131amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1132{
1133        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1134        struct drm_encoder *encoder;
1135
1136        drm_connector_for_each_possible_encoder(connector, encoder) {
1137                if (amdgpu_connector->use_digital == true) {
1138                        if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1139                                return encoder;
1140                } else {
1141                        if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1142                            encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1143                                return encoder;
1144                }
1145        }
1146
1147        /* see if we have a default encoder  TODO */
1148
1149        /* then check use digitial */
1150        /* pick the first one */
1151        drm_connector_for_each_possible_encoder(connector, encoder)
1152                return encoder;
1153
1154        return NULL;
1155}
1156
1157static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1158{
1159        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1160        if (connector->force == DRM_FORCE_ON)
1161                amdgpu_connector->use_digital = false;
1162        if (connector->force == DRM_FORCE_ON_DIGITAL)
1163                amdgpu_connector->use_digital = true;
1164}
1165
1166static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1167                                            struct drm_display_mode *mode)
1168{
1169        struct drm_device *dev = connector->dev;
1170        struct amdgpu_device *adev = drm_to_adev(dev);
1171        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1172
1173        /* XXX check mode bandwidth */
1174
1175        if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1176                if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1177                    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1178                    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1179                        return MODE_OK;
1180                } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1181                        /* HDMI 1.3+ supports max clock of 340 Mhz */
1182                        if (mode->clock > 340000)
1183                                return MODE_CLOCK_HIGH;
1184                        else
1185                                return MODE_OK;
1186                } else {
1187                        return MODE_CLOCK_HIGH;
1188                }
1189        }
1190
1191        /* check against the max pixel clock */
1192        if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1193                return MODE_CLOCK_HIGH;
1194
1195        return MODE_OK;
1196}
1197
1198static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1199        .get_modes = amdgpu_connector_vga_get_modes,
1200        .mode_valid = amdgpu_connector_dvi_mode_valid,
1201        .best_encoder = amdgpu_connector_dvi_encoder,
1202};
1203
1204static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1205        .dpms = drm_helper_connector_dpms,
1206        .detect = amdgpu_connector_dvi_detect,
1207        .fill_modes = drm_helper_probe_single_connector_modes,
1208        .set_property = amdgpu_connector_set_property,
1209        .early_unregister = amdgpu_connector_unregister,
1210        .destroy = amdgpu_connector_destroy,
1211        .force = amdgpu_connector_dvi_force,
1212};
1213
1214static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1215{
1216        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1217        struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1218        struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1219        int ret;
1220
1221        if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1222            (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1223                struct drm_display_mode *mode;
1224
1225                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1226                        if (!amdgpu_dig_connector->edp_on)
1227                                amdgpu_atombios_encoder_set_edp_panel_power(connector,
1228                                                                     ATOM_TRANSMITTER_ACTION_POWER_ON);
1229                        amdgpu_connector_get_edid(connector);
1230                        ret = amdgpu_connector_ddc_get_modes(connector);
1231                        if (!amdgpu_dig_connector->edp_on)
1232                                amdgpu_atombios_encoder_set_edp_panel_power(connector,
1233                                                                     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1234                } else {
1235                        /* need to setup ddc on the bridge */
1236                        if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1237                            ENCODER_OBJECT_ID_NONE) {
1238                                if (encoder)
1239                                        amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1240                        }
1241                        amdgpu_connector_get_edid(connector);
1242                        ret = amdgpu_connector_ddc_get_modes(connector);
1243                }
1244
1245                if (ret > 0) {
1246                        if (encoder) {
1247                                amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1248                                /* add scaled modes */
1249                                amdgpu_connector_add_common_modes(encoder, connector);
1250                        }
1251                        return ret;
1252                }
1253
1254                if (!encoder)
1255                        return 0;
1256
1257                /* we have no EDID modes */
1258                mode = amdgpu_connector_lcd_native_mode(encoder);
1259                if (mode) {
1260                        ret = 1;
1261                        drm_mode_probed_add(connector, mode);
1262                        /* add the width/height from vbios tables if available */
1263                        connector->display_info.width_mm = mode->width_mm;
1264                        connector->display_info.height_mm = mode->height_mm;
1265                        /* add scaled modes */
1266                        amdgpu_connector_add_common_modes(encoder, connector);
1267                }
1268        } else {
1269                /* need to setup ddc on the bridge */
1270                if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1271                        ENCODER_OBJECT_ID_NONE) {
1272                        if (encoder)
1273                                amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1274                }
1275                amdgpu_connector_get_edid(connector);
1276                ret = amdgpu_connector_ddc_get_modes(connector);
1277
1278                amdgpu_get_native_mode(connector);
1279        }
1280
1281        return ret;
1282}
1283
1284u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1285{
1286        struct drm_encoder *encoder;
1287        struct amdgpu_encoder *amdgpu_encoder;
1288
1289        drm_connector_for_each_possible_encoder(connector, encoder) {
1290                amdgpu_encoder = to_amdgpu_encoder(encoder);
1291
1292                switch (amdgpu_encoder->encoder_id) {
1293                case ENCODER_OBJECT_ID_TRAVIS:
1294                case ENCODER_OBJECT_ID_NUTMEG:
1295                        return amdgpu_encoder->encoder_id;
1296                default:
1297                        break;
1298                }
1299        }
1300
1301        return ENCODER_OBJECT_ID_NONE;
1302}
1303
1304static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1305{
1306        struct drm_encoder *encoder;
1307        struct amdgpu_encoder *amdgpu_encoder;
1308        bool found = false;
1309
1310        drm_connector_for_each_possible_encoder(connector, encoder) {
1311                amdgpu_encoder = to_amdgpu_encoder(encoder);
1312                if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1313                        found = true;
1314        }
1315
1316        return found;
1317}
1318
1319bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1320{
1321        struct drm_device *dev = connector->dev;
1322        struct amdgpu_device *adev = drm_to_adev(dev);
1323
1324        if ((adev->clock.default_dispclk >= 53900) &&
1325            amdgpu_connector_encoder_is_hbr2(connector)) {
1326                return true;
1327        }
1328
1329        return false;
1330}
1331
1332static enum drm_connector_status
1333amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1334{
1335        struct drm_device *dev = connector->dev;
1336        struct amdgpu_device *adev = drm_to_adev(dev);
1337        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1338        enum drm_connector_status ret = connector_status_disconnected;
1339        struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1340        struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1341        int r;
1342
1343        if (!drm_kms_helper_is_poll_worker()) {
1344                r = pm_runtime_get_sync(connector->dev->dev);
1345                if (r < 0) {
1346                        pm_runtime_put_autosuspend(connector->dev->dev);
1347                        return connector_status_disconnected;
1348                }
1349        }
1350
1351        if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1352                ret = connector->status;
1353                goto out;
1354        }
1355
1356        amdgpu_connector_free_edid(connector);
1357
1358        if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1359            (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1360                if (encoder) {
1361                        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1362                        struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1363
1364                        /* check if panel is valid */
1365                        if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1366                                ret = connector_status_connected;
1367                }
1368                /* eDP is always DP */
1369                amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1370                if (!amdgpu_dig_connector->edp_on)
1371                        amdgpu_atombios_encoder_set_edp_panel_power(connector,
1372                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
1373                if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1374                        ret = connector_status_connected;
1375                if (!amdgpu_dig_connector->edp_on)
1376                        amdgpu_atombios_encoder_set_edp_panel_power(connector,
1377                                                             ATOM_TRANSMITTER_ACTION_POWER_OFF);
1378        } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1379                   ENCODER_OBJECT_ID_NONE) {
1380                /* DP bridges are always DP */
1381                amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1382                /* get the DPCD from the bridge */
1383                amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1384
1385                if (encoder) {
1386                        /* setup ddc on the bridge */
1387                        amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1388                        /* bridge chips are always aux */
1389                        /* try DDC */
1390                        if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1391                                ret = connector_status_connected;
1392                        else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1393                                const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1394                                ret = encoder_funcs->detect(encoder, connector);
1395                        }
1396                }
1397        } else {
1398                amdgpu_dig_connector->dp_sink_type =
1399                        amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1400                if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1401                        ret = connector_status_connected;
1402                        if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1403                                amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1404                } else {
1405                        if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1406                                if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1407                                        ret = connector_status_connected;
1408                        } else {
1409                                /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1410                                if (amdgpu_display_ddc_probe(amdgpu_connector,
1411                                                             false))
1412                                        ret = connector_status_connected;
1413                        }
1414                }
1415        }
1416
1417        amdgpu_connector_update_scratch_regs(connector, ret);
1418out:
1419        if (!drm_kms_helper_is_poll_worker()) {
1420                pm_runtime_mark_last_busy(connector->dev->dev);
1421                pm_runtime_put_autosuspend(connector->dev->dev);
1422        }
1423
1424        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1425            connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1426                drm_dp_set_subconnector_property(&amdgpu_connector->base,
1427                                                 ret,
1428                                                 amdgpu_dig_connector->dpcd,
1429                                                 amdgpu_dig_connector->downstream_ports);
1430        return ret;
1431}
1432
1433static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1434                                           struct drm_display_mode *mode)
1435{
1436        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1437        struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1438
1439        /* XXX check mode bandwidth */
1440
1441        if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1442            (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1443                struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1444
1445                if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1446                        return MODE_PANEL;
1447
1448                if (encoder) {
1449                        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1450                        struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1451
1452                        /* AVIVO hardware supports downscaling modes larger than the panel
1453                         * to the panel size, but I'm not sure this is desirable.
1454                         */
1455                        if ((mode->hdisplay > native_mode->hdisplay) ||
1456                            (mode->vdisplay > native_mode->vdisplay))
1457                                return MODE_PANEL;
1458
1459                        /* if scaling is disabled, block non-native modes */
1460                        if (amdgpu_encoder->rmx_type == RMX_OFF) {
1461                                if ((mode->hdisplay != native_mode->hdisplay) ||
1462                                    (mode->vdisplay != native_mode->vdisplay))
1463                                        return MODE_PANEL;
1464                        }
1465                }
1466                return MODE_OK;
1467        } else {
1468                if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1469                    (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1470                        return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1471                } else {
1472                        if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1473                                /* HDMI 1.3+ supports max clock of 340 Mhz */
1474                                if (mode->clock > 340000)
1475                                        return MODE_CLOCK_HIGH;
1476                        } else {
1477                                if (mode->clock > 165000)
1478                                        return MODE_CLOCK_HIGH;
1479                        }
1480                }
1481        }
1482
1483        return MODE_OK;
1484}
1485
1486static int
1487amdgpu_connector_late_register(struct drm_connector *connector)
1488{
1489        struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1490        int r = 0;
1491
1492        if (amdgpu_connector->ddc_bus->has_aux) {
1493                amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1494                r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1495        }
1496
1497        return r;
1498}
1499
1500static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1501        .get_modes = amdgpu_connector_dp_get_modes,
1502        .mode_valid = amdgpu_connector_dp_mode_valid,
1503        .best_encoder = amdgpu_connector_dvi_encoder,
1504};
1505
1506static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1507        .dpms = drm_helper_connector_dpms,
1508        .detect = amdgpu_connector_dp_detect,
1509        .fill_modes = drm_helper_probe_single_connector_modes,
1510        .set_property = amdgpu_connector_set_property,
1511        .early_unregister = amdgpu_connector_unregister,
1512        .destroy = amdgpu_connector_destroy,
1513        .force = amdgpu_connector_dvi_force,
1514        .late_register = amdgpu_connector_late_register,
1515};
1516
1517static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1518        .dpms = drm_helper_connector_dpms,
1519        .detect = amdgpu_connector_dp_detect,
1520        .fill_modes = drm_helper_probe_single_connector_modes,
1521        .set_property = amdgpu_connector_set_lcd_property,
1522        .early_unregister = amdgpu_connector_unregister,
1523        .destroy = amdgpu_connector_destroy,
1524        .force = amdgpu_connector_dvi_force,
1525        .late_register = amdgpu_connector_late_register,
1526};
1527
1528void
1529amdgpu_connector_add(struct amdgpu_device *adev,
1530                      uint32_t connector_id,
1531                      uint32_t supported_device,
1532                      int connector_type,
1533                      struct amdgpu_i2c_bus_rec *i2c_bus,
1534                      uint16_t connector_object_id,
1535                      struct amdgpu_hpd *hpd,
1536                      struct amdgpu_router *router)
1537{
1538        struct drm_device *dev = adev_to_drm(adev);
1539        struct drm_connector *connector;
1540        struct drm_connector_list_iter iter;
1541        struct amdgpu_connector *amdgpu_connector;
1542        struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1543        struct drm_encoder *encoder;
1544        struct amdgpu_encoder *amdgpu_encoder;
1545        struct i2c_adapter *ddc = NULL;
1546        uint32_t subpixel_order = SubPixelNone;
1547        bool shared_ddc = false;
1548        bool is_dp_bridge = false;
1549        bool has_aux = false;
1550
1551        if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1552                return;
1553
1554        /* see if we already added it */
1555        drm_connector_list_iter_begin(dev, &iter);
1556        drm_for_each_connector_iter(connector, &iter) {
1557                amdgpu_connector = to_amdgpu_connector(connector);
1558                if (amdgpu_connector->connector_id == connector_id) {
1559                        amdgpu_connector->devices |= supported_device;
1560                        drm_connector_list_iter_end(&iter);
1561                        return;
1562                }
1563                if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1564                        if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1565                                amdgpu_connector->shared_ddc = true;
1566                                shared_ddc = true;
1567                        }
1568                        if (amdgpu_connector->router_bus && router->ddc_valid &&
1569                            (amdgpu_connector->router.router_id == router->router_id)) {
1570                                amdgpu_connector->shared_ddc = false;
1571                                shared_ddc = false;
1572                        }
1573                }
1574        }
1575        drm_connector_list_iter_end(&iter);
1576
1577        /* check if it's a dp bridge */
1578        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1579                amdgpu_encoder = to_amdgpu_encoder(encoder);
1580                if (amdgpu_encoder->devices & supported_device) {
1581                        switch (amdgpu_encoder->encoder_id) {
1582                        case ENCODER_OBJECT_ID_TRAVIS:
1583                        case ENCODER_OBJECT_ID_NUTMEG:
1584                                is_dp_bridge = true;
1585                                break;
1586                        default:
1587                                break;
1588                        }
1589                }
1590        }
1591
1592        amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1593        if (!amdgpu_connector)
1594                return;
1595
1596        connector = &amdgpu_connector->base;
1597
1598        amdgpu_connector->connector_id = connector_id;
1599        amdgpu_connector->devices = supported_device;
1600        amdgpu_connector->shared_ddc = shared_ddc;
1601        amdgpu_connector->connector_object_id = connector_object_id;
1602        amdgpu_connector->hpd = *hpd;
1603
1604        amdgpu_connector->router = *router;
1605        if (router->ddc_valid || router->cd_valid) {
1606                amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1607                if (!amdgpu_connector->router_bus)
1608                        DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1609        }
1610
1611        if (is_dp_bridge) {
1612                amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1613                if (!amdgpu_dig_connector)
1614                        goto failed;
1615                amdgpu_connector->con_priv = amdgpu_dig_connector;
1616                if (i2c_bus->valid) {
1617                        amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1618                        if (amdgpu_connector->ddc_bus) {
1619                                has_aux = true;
1620                                ddc = &amdgpu_connector->ddc_bus->adapter;
1621                        } else {
1622                                DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1623                        }
1624                }
1625                switch (connector_type) {
1626                case DRM_MODE_CONNECTOR_VGA:
1627                case DRM_MODE_CONNECTOR_DVIA:
1628                default:
1629                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1630                                                    &amdgpu_connector_dp_funcs,
1631                                                    connector_type,
1632                                                    ddc);
1633                        drm_connector_helper_add(&amdgpu_connector->base,
1634                                                 &amdgpu_connector_dp_helper_funcs);
1635                        connector->interlace_allowed = true;
1636                        connector->doublescan_allowed = true;
1637                        amdgpu_connector->dac_load_detect = true;
1638                        drm_object_attach_property(&amdgpu_connector->base.base,
1639                                                      adev->mode_info.load_detect_property,
1640                                                      1);
1641                        drm_object_attach_property(&amdgpu_connector->base.base,
1642                                                   dev->mode_config.scaling_mode_property,
1643                                                   DRM_MODE_SCALE_NONE);
1644                        break;
1645                case DRM_MODE_CONNECTOR_DVII:
1646                case DRM_MODE_CONNECTOR_DVID:
1647                case DRM_MODE_CONNECTOR_HDMIA:
1648                case DRM_MODE_CONNECTOR_HDMIB:
1649                case DRM_MODE_CONNECTOR_DisplayPort:
1650                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1651                                                    &amdgpu_connector_dp_funcs,
1652                                                    connector_type,
1653                                                    ddc);
1654                        drm_connector_helper_add(&amdgpu_connector->base,
1655                                                 &amdgpu_connector_dp_helper_funcs);
1656                        drm_object_attach_property(&amdgpu_connector->base.base,
1657                                                      adev->mode_info.underscan_property,
1658                                                      UNDERSCAN_OFF);
1659                        drm_object_attach_property(&amdgpu_connector->base.base,
1660                                                      adev->mode_info.underscan_hborder_property,
1661                                                      0);
1662                        drm_object_attach_property(&amdgpu_connector->base.base,
1663                                                      adev->mode_info.underscan_vborder_property,
1664                                                      0);
1665
1666                        drm_object_attach_property(&amdgpu_connector->base.base,
1667                                                   dev->mode_config.scaling_mode_property,
1668                                                   DRM_MODE_SCALE_NONE);
1669
1670                        drm_object_attach_property(&amdgpu_connector->base.base,
1671                                                   adev->mode_info.dither_property,
1672                                                   AMDGPU_FMT_DITHER_DISABLE);
1673
1674                        if (amdgpu_audio != 0)
1675                                drm_object_attach_property(&amdgpu_connector->base.base,
1676                                                           adev->mode_info.audio_property,
1677                                                           AMDGPU_AUDIO_AUTO);
1678
1679                        subpixel_order = SubPixelHorizontalRGB;
1680                        connector->interlace_allowed = true;
1681                        if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1682                                connector->doublescan_allowed = true;
1683                        else
1684                                connector->doublescan_allowed = false;
1685                        if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1686                                amdgpu_connector->dac_load_detect = true;
1687                                drm_object_attach_property(&amdgpu_connector->base.base,
1688                                                              adev->mode_info.load_detect_property,
1689                                                              1);
1690                        }
1691                        break;
1692                case DRM_MODE_CONNECTOR_LVDS:
1693                case DRM_MODE_CONNECTOR_eDP:
1694                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1695                                                    &amdgpu_connector_edp_funcs,
1696                                                    connector_type,
1697                                                    ddc);
1698                        drm_connector_helper_add(&amdgpu_connector->base,
1699                                                 &amdgpu_connector_dp_helper_funcs);
1700                        drm_object_attach_property(&amdgpu_connector->base.base,
1701                                                      dev->mode_config.scaling_mode_property,
1702                                                      DRM_MODE_SCALE_FULLSCREEN);
1703                        subpixel_order = SubPixelHorizontalRGB;
1704                        connector->interlace_allowed = false;
1705                        connector->doublescan_allowed = false;
1706                        break;
1707                }
1708        } else {
1709                switch (connector_type) {
1710                case DRM_MODE_CONNECTOR_VGA:
1711                        if (i2c_bus->valid) {
1712                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1713                                if (!amdgpu_connector->ddc_bus)
1714                                        DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1715                                else
1716                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1717                        }
1718                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1719                                                    &amdgpu_connector_vga_funcs,
1720                                                    connector_type,
1721                                                    ddc);
1722                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1723                        amdgpu_connector->dac_load_detect = true;
1724                        drm_object_attach_property(&amdgpu_connector->base.base,
1725                                                      adev->mode_info.load_detect_property,
1726                                                      1);
1727                        drm_object_attach_property(&amdgpu_connector->base.base,
1728                                                   dev->mode_config.scaling_mode_property,
1729                                                   DRM_MODE_SCALE_NONE);
1730                        /* no HPD on analog connectors */
1731                        amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1732                        connector->interlace_allowed = true;
1733                        connector->doublescan_allowed = true;
1734                        break;
1735                case DRM_MODE_CONNECTOR_DVIA:
1736                        if (i2c_bus->valid) {
1737                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1738                                if (!amdgpu_connector->ddc_bus)
1739                                        DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1740                                else
1741                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1742                        }
1743                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1744                                                    &amdgpu_connector_vga_funcs,
1745                                                    connector_type,
1746                                                    ddc);
1747                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1748                        amdgpu_connector->dac_load_detect = true;
1749                        drm_object_attach_property(&amdgpu_connector->base.base,
1750                                                      adev->mode_info.load_detect_property,
1751                                                      1);
1752                        drm_object_attach_property(&amdgpu_connector->base.base,
1753                                                   dev->mode_config.scaling_mode_property,
1754                                                   DRM_MODE_SCALE_NONE);
1755                        /* no HPD on analog connectors */
1756                        amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1757                        connector->interlace_allowed = true;
1758                        connector->doublescan_allowed = true;
1759                        break;
1760                case DRM_MODE_CONNECTOR_DVII:
1761                case DRM_MODE_CONNECTOR_DVID:
1762                        amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1763                        if (!amdgpu_dig_connector)
1764                                goto failed;
1765                        amdgpu_connector->con_priv = amdgpu_dig_connector;
1766                        if (i2c_bus->valid) {
1767                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1768                                if (!amdgpu_connector->ddc_bus)
1769                                        DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1770                                else
1771                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1772                        }
1773                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1774                                                    &amdgpu_connector_dvi_funcs,
1775                                                    connector_type,
1776                                                    ddc);
1777                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1778                        subpixel_order = SubPixelHorizontalRGB;
1779                        drm_object_attach_property(&amdgpu_connector->base.base,
1780                                                      adev->mode_info.coherent_mode_property,
1781                                                      1);
1782                        drm_object_attach_property(&amdgpu_connector->base.base,
1783                                                   adev->mode_info.underscan_property,
1784                                                   UNDERSCAN_OFF);
1785                        drm_object_attach_property(&amdgpu_connector->base.base,
1786                                                   adev->mode_info.underscan_hborder_property,
1787                                                   0);
1788                        drm_object_attach_property(&amdgpu_connector->base.base,
1789                                                   adev->mode_info.underscan_vborder_property,
1790                                                   0);
1791                        drm_object_attach_property(&amdgpu_connector->base.base,
1792                                                   dev->mode_config.scaling_mode_property,
1793                                                   DRM_MODE_SCALE_NONE);
1794
1795                        if (amdgpu_audio != 0) {
1796                                drm_object_attach_property(&amdgpu_connector->base.base,
1797                                                           adev->mode_info.audio_property,
1798                                                           AMDGPU_AUDIO_AUTO);
1799                        }
1800                        drm_object_attach_property(&amdgpu_connector->base.base,
1801                                                   adev->mode_info.dither_property,
1802                                                   AMDGPU_FMT_DITHER_DISABLE);
1803                        if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1804                                amdgpu_connector->dac_load_detect = true;
1805                                drm_object_attach_property(&amdgpu_connector->base.base,
1806                                                           adev->mode_info.load_detect_property,
1807                                                           1);
1808                        }
1809                        connector->interlace_allowed = true;
1810                        if (connector_type == DRM_MODE_CONNECTOR_DVII)
1811                                connector->doublescan_allowed = true;
1812                        else
1813                                connector->doublescan_allowed = false;
1814                        break;
1815                case DRM_MODE_CONNECTOR_HDMIA:
1816                case DRM_MODE_CONNECTOR_HDMIB:
1817                        amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1818                        if (!amdgpu_dig_connector)
1819                                goto failed;
1820                        amdgpu_connector->con_priv = amdgpu_dig_connector;
1821                        if (i2c_bus->valid) {
1822                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1823                                if (!amdgpu_connector->ddc_bus)
1824                                        DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1825                                else
1826                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1827                        }
1828                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1829                                                    &amdgpu_connector_dvi_funcs,
1830                                                    connector_type,
1831                                                    ddc);
1832                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1833                        drm_object_attach_property(&amdgpu_connector->base.base,
1834                                                      adev->mode_info.coherent_mode_property,
1835                                                      1);
1836                        drm_object_attach_property(&amdgpu_connector->base.base,
1837                                                   adev->mode_info.underscan_property,
1838                                                   UNDERSCAN_OFF);
1839                        drm_object_attach_property(&amdgpu_connector->base.base,
1840                                                   adev->mode_info.underscan_hborder_property,
1841                                                   0);
1842                        drm_object_attach_property(&amdgpu_connector->base.base,
1843                                                   adev->mode_info.underscan_vborder_property,
1844                                                   0);
1845                        drm_object_attach_property(&amdgpu_connector->base.base,
1846                                                   dev->mode_config.scaling_mode_property,
1847                                                   DRM_MODE_SCALE_NONE);
1848                        if (amdgpu_audio != 0) {
1849                                drm_object_attach_property(&amdgpu_connector->base.base,
1850                                                           adev->mode_info.audio_property,
1851                                                           AMDGPU_AUDIO_AUTO);
1852                        }
1853                        drm_object_attach_property(&amdgpu_connector->base.base,
1854                                                   adev->mode_info.dither_property,
1855                                                   AMDGPU_FMT_DITHER_DISABLE);
1856                        subpixel_order = SubPixelHorizontalRGB;
1857                        connector->interlace_allowed = true;
1858                        if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1859                                connector->doublescan_allowed = true;
1860                        else
1861                                connector->doublescan_allowed = false;
1862                        break;
1863                case DRM_MODE_CONNECTOR_DisplayPort:
1864                        amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1865                        if (!amdgpu_dig_connector)
1866                                goto failed;
1867                        amdgpu_connector->con_priv = amdgpu_dig_connector;
1868                        if (i2c_bus->valid) {
1869                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1870                                if (amdgpu_connector->ddc_bus) {
1871                                        has_aux = true;
1872                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1873                                } else {
1874                                        DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1875                                }
1876                        }
1877                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1878                                                    &amdgpu_connector_dp_funcs,
1879                                                    connector_type,
1880                                                    ddc);
1881                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1882                        subpixel_order = SubPixelHorizontalRGB;
1883                        drm_object_attach_property(&amdgpu_connector->base.base,
1884                                                      adev->mode_info.coherent_mode_property,
1885                                                      1);
1886                        drm_object_attach_property(&amdgpu_connector->base.base,
1887                                                   adev->mode_info.underscan_property,
1888                                                   UNDERSCAN_OFF);
1889                        drm_object_attach_property(&amdgpu_connector->base.base,
1890                                                   adev->mode_info.underscan_hborder_property,
1891                                                   0);
1892                        drm_object_attach_property(&amdgpu_connector->base.base,
1893                                                   adev->mode_info.underscan_vborder_property,
1894                                                   0);
1895                        drm_object_attach_property(&amdgpu_connector->base.base,
1896                                                   dev->mode_config.scaling_mode_property,
1897                                                   DRM_MODE_SCALE_NONE);
1898                        if (amdgpu_audio != 0) {
1899                                drm_object_attach_property(&amdgpu_connector->base.base,
1900                                                           adev->mode_info.audio_property,
1901                                                           AMDGPU_AUDIO_AUTO);
1902                        }
1903                        drm_object_attach_property(&amdgpu_connector->base.base,
1904                                                   adev->mode_info.dither_property,
1905                                                   AMDGPU_FMT_DITHER_DISABLE);
1906                        connector->interlace_allowed = true;
1907                        /* in theory with a DP to VGA converter... */
1908                        connector->doublescan_allowed = false;
1909                        break;
1910                case DRM_MODE_CONNECTOR_eDP:
1911                        amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1912                        if (!amdgpu_dig_connector)
1913                                goto failed;
1914                        amdgpu_connector->con_priv = amdgpu_dig_connector;
1915                        if (i2c_bus->valid) {
1916                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1917                                if (amdgpu_connector->ddc_bus) {
1918                                        has_aux = true;
1919                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1920                                } else {
1921                                        DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1922                                }
1923                        }
1924                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1925                                                    &amdgpu_connector_edp_funcs,
1926                                                    connector_type,
1927                                                    ddc);
1928                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1929                        drm_object_attach_property(&amdgpu_connector->base.base,
1930                                                      dev->mode_config.scaling_mode_property,
1931                                                      DRM_MODE_SCALE_FULLSCREEN);
1932                        subpixel_order = SubPixelHorizontalRGB;
1933                        connector->interlace_allowed = false;
1934                        connector->doublescan_allowed = false;
1935                        break;
1936                case DRM_MODE_CONNECTOR_LVDS:
1937                        amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1938                        if (!amdgpu_dig_connector)
1939                                goto failed;
1940                        amdgpu_connector->con_priv = amdgpu_dig_connector;
1941                        if (i2c_bus->valid) {
1942                                amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1943                                if (!amdgpu_connector->ddc_bus)
1944                                        DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1945                                else
1946                                        ddc = &amdgpu_connector->ddc_bus->adapter;
1947                        }
1948                        drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1949                                                    &amdgpu_connector_lvds_funcs,
1950                                                    connector_type,
1951                                                    ddc);
1952                        drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1953                        drm_object_attach_property(&amdgpu_connector->base.base,
1954                                                      dev->mode_config.scaling_mode_property,
1955                                                      DRM_MODE_SCALE_FULLSCREEN);
1956                        subpixel_order = SubPixelHorizontalRGB;
1957                        connector->interlace_allowed = false;
1958                        connector->doublescan_allowed = false;
1959                        break;
1960                }
1961        }
1962
1963        if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1964                if (i2c_bus->valid) {
1965                        connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1966                                            DRM_CONNECTOR_POLL_DISCONNECT;
1967                }
1968        } else
1969                connector->polled = DRM_CONNECTOR_POLL_HPD;
1970
1971        connector->display_info.subpixel_order = subpixel_order;
1972
1973        if (has_aux)
1974                amdgpu_atombios_dp_aux_init(amdgpu_connector);
1975
1976        if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1977            connector_type == DRM_MODE_CONNECTOR_eDP) {
1978                drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
1979        }
1980
1981        return;
1982
1983failed:
1984        drm_connector_cleanup(connector);
1985        kfree(connector);
1986}
1987