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26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31#include "logger_types.h"
32#if defined(CONFIG_DRM_AMD_DC_HDCP)
33#include "hdcp_types.h"
34#endif
35#include "gpio_types.h"
36#include "link_service_types.h"
37#include "grph_object_ctrl_defs.h"
38#include <inc/hw/opp.h>
39
40#include "inc/hw_sequencer.h"
41#include "inc/compressor.h"
42#include "inc/hw/dmcu.h"
43#include "dml/display_mode_lib.h"
44
45
46struct aux_payload;
47
48#define DC_VER "3.2.141"
49
50#define MAX_SURFACES 3
51#define MAX_PLANES 6
52#define MAX_STREAMS 6
53#define MAX_SINKS_PER_LINK 4
54#define MIN_VIEWPORT_SIZE 12
55#define MAX_NUM_EDP 2
56
57
58
59
60struct dc_versions {
61 const char *dc_ver;
62 struct dmcu_version dmcu_version;
63};
64
65enum dp_protocol_version {
66 DP_VERSION_1_4,
67};
68
69enum dc_plane_type {
70 DC_PLANE_TYPE_INVALID,
71 DC_PLANE_TYPE_DCE_RGB,
72 DC_PLANE_TYPE_DCE_UNDERLAY,
73 DC_PLANE_TYPE_DCN_UNIVERSAL,
74};
75
76struct dc_plane_cap {
77 enum dc_plane_type type;
78 uint32_t blends_with_above : 1;
79 uint32_t blends_with_below : 1;
80 uint32_t per_pixel_alpha : 1;
81 struct {
82 uint32_t argb8888 : 1;
83 uint32_t nv12 : 1;
84 uint32_t fp16 : 1;
85 uint32_t p010 : 1;
86 uint32_t ayuv : 1;
87 } pixel_format_support;
88
89
90
91 struct {
92 uint32_t argb8888;
93 uint32_t nv12;
94 uint32_t fp16;
95 } max_upscale_factor;
96
97
98
99 struct {
100 uint32_t argb8888;
101 uint32_t nv12;
102 uint32_t fp16;
103 } max_downscale_factor;
104
105 uint32_t min_width;
106 uint32_t min_height;
107};
108
109
110struct rom_curve_caps {
111 uint16_t srgb : 1;
112 uint16_t bt2020 : 1;
113 uint16_t gamma2_2 : 1;
114 uint16_t pq : 1;
115 uint16_t hlg : 1;
116};
117
118struct dpp_color_caps {
119 uint16_t dcn_arch : 1;
120
121 uint16_t input_lut_shared : 1;
122 uint16_t icsc : 1;
123 uint16_t dgam_ram : 1;
124 uint16_t post_csc : 1;
125 uint16_t gamma_corr : 1;
126
127
128
129
130 uint16_t hw_3d_lut : 1;
131 uint16_t ogam_ram : 1;
132 uint16_t ocsc : 1;
133 uint16_t dgam_rom_for_yuv : 1;
134 struct rom_curve_caps dgam_rom_caps;
135 struct rom_curve_caps ogam_rom_caps;
136};
137
138struct mpc_color_caps {
139 uint16_t gamut_remap : 1;
140 uint16_t ogam_ram : 1;
141 uint16_t ocsc : 1;
142 uint16_t num_3dluts : 3;
143 uint16_t shared_3d_lut:1;
144
145 struct rom_curve_caps ogam_rom_caps;
146};
147
148struct dc_color_caps {
149 struct dpp_color_caps dpp;
150 struct mpc_color_caps mpc;
151};
152
153struct dc_caps {
154 uint32_t max_streams;
155 uint32_t max_links;
156 uint32_t max_audios;
157 uint32_t max_slave_planes;
158 uint32_t max_slave_yuv_planes;
159 uint32_t max_slave_rgb_planes;
160 uint32_t max_planes;
161 uint32_t max_downscale_ratio;
162 uint32_t i2c_speed_in_khz;
163 uint32_t i2c_speed_in_khz_hdcp;
164 uint32_t dmdata_alloc_size;
165 unsigned int max_cursor_size;
166 unsigned int max_video_width;
167 unsigned int min_horizontal_blanking_period;
168 int linear_pitch_alignment;
169 bool dcc_const_color;
170 bool dynamic_audio;
171 bool is_apu;
172 bool dual_link_dvi;
173 bool post_blend_color_processing;
174 bool force_dp_tps4_for_cp2520;
175 bool disable_dp_clk_share;
176 bool psp_setup_panel_mode;
177 bool extended_aux_timeout_support;
178 bool dmcub_support;
179 uint32_t num_of_internal_disp;
180 enum dp_protocol_version max_dp_protocol_version;
181 unsigned int mall_size_per_mem_channel;
182 unsigned int mall_size_total;
183 unsigned int cursor_cache_size;
184 struct dc_plane_cap planes[MAX_PLANES];
185 struct dc_color_caps color;
186 bool vbios_lttpr_aware;
187 bool vbios_lttpr_enable;
188};
189
190struct dc_bug_wa {
191 bool no_connect_phy_config;
192 bool dedcn20_305_wa;
193 bool skip_clock_update;
194 bool lt_early_cr_pattern;
195};
196
197struct dc_dcc_surface_param {
198 struct dc_size surface_size;
199 enum surface_pixel_format format;
200 enum swizzle_mode_values swizzle_mode;
201 enum dc_scan_direction scan;
202};
203
204struct dc_dcc_setting {
205 unsigned int max_compressed_blk_size;
206 unsigned int max_uncompressed_blk_size;
207 bool independent_64b_blks;
208#if defined(CONFIG_DRM_AMD_DC_DCN)
209
210 struct {
211 uint32_t dcc_256_64_64 : 1;
212 uint32_t dcc_128_128_uncontrained : 1;
213 uint32_t dcc_256_128_128 : 1;
214 uint32_t dcc_256_256_unconstrained : 1;
215 } dcc_controls;
216#endif
217};
218
219struct dc_surface_dcc_cap {
220 union {
221 struct {
222 struct dc_dcc_setting rgb;
223 } grph;
224
225 struct {
226 struct dc_dcc_setting luma;
227 struct dc_dcc_setting chroma;
228 } video;
229 };
230
231 bool capable;
232 bool const_color_support;
233};
234
235struct dc_static_screen_params {
236 struct {
237 bool force_trigger;
238 bool cursor_update;
239 bool surface_update;
240 bool overlay_update;
241 } triggers;
242 unsigned int num_frames;
243};
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271
272enum surface_update_type {
273 UPDATE_TYPE_FAST,
274 UPDATE_TYPE_MED,
275 UPDATE_TYPE_FULL,
276};
277
278
279struct dc;
280struct dc_plane_state;
281struct dc_state;
282
283
284struct dc_cap_funcs {
285 bool (*get_dcc_compression_cap)(const struct dc *dc,
286 const struct dc_dcc_surface_param *input,
287 struct dc_surface_dcc_cap *output);
288};
289
290struct link_training_settings;
291
292
293
294struct dc_config {
295 bool gpu_vm_support;
296 bool disable_disp_pll_sharing;
297 bool fbc_support;
298 bool disable_fractional_pwm;
299 bool allow_seamless_boot_optimization;
300 bool power_down_display_on_boot;
301 bool edp_not_connected;
302 bool edp_no_power_sequencing;
303 bool force_enum_edp;
304 bool forced_clocks;
305 bool allow_lttpr_non_transparent_mode;
306 bool multi_mon_pp_mclk_switch;
307 bool disable_dmcu;
308 bool enable_4to1MPC;
309 bool allow_edp_hotplug_detection;
310#if defined(CONFIG_DRM_AMD_DC_DCN)
311 bool clamp_min_dcfclk;
312#endif
313 uint64_t vblank_alignment_dto_params;
314 uint8_t vblank_alignment_max_frame_time_diff;
315 bool is_asymmetric_memory;
316 bool is_single_rank_dimm;
317};
318
319enum visual_confirm {
320 VISUAL_CONFIRM_DISABLE = 0,
321 VISUAL_CONFIRM_SURFACE = 1,
322 VISUAL_CONFIRM_HDR = 2,
323 VISUAL_CONFIRM_MPCTREE = 4,
324 VISUAL_CONFIRM_PSR = 5,
325 VISUAL_CONFIRM_SWIZZLE = 9,
326};
327
328enum dcc_option {
329 DCC_ENABLE = 0,
330 DCC_DISABLE = 1,
331 DCC_HALF_REQ_DISALBE = 2,
332};
333
334enum pipe_split_policy {
335 MPC_SPLIT_DYNAMIC = 0,
336 MPC_SPLIT_AVOID = 1,
337 MPC_SPLIT_AVOID_MULT_DISP = 2,
338};
339
340enum wm_report_mode {
341 WM_REPORT_DEFAULT = 0,
342 WM_REPORT_OVERRIDE = 1,
343};
344enum dtm_pstate{
345 dtm_level_p0 = 0,
346 dtm_level_p1,
347 dtm_level_p2,
348 dtm_level_p3,
349 dtm_level_p4,
350};
351
352enum dcn_pwr_state {
353 DCN_PWR_STATE_UNKNOWN = -1,
354 DCN_PWR_STATE_MISSION_MODE = 0,
355 DCN_PWR_STATE_LOW_POWER = 3,
356};
357
358#if defined(CONFIG_DRM_AMD_DC_DCN)
359enum dcn_zstate_support_state {
360 DCN_ZSTATE_SUPPORT_UNKNOWN,
361 DCN_ZSTATE_SUPPORT_ALLOW,
362 DCN_ZSTATE_SUPPORT_DISALLOW,
363};
364#endif
365
366
367
368
369struct dc_clocks {
370 int dispclk_khz;
371 int actual_dispclk_khz;
372 int dppclk_khz;
373 int actual_dppclk_khz;
374 int disp_dpp_voltage_level_khz;
375 int dcfclk_khz;
376 int socclk_khz;
377 int dcfclk_deep_sleep_khz;
378 int fclk_khz;
379 int phyclk_khz;
380 int dramclk_khz;
381 bool p_state_change_support;
382#if defined(CONFIG_DRM_AMD_DC_DCN)
383 enum dcn_zstate_support_state zstate_support;
384 bool dtbclk_en;
385#endif
386 enum dcn_pwr_state pwr_state;
387
388
389
390
391 bool prev_p_state_change_support;
392 enum dtm_pstate dtm_level;
393 int max_supported_dppclk_khz;
394 int max_supported_dispclk_khz;
395 int bw_dppclk_khz;
396 int bw_dispclk_khz;
397};
398
399struct dc_bw_validation_profile {
400 bool enable;
401
402 unsigned long long total_ticks;
403 unsigned long long voltage_level_ticks;
404 unsigned long long watermark_ticks;
405 unsigned long long rq_dlg_ticks;
406
407 unsigned long long total_count;
408 unsigned long long skip_fast_count;
409 unsigned long long skip_pass_count;
410 unsigned long long skip_fail_count;
411};
412
413#define BW_VAL_TRACE_SETUP() \
414 unsigned long long end_tick = 0; \
415 unsigned long long voltage_level_tick = 0; \
416 unsigned long long watermark_tick = 0; \
417 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
418 dm_get_timestamp(dc->ctx) : 0
419
420#define BW_VAL_TRACE_COUNT() \
421 if (dc->debug.bw_val_profile.enable) \
422 dc->debug.bw_val_profile.total_count++
423
424#define BW_VAL_TRACE_SKIP(status) \
425 if (dc->debug.bw_val_profile.enable) { \
426 if (!voltage_level_tick) \
427 voltage_level_tick = dm_get_timestamp(dc->ctx); \
428 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
429 }
430
431#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
432 if (dc->debug.bw_val_profile.enable) \
433 voltage_level_tick = dm_get_timestamp(dc->ctx)
434
435#define BW_VAL_TRACE_END_WATERMARKS() \
436 if (dc->debug.bw_val_profile.enable) \
437 watermark_tick = dm_get_timestamp(dc->ctx)
438
439#define BW_VAL_TRACE_FINISH() \
440 if (dc->debug.bw_val_profile.enable) { \
441 end_tick = dm_get_timestamp(dc->ctx); \
442 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
443 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
444 if (watermark_tick) { \
445 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
446 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
447 } \
448 }
449
450union mem_low_power_enable_options {
451 struct {
452 bool vga: 1;
453 bool i2c: 1;
454 bool dmcu: 1;
455 bool dscl: 1;
456 bool cm: 1;
457 bool mpc: 1;
458 bool optc: 1;
459 } bits;
460 uint32_t u32All;
461};
462
463struct dc_debug_options {
464 enum visual_confirm visual_confirm;
465 bool sanity_checks;
466 bool max_disp_clk;
467 bool surface_trace;
468 bool timing_trace;
469 bool clock_trace;
470 bool validation_trace;
471 bool bandwidth_calcs_trace;
472 int max_downscale_src_width;
473
474
475 bool disable_stutter;
476 bool use_max_lb;
477 enum dcc_option disable_dcc;
478 enum pipe_split_policy pipe_split_policy;
479 bool force_single_disp_pipe_split;
480 bool voltage_align_fclk;
481 bool disable_min_fclk;
482
483 bool disable_dfs_bypass;
484 bool disable_dpp_power_gate;
485 bool disable_hubp_power_gate;
486 bool disable_dsc_power_gate;
487 int dsc_min_slice_height_override;
488 int dsc_bpp_increment_div;
489 bool native422_support;
490 bool disable_pplib_wm_range;
491 enum wm_report_mode pplib_wm_report_mode;
492 unsigned int min_disp_clk_khz;
493 unsigned int min_dpp_clk_khz;
494 int sr_exit_time_dpm0_ns;
495 int sr_enter_plus_exit_time_dpm0_ns;
496 int sr_exit_time_ns;
497 int sr_enter_plus_exit_time_ns;
498 int urgent_latency_ns;
499 uint32_t underflow_assert_delay_us;
500 int percent_of_ideal_drambw;
501 int dram_clock_change_latency_ns;
502 bool optimized_watermark;
503 int always_scale;
504 bool disable_pplib_clock_request;
505 bool disable_clock_gate;
506 bool disable_mem_low_power;
507#if defined(CONFIG_DRM_AMD_DC_DCN)
508 bool pstate_enabled;
509#endif
510 bool disable_dmcu;
511 bool disable_psr;
512 bool force_abm_enable;
513 bool disable_stereo_support;
514 bool vsr_support;
515 bool performance_trace;
516 bool az_endpoint_mute_only;
517 bool always_use_regamma;
518 bool recovery_enabled;
519 bool avoid_vbios_exec_table;
520 bool scl_reset_length10;
521 bool hdmi20_disable;
522 bool skip_detection_link_training;
523 uint32_t edid_read_retry_times;
524 bool remove_disconnect_edp;
525 unsigned int force_odm_combine;
526#if defined(CONFIG_DRM_AMD_DC_DCN)
527 unsigned int force_odm_combine_4to1;
528 bool disable_z9_mpc;
529#endif
530 unsigned int force_fclk_khz;
531 bool enable_tri_buf;
532 bool dmub_offload_enabled;
533 bool dmcub_emulation;
534#if defined(CONFIG_DRM_AMD_DC_DCN)
535 bool disable_idle_power_optimizations;
536 unsigned int mall_size_override;
537 unsigned int mall_additional_timer_percent;
538 bool mall_error_as_fatal;
539#endif
540 bool dmub_command_table;
541 struct dc_bw_validation_profile bw_val_profile;
542 bool disable_fec;
543 bool disable_48mhz_pwrdwn;
544
545
546
547 unsigned int force_min_dcfclk_mhz;
548#if defined(CONFIG_DRM_AMD_DC_DCN)
549 int dwb_fi_phase;
550#endif
551 bool disable_timing_sync;
552 bool cm_in_bypass;
553 int force_clock_mode;
554
555 bool disable_dram_clock_change_vactive_support;
556 bool validate_dml_output;
557 bool enable_dmcub_surface_flip;
558 bool usbc_combo_phy_reset_wa;
559 bool disable_dsc;
560 bool enable_dram_clock_change_one_display_vactive;
561 union mem_low_power_enable_options enable_mem_low_power;
562 bool force_vblank_alignment;
563
564
565 bool enable_dmub_aux_for_legacy_ddc;
566 bool optimize_edp_link_rate;
567
568 bool force_enable_edp_fec;
569
570 uint8_t fec_enable_delay_in100us;
571#if defined(CONFIG_DRM_AMD_DC_DCN)
572 bool disable_z10;
573 bool enable_sw_cntl_psr;
574#endif
575};
576
577struct dc_debug_data {
578 uint32_t ltFailCount;
579 uint32_t i2cErrorCount;
580 uint32_t auxErrorCount;
581};
582
583struct dc_phy_addr_space_config {
584 struct {
585 uint64_t start_addr;
586 uint64_t end_addr;
587 uint64_t fb_top;
588 uint64_t fb_offset;
589 uint64_t fb_base;
590 uint64_t agp_top;
591 uint64_t agp_bot;
592 uint64_t agp_base;
593 } system_aperture;
594
595 struct {
596 uint64_t page_table_start_addr;
597 uint64_t page_table_end_addr;
598 uint64_t page_table_base_addr;
599#if defined(CONFIG_DRM_AMD_DC_DCN)
600 bool base_addr_is_mc_addr;
601#endif
602 } gart_config;
603
604 bool valid;
605 bool is_hvm_enabled;
606 uint64_t page_table_default_page_addr;
607};
608
609struct dc_virtual_addr_space_config {
610 uint64_t page_table_base_addr;
611 uint64_t page_table_start_addr;
612 uint64_t page_table_end_addr;
613 uint32_t page_table_block_size_in_bytes;
614 uint8_t page_table_depth;
615};
616
617struct dc_bounding_box_overrides {
618 int sr_exit_time_ns;
619 int sr_enter_plus_exit_time_ns;
620 int urgent_latency_ns;
621 int percent_of_ideal_drambw;
622 int dram_clock_change_latency_ns;
623 int dummy_clock_change_latency_ns;
624
625
626
627
628 int min_dcfclk_mhz;
629};
630
631struct resource_pool;
632struct dce_hwseq;
633struct gpu_info_soc_bounding_box_v1_0;
634struct dc {
635 struct dc_versions versions;
636 struct dc_caps caps;
637 struct dc_cap_funcs cap_funcs;
638 struct dc_config config;
639 struct dc_debug_options debug;
640 struct dc_bounding_box_overrides bb_overrides;
641 struct dc_bug_wa work_arounds;
642 struct dc_context *ctx;
643 struct dc_phy_addr_space_config vm_pa_config;
644
645 uint8_t link_count;
646 struct dc_link *links[MAX_PIPES * 2];
647
648 struct dc_state *current_state;
649 struct resource_pool *res_pool;
650
651 struct clk_mgr *clk_mgr;
652
653
654 struct dm_pp_clock_levels sclk_lvls;
655
656
657 struct bw_calcs_dceip *bw_dceip;
658 struct bw_calcs_vbios *bw_vbios;
659#ifdef CONFIG_DRM_AMD_DC_DCN
660 struct dcn_soc_bounding_box *dcn_soc;
661 struct dcn_ip_params *dcn_ip;
662 struct display_mode_lib dml;
663#endif
664
665
666 struct hw_sequencer_funcs hwss;
667 struct dce_hwseq *hwseq;
668
669
670 bool optimized_required;
671 bool wm_optimized_required;
672#if defined(CONFIG_DRM_AMD_DC_DCN)
673 bool idle_optimizations_allowed;
674#endif
675
676
677
678
679 struct compressor *fbc_compressor;
680
681 struct dc_debug_data debug_data;
682 struct dpcd_vendor_signature vendor_signature;
683
684 const char *build_id;
685 struct vm_helper *vm_helper;
686};
687
688enum frame_buffer_mode {
689 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
690 FRAME_BUFFER_MODE_ZFB_ONLY,
691 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
692} ;
693
694struct dchub_init_data {
695 int64_t zfb_phys_addr_base;
696 int64_t zfb_mc_base_addr;
697 uint64_t zfb_size_in_byte;
698 enum frame_buffer_mode fb_mode;
699 bool dchub_initialzied;
700 bool dchub_info_valid;
701};
702
703struct dc_init_data {
704 struct hw_asic_id asic_id;
705 void *driver;
706 struct cgs_device *cgs_device;
707 struct dc_bounding_box_overrides bb_overrides;
708
709 int num_virtual_links;
710
711
712
713
714 struct dc_bios *vbios_override;
715 enum dce_environment dce_environment;
716
717 struct dmub_offload_funcs *dmub_if;
718 struct dc_reg_helper_state *dmub_offload;
719
720 struct dc_config flags;
721 uint64_t log_mask;
722
723 struct dpcd_vendor_signature vendor_signature;
724#if defined(CONFIG_DRM_AMD_DC_DCN)
725 bool force_smu_not_present;
726#endif
727};
728
729struct dc_callback_init {
730#ifdef CONFIG_DRM_AMD_DC_HDCP
731 struct cp_psp cp_psp;
732#else
733 uint8_t reserved;
734#endif
735};
736
737struct dc *dc_create(const struct dc_init_data *init_params);
738void dc_hardware_init(struct dc *dc);
739
740int dc_get_vmid_use_vector(struct dc *dc);
741void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
742
743int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
744void dc_init_callbacks(struct dc *dc,
745 const struct dc_callback_init *init_params);
746void dc_deinit_callbacks(struct dc *dc);
747void dc_destroy(struct dc **dc);
748
749
750
751
752
753enum {
754 TRANSFER_FUNC_POINTS = 1025
755};
756
757struct dc_hdr_static_metadata {
758
759 unsigned int chromaticity_green_x;
760 unsigned int chromaticity_green_y;
761 unsigned int chromaticity_blue_x;
762 unsigned int chromaticity_blue_y;
763 unsigned int chromaticity_red_x;
764 unsigned int chromaticity_red_y;
765 unsigned int chromaticity_white_point_x;
766 unsigned int chromaticity_white_point_y;
767
768 uint32_t min_luminance;
769 uint32_t max_luminance;
770 uint32_t maximum_content_light_level;
771 uint32_t maximum_frame_average_light_level;
772};
773
774enum dc_transfer_func_type {
775 TF_TYPE_PREDEFINED,
776 TF_TYPE_DISTRIBUTED_POINTS,
777 TF_TYPE_BYPASS,
778 TF_TYPE_HWPWL
779};
780
781struct dc_transfer_func_distributed_points {
782 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
783 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
784 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
785
786 uint16_t end_exponent;
787 uint16_t x_point_at_y1_red;
788 uint16_t x_point_at_y1_green;
789 uint16_t x_point_at_y1_blue;
790};
791
792enum dc_transfer_func_predefined {
793 TRANSFER_FUNCTION_SRGB,
794 TRANSFER_FUNCTION_BT709,
795 TRANSFER_FUNCTION_PQ,
796 TRANSFER_FUNCTION_LINEAR,
797 TRANSFER_FUNCTION_UNITY,
798 TRANSFER_FUNCTION_HLG,
799 TRANSFER_FUNCTION_HLG12,
800 TRANSFER_FUNCTION_GAMMA22,
801 TRANSFER_FUNCTION_GAMMA24,
802 TRANSFER_FUNCTION_GAMMA26
803};
804
805
806struct dc_transfer_func {
807 struct kref refcount;
808 enum dc_transfer_func_type type;
809 enum dc_transfer_func_predefined tf;
810
811 uint32_t sdr_ref_white_level;
812 union {
813 struct pwl_params pwl;
814 struct dc_transfer_func_distributed_points tf_pts;
815 };
816};
817
818
819union dc_3dlut_state {
820 struct {
821 uint32_t initialized:1;
822 uint32_t rmu_idx_valid:1;
823 uint32_t rmu_mux_num:3;
824 uint32_t mpc_rmu0_mux:4;
825 uint32_t mpc_rmu1_mux:4;
826 uint32_t mpc_rmu2_mux:4;
827 uint32_t reserved:15;
828 } bits;
829 uint32_t raw;
830};
831
832
833struct dc_3dlut {
834 struct kref refcount;
835 struct tetrahedral_params lut_3d;
836 struct fixed31_32 hdr_multiplier;
837 union dc_3dlut_state state;
838};
839
840
841
842
843
844struct dc_plane_status {
845 struct dc_plane_address requested_address;
846 struct dc_plane_address current_address;
847 bool is_flip_pending;
848 bool is_right_eye;
849};
850
851union surface_update_flags {
852
853 struct {
854 uint32_t addr_update:1;
855
856 uint32_t dcc_change:1;
857 uint32_t color_space_change:1;
858 uint32_t horizontal_mirror_change:1;
859 uint32_t per_pixel_alpha_change:1;
860 uint32_t global_alpha_change:1;
861 uint32_t hdr_mult:1;
862 uint32_t rotation_change:1;
863 uint32_t swizzle_change:1;
864 uint32_t scaling_change:1;
865 uint32_t position_change:1;
866 uint32_t in_transfer_func_change:1;
867 uint32_t input_csc_change:1;
868 uint32_t coeff_reduction_change:1;
869 uint32_t output_tf_change:1;
870 uint32_t pixel_format_change:1;
871 uint32_t plane_size_change:1;
872 uint32_t gamut_remap_change:1;
873
874
875 uint32_t new_plane:1;
876 uint32_t bpp_change:1;
877 uint32_t gamma_change:1;
878 uint32_t bandwidth_change:1;
879 uint32_t clock_change:1;
880 uint32_t stereo_format_change:1;
881 uint32_t full_update:1;
882 } bits;
883
884 uint32_t raw;
885};
886
887struct dc_plane_state {
888 struct dc_plane_address address;
889 struct dc_plane_flip_time time;
890 bool triplebuffer_flips;
891 struct scaling_taps scaling_quality;
892 struct rect src_rect;
893 struct rect dst_rect;
894 struct rect clip_rect;
895
896 struct plane_size plane_size;
897 union dc_tiling_info tiling_info;
898
899 struct dc_plane_dcc_param dcc;
900
901 struct dc_gamma *gamma_correction;
902 struct dc_transfer_func *in_transfer_func;
903 struct dc_bias_and_scale *bias_and_scale;
904 struct dc_csc_transform input_csc_color_matrix;
905 struct fixed31_32 coeff_reduction_factor;
906 struct fixed31_32 hdr_mult;
907 struct colorspace_transform gamut_remap_matrix;
908
909
910 struct dc_hdr_static_metadata hdr_static_ctx;
911
912 enum dc_color_space color_space;
913
914 struct dc_3dlut *lut3d_func;
915 struct dc_transfer_func *in_shaper_func;
916 struct dc_transfer_func *blend_tf;
917
918#if defined(CONFIG_DRM_AMD_DC_DCN)
919 struct dc_transfer_func *gamcor_tf;
920#endif
921 enum surface_pixel_format format;
922 enum dc_rotation_angle rotation;
923 enum plane_stereo_format stereo_format;
924
925 bool is_tiling_rotated;
926 bool per_pixel_alpha;
927 bool global_alpha;
928 int global_alpha_value;
929 bool visible;
930 bool flip_immediate;
931 bool horizontal_mirror;
932 int layer_index;
933
934 union surface_update_flags update_flags;
935 bool flip_int_enabled;
936 bool skip_manual_trigger;
937
938
939 struct dc_plane_status status;
940 struct dc_context *ctx;
941
942
943 bool force_full_update;
944
945
946 enum dc_irq_source irq_source;
947 struct kref refcount;
948};
949
950struct dc_plane_info {
951 struct plane_size plane_size;
952 union dc_tiling_info tiling_info;
953 struct dc_plane_dcc_param dcc;
954 enum surface_pixel_format format;
955 enum dc_rotation_angle rotation;
956 enum plane_stereo_format stereo_format;
957 enum dc_color_space color_space;
958 bool horizontal_mirror;
959 bool visible;
960 bool per_pixel_alpha;
961 bool global_alpha;
962 int global_alpha_value;
963 bool input_csc_enabled;
964 int layer_index;
965};
966
967struct dc_scaling_info {
968 struct rect src_rect;
969 struct rect dst_rect;
970 struct rect clip_rect;
971 struct scaling_taps scaling_quality;
972};
973
974struct dc_surface_update {
975 struct dc_plane_state *surface;
976
977
978 const struct dc_flip_addrs *flip_addr;
979 const struct dc_plane_info *plane_info;
980 const struct dc_scaling_info *scaling_info;
981 struct fixed31_32 hdr_mult;
982
983
984
985 const struct dc_gamma *gamma;
986 const struct dc_transfer_func *in_transfer_func;
987
988 const struct dc_csc_transform *input_csc_color_matrix;
989 const struct fixed31_32 *coeff_reduction_factor;
990 const struct dc_transfer_func *func_shaper;
991 const struct dc_3dlut *lut3d_func;
992 const struct dc_transfer_func *blend_tf;
993 const struct colorspace_transform *gamut_remap_matrix;
994};
995
996
997
998
999struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1000const struct dc_plane_status *dc_plane_get_status(
1001 const struct dc_plane_state *plane_state);
1002
1003void dc_plane_state_retain(struct dc_plane_state *plane_state);
1004void dc_plane_state_release(struct dc_plane_state *plane_state);
1005
1006void dc_gamma_retain(struct dc_gamma *dc_gamma);
1007void dc_gamma_release(struct dc_gamma **dc_gamma);
1008struct dc_gamma *dc_create_gamma(void);
1009
1010void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1011void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1012struct dc_transfer_func *dc_create_transfer_func(void);
1013
1014struct dc_3dlut *dc_create_3dlut_func(void);
1015void dc_3dlut_func_release(struct dc_3dlut *lut);
1016void dc_3dlut_func_retain(struct dc_3dlut *lut);
1017
1018
1019
1020
1021
1022struct dc_flip_addrs {
1023 struct dc_plane_address address;
1024 unsigned int flip_timestamp_in_us;
1025 bool flip_immediate;
1026
1027 bool triplebuffer_flips;
1028};
1029
1030void dc_post_update_surfaces_to_stream(
1031 struct dc *dc);
1032
1033#include "dc_stream.h"
1034
1035
1036
1037
1038struct dc_validation_set {
1039 struct dc_stream_state *stream;
1040 struct dc_plane_state *plane_states[MAX_SURFACES];
1041 uint8_t plane_count;
1042};
1043
1044bool dc_validate_seamless_boot_timing(const struct dc *dc,
1045 const struct dc_sink *sink,
1046 struct dc_crtc_timing *crtc_timing);
1047
1048enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1049
1050void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1051
1052bool dc_set_generic_gpio_for_stereo(bool enable,
1053 struct gpio_service *gpio_service);
1054
1055
1056
1057
1058
1059enum dc_status dc_validate_global_state(
1060 struct dc *dc,
1061 struct dc_state *new_ctx,
1062 bool fast_validate);
1063
1064
1065void dc_resource_state_construct(
1066 const struct dc *dc,
1067 struct dc_state *dst_ctx);
1068
1069#if defined(CONFIG_DRM_AMD_DC_DCN)
1070bool dc_acquire_release_mpc_3dlut(
1071 struct dc *dc, bool acquire,
1072 struct dc_stream_state *stream,
1073 struct dc_3dlut **lut,
1074 struct dc_transfer_func **shaper);
1075#endif
1076
1077void dc_resource_state_copy_construct(
1078 const struct dc_state *src_ctx,
1079 struct dc_state *dst_ctx);
1080
1081void dc_resource_state_copy_construct_current(
1082 const struct dc *dc,
1083 struct dc_state *dst_ctx);
1084
1085void dc_resource_state_destruct(struct dc_state *context);
1086
1087bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098bool dc_commit_state(struct dc *dc, struct dc_state *context);
1099
1100struct dc_state *dc_create_state(struct dc *dc);
1101struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1102void dc_retain_state(struct dc_state *context);
1103void dc_release_state(struct dc_state *context);
1104
1105
1106
1107
1108
1109struct dpcd_caps {
1110 union dpcd_rev dpcd_rev;
1111 union max_lane_count max_ln_count;
1112 union max_down_spread max_down_spread;
1113 union dprx_feature dprx_feature;
1114
1115
1116 uint8_t edp_supported_link_rates_count;
1117 enum dc_link_rate edp_supported_link_rates[8];
1118
1119
1120 enum display_dongle_type dongle_type;
1121
1122 bool is_branch_dev;
1123
1124 union sink_count sink_count;
1125
1126
1127 struct dc_dongle_caps dongle_caps;
1128
1129 uint32_t sink_dev_id;
1130 int8_t sink_dev_id_str[6];
1131 int8_t sink_hw_revision;
1132 int8_t sink_fw_revision[2];
1133
1134 uint32_t branch_dev_id;
1135 int8_t branch_dev_name[6];
1136 int8_t branch_hw_revision;
1137 int8_t branch_fw_revision[2];
1138
1139 bool allow_invalid_MSA_timing_param;
1140 bool panel_mode_edp;
1141 bool dpcd_display_control_capable;
1142 bool ext_receiver_cap_field_present;
1143 bool dynamic_backlight_capable_edp;
1144 union dpcd_fec_capability fec_cap;
1145 struct dpcd_dsc_capabilities dsc_caps;
1146 struct dc_lttpr_caps lttpr_caps;
1147 struct psr_caps psr_caps;
1148
1149};
1150
1151union dpcd_sink_ext_caps {
1152 struct {
1153
1154
1155
1156 uint8_t sdr_aux_backlight_control : 1;
1157 uint8_t hdr_aux_backlight_control : 1;
1158 uint8_t reserved_1 : 2;
1159 uint8_t oled : 1;
1160 uint8_t reserved : 3;
1161 } bits;
1162 uint8_t raw;
1163};
1164
1165#if defined(CONFIG_DRM_AMD_DC_HDCP)
1166union hdcp_rx_caps {
1167 struct {
1168 uint8_t version;
1169 uint8_t reserved;
1170 struct {
1171 uint8_t repeater : 1;
1172 uint8_t hdcp_capable : 1;
1173 uint8_t reserved : 6;
1174 } byte0;
1175 } fields;
1176 uint8_t raw[3];
1177};
1178
1179union hdcp_bcaps {
1180 struct {
1181 uint8_t HDCP_CAPABLE:1;
1182 uint8_t REPEATER:1;
1183 uint8_t RESERVED:6;
1184 } bits;
1185 uint8_t raw;
1186};
1187
1188struct hdcp_caps {
1189 union hdcp_rx_caps rx_caps;
1190 union hdcp_bcaps bcaps;
1191};
1192#endif
1193
1194#include "dc_link.h"
1195
1196#if defined(CONFIG_DRM_AMD_DC_DCN)
1197uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1198
1199#endif
1200
1201
1202
1203
1204struct dc_container_id {
1205
1206 unsigned char guid[16];
1207
1208 unsigned int portId[2];
1209
1210 unsigned short manufacturerName;
1211
1212 unsigned short productCode;
1213};
1214
1215
1216struct dc_sink_dsc_caps {
1217
1218
1219 bool is_virtual_dpcd_dsc;
1220 struct dsc_dec_dpcd_caps dsc_dec_caps;
1221};
1222
1223struct dc_sink_fec_caps {
1224 bool is_rx_fec_supported;
1225 bool is_topology_fec_supported;
1226};
1227
1228
1229
1230
1231struct dc_sink {
1232 enum signal_type sink_signal;
1233 struct dc_edid dc_edid;
1234 struct dc_edid_caps edid_caps;
1235 struct dc_container_id *dc_container_id;
1236 uint32_t dongle_max_pix_clk;
1237 void *priv;
1238 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1239 bool converter_disable_audio;
1240
1241 struct dc_sink_dsc_caps dsc_caps;
1242 struct dc_sink_fec_caps fec_caps;
1243
1244 bool is_vsc_sdp_colorimetry_supported;
1245
1246
1247 struct dc_link *link;
1248 struct dc_context *ctx;
1249
1250 uint32_t sink_id;
1251
1252
1253
1254
1255
1256 struct kref refcount;
1257};
1258
1259void dc_sink_retain(struct dc_sink *sink);
1260void dc_sink_release(struct dc_sink *sink);
1261
1262struct dc_sink_init_data {
1263 enum signal_type sink_signal;
1264 struct dc_link *link;
1265 uint32_t dongle_max_pix_clk;
1266 bool converter_disable_audio;
1267};
1268
1269struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1270
1271
1272struct dc_cursor {
1273 struct dc_plane_address address;
1274 struct dc_cursor_attributes attributes;
1275};
1276
1277
1278
1279
1280
1281enum dc_irq_source dc_interrupt_to_irq_source(
1282 struct dc *dc,
1283 uint32_t src_id,
1284 uint32_t ext_id);
1285bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1286void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1287enum dc_irq_source dc_get_hpd_irq_source_at_index(
1288 struct dc *dc, uint32_t link_index);
1289
1290
1291
1292
1293
1294void dc_set_power_state(
1295 struct dc *dc,
1296 enum dc_acpi_cm_power_state power_state);
1297void dc_resume(struct dc *dc);
1298
1299void dc_power_down_on_boot(struct dc *dc);
1300
1301#if defined(CONFIG_DRM_AMD_DC_HDCP)
1302
1303
1304
1305enum hdcp_message_status dc_process_hdcp_msg(
1306 enum signal_type signal,
1307 struct dc_link *link,
1308 struct hdcp_protection_message *message_info);
1309#endif
1310bool dc_is_dmcu_initialized(struct dc *dc);
1311
1312enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1313void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1314#if defined(CONFIG_DRM_AMD_DC_DCN)
1315
1316bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1317 struct dc_cursor_attributes *cursor_attr);
1318
1319void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1320
1321
1322
1323
1324
1325void dc_unlock_memory_clock_frequency(struct dc *dc);
1326
1327
1328
1329
1330
1331void dc_lock_memory_clock_frequency(struct dc *dc);
1332
1333
1334void dc_hardware_release(struct dc *dc);
1335
1336#endif
1337
1338bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1339#if defined(CONFIG_DRM_AMD_DC_DCN)
1340void dc_z10_restore(struct dc *dc);
1341void dc_z10_save_init(struct dc *dc);
1342#endif
1343
1344bool dc_enable_dmub_notifications(struct dc *dc);
1345
1346bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1347 uint32_t link_index,
1348 struct aux_payload *payload);
1349
1350
1351
1352
1353#include "dc_dsc.h"
1354
1355
1356
1357
1358void dc_disable_accelerated_mode(struct dc *dc);
1359
1360#endif
1361