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31#include <linux/export.h>
32#include <linux/pci.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_atomic_helper.h>
36#include <drm/drm_atomic_state_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_crtc_helper.h>
39#include <drm/drm_fourcc.h>
40#include <drm/drm_gem_atomic_helper.h>
41#include <drm/drm_gem_framebuffer_helper.h>
42#include <drm/drm_gem_vram_helper.h>
43#include <drm/drm_plane_helper.h>
44#include <drm/drm_probe_helper.h>
45#include <drm/drm_simple_kms_helper.h>
46
47#include "ast_drv.h"
48#include "ast_tables.h"
49
50static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
51static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
52
53static inline void ast_load_palette_index(struct ast_private *ast,
54 u8 index, u8 red, u8 green,
55 u8 blue)
56{
57 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, red);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61 ast_io_write8(ast, AST_IO_DAC_DATA, green);
62 ast_io_read8(ast, AST_IO_SEQ_PORT);
63 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
64 ast_io_read8(ast, AST_IO_SEQ_PORT);
65}
66
67static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
68{
69 u16 *r, *g, *b;
70 int i;
71
72 if (!crtc->enabled)
73 return;
74
75 r = crtc->gamma_store;
76 g = r + crtc->gamma_size;
77 b = g + crtc->gamma_size;
78
79 for (i = 0; i < 256; i++)
80 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
81}
82
83static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
84 const struct drm_display_mode *mode,
85 struct drm_display_mode *adjusted_mode,
86 struct ast_vbios_mode_info *vbios_mode)
87{
88 u32 refresh_rate_index = 0, refresh_rate;
89 const struct ast_vbios_enhtable *best = NULL;
90 u32 hborder, vborder;
91 bool check_sync;
92
93 switch (format->cpp[0] * 8) {
94 case 8:
95 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
96 break;
97 case 16:
98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
99 break;
100 case 24:
101 case 32:
102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
103 break;
104 default:
105 return false;
106 }
107
108 switch (mode->crtc_hdisplay) {
109 case 640:
110 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
111 break;
112 case 800:
113 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
114 break;
115 case 1024:
116 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
117 break;
118 case 1280:
119 if (mode->crtc_vdisplay == 800)
120 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
121 else
122 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
123 break;
124 case 1360:
125 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
126 break;
127 case 1440:
128 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
129 break;
130 case 1600:
131 if (mode->crtc_vdisplay == 900)
132 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
133 else
134 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
135 break;
136 case 1680:
137 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
138 break;
139 case 1920:
140 if (mode->crtc_vdisplay == 1080)
141 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
142 else
143 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
144 break;
145 default:
146 return false;
147 }
148
149 refresh_rate = drm_mode_vrefresh(mode);
150 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
151
152 while (1) {
153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
154
155 while (loop->refresh_rate != 0xff) {
156 if ((check_sync) &&
157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
158 (loop->flags & PVSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
160 (loop->flags & NVSync)) ||
161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
162 (loop->flags & PHSync)) ||
163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
164 (loop->flags & NHSync)))) {
165 loop++;
166 continue;
167 }
168 if (loop->refresh_rate <= refresh_rate
169 && (!best || loop->refresh_rate > best->refresh_rate))
170 best = loop;
171 loop++;
172 }
173 if (best || !check_sync)
174 break;
175 check_sync = 0;
176 }
177
178 if (best)
179 vbios_mode->enh_table = best;
180
181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
183
184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
188 vbios_mode->enh_table->hfp;
189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
190 vbios_mode->enh_table->hfp +
191 vbios_mode->enh_table->hsync);
192
193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
197 vbios_mode->enh_table->vfp;
198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
199 vbios_mode->enh_table->vfp +
200 vbios_mode->enh_table->vsync);
201
202 return true;
203}
204
205static void ast_set_vbios_color_reg(struct ast_private *ast,
206 const struct drm_format_info *format,
207 const struct ast_vbios_mode_info *vbios_mode)
208{
209 u32 color_index;
210
211 switch (format->cpp[0]) {
212 case 1:
213 color_index = VGAModeIndex - 1;
214 break;
215 case 2:
216 color_index = HiCModeIndex;
217 break;
218 case 3:
219 case 4:
220 color_index = TrueCModeIndex;
221 break;
222 default:
223 return;
224 }
225
226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
227
228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
229
230 if (vbios_mode->enh_table->flags & NewModeInfo) {
231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
233 }
234}
235
236static void ast_set_vbios_mode_reg(struct ast_private *ast,
237 const struct drm_display_mode *adjusted_mode,
238 const struct ast_vbios_mode_info *vbios_mode)
239{
240 u32 refresh_rate_index, mode_id;
241
242 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
243 mode_id = vbios_mode->enh_table->mode_id;
244
245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
247
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
249
250 if (vbios_mode->enh_table->flags & NewModeInfo) {
251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
257 }
258}
259
260static void ast_set_std_reg(struct ast_private *ast,
261 struct drm_display_mode *mode,
262 struct ast_vbios_mode_info *vbios_mode)
263{
264 const struct ast_vbios_stdtable *stdtable;
265 u32 i;
266 u8 jreg;
267
268 stdtable = vbios_mode->std_table;
269
270 jreg = stdtable->misc;
271 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
272
273
274 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
275 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
276 for (i = 1; i < 4; i++) {
277 jreg = stdtable->seq[i];
278 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
279 }
280
281
282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
283 for (i = 0; i < 12; i++)
284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
285 for (i = 14; i < 19; i++)
286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
287 for (i = 20; i < 25; i++)
288 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
289
290
291 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
292 for (i = 0; i < 20; i++) {
293 jreg = stdtable->ar[i];
294 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
295 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
296 }
297 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
298 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
299
300 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
302
303
304 for (i = 0; i < 9; i++)
305 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
306}
307
308static void ast_set_crtc_reg(struct ast_private *ast,
309 struct drm_display_mode *mode,
310 struct ast_vbios_mode_info *vbios_mode)
311{
312 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
313 u16 temp, precache = 0;
314
315 if ((ast->chip == AST2500) &&
316 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
317 precache = 40;
318
319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
320
321 temp = (mode->crtc_htotal >> 3) - 5;
322 if (temp & 0x100)
323 jregAC |= 0x01;
324 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
325
326 temp = (mode->crtc_hdisplay >> 3) - 1;
327 if (temp & 0x100)
328 jregAC |= 0x04;
329 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
330
331 temp = (mode->crtc_hblank_start >> 3) - 1;
332 if (temp & 0x100)
333 jregAC |= 0x10;
334 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
335
336 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
337 if (temp & 0x20)
338 jreg05 |= 0x80;
339 if (temp & 0x40)
340 jregAD |= 0x01;
341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
342
343 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
344 if (temp & 0x100)
345 jregAC |= 0x40;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
347
348 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
349 if (temp & 0x20)
350 jregAD |= 0x04;
351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
352
353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
355
356
357 temp = (mode->crtc_vtotal) - 2;
358 if (temp & 0x100)
359 jreg07 |= 0x01;
360 if (temp & 0x200)
361 jreg07 |= 0x20;
362 if (temp & 0x400)
363 jregAE |= 0x01;
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
365
366 temp = (mode->crtc_vsync_start) - 1;
367 if (temp & 0x100)
368 jreg07 |= 0x04;
369 if (temp & 0x200)
370 jreg07 |= 0x80;
371 if (temp & 0x400)
372 jregAE |= 0x08;
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
374
375 temp = (mode->crtc_vsync_end - 1) & 0x3f;
376 if (temp & 0x10)
377 jregAE |= 0x20;
378 if (temp & 0x20)
379 jregAE |= 0x40;
380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
381
382 temp = mode->crtc_vdisplay - 1;
383 if (temp & 0x100)
384 jreg07 |= 0x02;
385 if (temp & 0x200)
386 jreg07 |= 0x40;
387 if (temp & 0x400)
388 jregAE |= 0x02;
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
390
391 temp = mode->crtc_vblank_start - 1;
392 if (temp & 0x100)
393 jreg07 |= 0x08;
394 if (temp & 0x200)
395 jreg09 |= 0x20;
396 if (temp & 0x400)
397 jregAE |= 0x04;
398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
399
400 temp = mode->crtc_vblank_end - 1;
401 if (temp & 0x100)
402 jregAE |= 0x10;
403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
404
405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
408
409 if (precache)
410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
411 else
412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
413
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
415}
416
417static void ast_set_offset_reg(struct ast_private *ast,
418 struct drm_framebuffer *fb)
419{
420 u16 offset;
421
422 offset = fb->pitches[0] >> 3;
423 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
425}
426
427static void ast_set_dclk_reg(struct ast_private *ast,
428 struct drm_display_mode *mode,
429 struct ast_vbios_mode_info *vbios_mode)
430{
431 const struct ast_vbios_dclk_info *clk_info;
432
433 if (ast->chip == AST2500)
434 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
435 else
436 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
437
438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
441 (clk_info->param3 & 0xc0) |
442 ((clk_info->param3 & 0x3) << 4));
443}
444
445static void ast_set_color_reg(struct ast_private *ast,
446 const struct drm_format_info *format)
447{
448 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
449
450 switch (format->cpp[0] * 8) {
451 case 8:
452 jregA0 = 0x70;
453 jregA3 = 0x01;
454 jregA8 = 0x00;
455 break;
456 case 15:
457 case 16:
458 jregA0 = 0x70;
459 jregA3 = 0x04;
460 jregA8 = 0x02;
461 break;
462 case 32:
463 jregA0 = 0x70;
464 jregA3 = 0x08;
465 jregA8 = 0x02;
466 break;
467 }
468
469 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
470 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
471 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
472}
473
474static void ast_set_crtthd_reg(struct ast_private *ast)
475{
476
477 if (ast->chip == AST2600) {
478 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0xe0);
479 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0xa0);
480 } else if (ast->chip == AST2300 || ast->chip == AST2400 ||
481 ast->chip == AST2500) {
482 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
483 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
484 } else if (ast->chip == AST2100 ||
485 ast->chip == AST1100 ||
486 ast->chip == AST2200 ||
487 ast->chip == AST2150) {
488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
489 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
490 } else {
491 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
492 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
493 }
494}
495
496static void ast_set_sync_reg(struct ast_private *ast,
497 struct drm_display_mode *mode,
498 struct ast_vbios_mode_info *vbios_mode)
499{
500 u8 jreg;
501
502 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
503 jreg &= ~0xC0;
504 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
505 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
506 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
507}
508
509static void ast_set_start_address_crt1(struct ast_private *ast,
510 unsigned offset)
511{
512 u32 addr;
513
514 addr = offset >> 2;
515 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
516 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
517 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
518
519}
520
521static void ast_wait_for_vretrace(struct ast_private *ast)
522{
523 unsigned long timeout = jiffies + HZ;
524 u8 vgair1;
525
526 do {
527 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
528 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
529}
530
531
532
533
534
535static const uint32_t ast_primary_plane_formats[] = {
536 DRM_FORMAT_XRGB8888,
537 DRM_FORMAT_RGB565,
538 DRM_FORMAT_C8,
539};
540
541static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
542 struct drm_atomic_state *state)
543{
544 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
545 plane);
546 struct drm_crtc_state *crtc_state;
547 struct ast_crtc_state *ast_crtc_state;
548 int ret;
549
550 if (!new_plane_state->crtc)
551 return 0;
552
553 crtc_state = drm_atomic_get_new_crtc_state(state,
554 new_plane_state->crtc);
555
556 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
557 DRM_PLANE_HELPER_NO_SCALING,
558 DRM_PLANE_HELPER_NO_SCALING,
559 false, true);
560 if (ret)
561 return ret;
562
563 if (!new_plane_state->visible)
564 return 0;
565
566 ast_crtc_state = to_ast_crtc_state(crtc_state);
567
568 ast_crtc_state->format = new_plane_state->fb->format;
569
570 return 0;
571}
572
573static void
574ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
575 struct drm_atomic_state *state)
576{
577 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
578 plane);
579 struct drm_device *dev = plane->dev;
580 struct ast_private *ast = to_ast_private(dev);
581 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
582 plane);
583 struct drm_gem_vram_object *gbo;
584 s64 gpu_addr;
585 struct drm_framebuffer *fb = new_state->fb;
586 struct drm_framebuffer *old_fb = old_state->fb;
587
588 if (!old_fb || (fb->format != old_fb->format)) {
589 struct drm_crtc_state *crtc_state = new_state->crtc->state;
590 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
591 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
592
593 ast_set_color_reg(ast, fb->format);
594 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
595 }
596
597 gbo = drm_gem_vram_of_gem(fb->obj[0]);
598 gpu_addr = drm_gem_vram_offset(gbo);
599 if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
600 return;
601
602 ast_set_offset_reg(ast, fb);
603 ast_set_start_address_crt1(ast, (u32)gpu_addr);
604
605 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
606}
607
608static void
609ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
610 struct drm_atomic_state *state)
611{
612 struct ast_private *ast = to_ast_private(plane->dev);
613
614 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
615}
616
617static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
618 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
619 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
620 .atomic_check = ast_primary_plane_helper_atomic_check,
621 .atomic_update = ast_primary_plane_helper_atomic_update,
622 .atomic_disable = ast_primary_plane_helper_atomic_disable,
623};
624
625static const struct drm_plane_funcs ast_primary_plane_funcs = {
626 .update_plane = drm_atomic_helper_update_plane,
627 .disable_plane = drm_atomic_helper_disable_plane,
628 .destroy = drm_plane_cleanup,
629 .reset = drm_atomic_helper_plane_reset,
630 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
631 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
632};
633
634static int ast_primary_plane_init(struct ast_private *ast)
635{
636 struct drm_device *dev = &ast->base;
637 struct drm_plane *primary_plane = &ast->primary_plane;
638 int ret;
639
640 ret = drm_universal_plane_init(dev, primary_plane, 0x01,
641 &ast_primary_plane_funcs,
642 ast_primary_plane_formats,
643 ARRAY_SIZE(ast_primary_plane_formats),
644 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
645 if (ret) {
646 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
647 return ret;
648 }
649 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
650
651 return 0;
652}
653
654
655
656
657
658static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
659{
660 union {
661 u32 ul;
662 u8 b[4];
663 } srcdata32[2], data32;
664 union {
665 u16 us;
666 u8 b[2];
667 } data16;
668 u32 csum = 0;
669 s32 alpha_dst_delta, last_alpha_dst_delta;
670 u8 __iomem *dstxor;
671 const u8 *srcxor;
672 int i, j;
673 u32 per_pixel_copy, two_pixel_copy;
674
675 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
676 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
677
678 srcxor = src;
679 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
680 per_pixel_copy = width & 1;
681 two_pixel_copy = width >> 1;
682
683 for (j = 0; j < height; j++) {
684 for (i = 0; i < two_pixel_copy; i++) {
685 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
686 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
687 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
688 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
689 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
690 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
691
692 writel(data32.ul, dstxor);
693 csum += data32.ul;
694
695 dstxor += 4;
696 srcxor += 8;
697
698 }
699
700 for (i = 0; i < per_pixel_copy; i++) {
701 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
702 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
703 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
704 writew(data16.us, dstxor);
705 csum += (u32)data16.us;
706
707 dstxor += 2;
708 srcxor += 4;
709 }
710 dstxor += last_alpha_dst_delta;
711 }
712
713
714 dst += AST_HWC_SIZE;
715 writel(csum, dst);
716 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
717 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
718 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
719 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
720}
721
722static void ast_set_cursor_base(struct ast_private *ast, u64 address)
723{
724 u8 addr0 = (address >> 3) & 0xff;
725 u8 addr1 = (address >> 11) & 0xff;
726 u8 addr2 = (address >> 19) & 0xff;
727
728 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
729 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
730 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
731}
732
733static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
734 u8 x_offset, u8 y_offset)
735{
736 u8 x0 = (x & 0x00ff);
737 u8 x1 = (x & 0x0f00) >> 8;
738 u8 y0 = (y & 0x00ff);
739 u8 y1 = (y & 0x0700) >> 8;
740
741 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
742 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
743 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
744 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
745 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
746 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
747}
748
749static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
750{
751 static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
752 AST_IO_VGACRCB_HWC_ENABLED);
753
754 u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
755
756 if (enabled)
757 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
758
759 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
760}
761
762static const uint32_t ast_cursor_plane_formats[] = {
763 DRM_FORMAT_ARGB8888,
764};
765
766static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
767 struct drm_atomic_state *state)
768{
769 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
770 plane);
771 struct drm_framebuffer *fb = new_plane_state->fb;
772 struct drm_crtc_state *crtc_state;
773 int ret;
774
775 if (!new_plane_state->crtc)
776 return 0;
777
778 crtc_state = drm_atomic_get_new_crtc_state(state,
779 new_plane_state->crtc);
780
781 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
782 DRM_PLANE_HELPER_NO_SCALING,
783 DRM_PLANE_HELPER_NO_SCALING,
784 true, true);
785 if (ret)
786 return ret;
787
788 if (!new_plane_state->visible)
789 return 0;
790
791 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
792 return -EINVAL;
793
794 return 0;
795}
796
797static void
798ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
799 struct drm_atomic_state *state)
800{
801 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
802 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
803 plane);
804 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
805 plane);
806 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
807 struct drm_framebuffer *fb = new_state->fb;
808 struct ast_private *ast = to_ast_private(plane->dev);
809 struct dma_buf_map dst_map =
810 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
811 u64 dst_off =
812 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
813 struct dma_buf_map src_map = shadow_plane_state->map[0];
814 unsigned int offset_x, offset_y;
815 u16 x, y;
816 u8 x_offset, y_offset;
817 u8 __iomem *dst;
818 u8 __iomem *sig;
819 const u8 *src;
820
821 src = src_map.vaddr;
822 dst = dst_map.vaddr_iomem;
823 sig = dst + AST_HWC_SIZE;
824
825
826
827
828
829
830 ast_update_cursor_image(dst, src, fb->width, fb->height);
831
832 if (new_state->fb != old_state->fb) {
833 ast_set_cursor_base(ast, dst_off);
834
835 ++ast_cursor_plane->next_hwc_index;
836 ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc);
837 }
838
839
840
841
842
843 writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
844 writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
845
846 offset_x = AST_MAX_HWC_WIDTH - fb->width;
847 offset_y = AST_MAX_HWC_HEIGHT - fb->height;
848
849 if (new_state->crtc_x < 0) {
850 x_offset = (-new_state->crtc_x) + offset_x;
851 x = 0;
852 } else {
853 x_offset = offset_x;
854 x = new_state->crtc_x;
855 }
856 if (new_state->crtc_y < 0) {
857 y_offset = (-new_state->crtc_y) + offset_y;
858 y = 0;
859 } else {
860 y_offset = offset_y;
861 y = new_state->crtc_y;
862 }
863
864 ast_set_cursor_location(ast, x, y, x_offset, y_offset);
865
866
867 ast_set_cursor_enabled(ast, true);
868}
869
870static void
871ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
872 struct drm_atomic_state *state)
873{
874 struct ast_private *ast = to_ast_private(plane->dev);
875
876 ast_set_cursor_enabled(ast, false);
877}
878
879static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
880 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
881 .atomic_check = ast_cursor_plane_helper_atomic_check,
882 .atomic_update = ast_cursor_plane_helper_atomic_update,
883 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
884};
885
886static void ast_cursor_plane_destroy(struct drm_plane *plane)
887{
888 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
889 size_t i;
890 struct drm_gem_vram_object *gbo;
891 struct dma_buf_map map;
892
893 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
894 gbo = ast_cursor_plane->hwc[i].gbo;
895 map = ast_cursor_plane->hwc[i].map;
896 drm_gem_vram_vunmap(gbo, &map);
897 drm_gem_vram_unpin(gbo);
898 drm_gem_vram_put(gbo);
899 }
900
901 drm_plane_cleanup(plane);
902}
903
904static const struct drm_plane_funcs ast_cursor_plane_funcs = {
905 .update_plane = drm_atomic_helper_update_plane,
906 .disable_plane = drm_atomic_helper_disable_plane,
907 .destroy = ast_cursor_plane_destroy,
908 DRM_GEM_SHADOW_PLANE_FUNCS,
909};
910
911static int ast_cursor_plane_init(struct ast_private *ast)
912{
913 struct drm_device *dev = &ast->base;
914 struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane;
915 struct drm_plane *cursor_plane = &ast_cursor_plane->base;
916 size_t size, i;
917 struct drm_gem_vram_object *gbo;
918 struct dma_buf_map map;
919 int ret;
920 s64 off;
921
922
923
924
925
926
927 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
928
929 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
930 gbo = drm_gem_vram_create(dev, size, 0);
931 if (IS_ERR(gbo)) {
932 ret = PTR_ERR(gbo);
933 goto err_hwc;
934 }
935 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
936 DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
937 if (ret)
938 goto err_drm_gem_vram_put;
939 ret = drm_gem_vram_vmap(gbo, &map);
940 if (ret)
941 goto err_drm_gem_vram_unpin;
942 off = drm_gem_vram_offset(gbo);
943 if (off < 0) {
944 ret = off;
945 goto err_drm_gem_vram_vunmap;
946 }
947 ast_cursor_plane->hwc[i].gbo = gbo;
948 ast_cursor_plane->hwc[i].map = map;
949 ast_cursor_plane->hwc[i].off = off;
950 }
951
952
953
954
955
956
957 ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
958 &ast_cursor_plane_funcs,
959 ast_cursor_plane_formats,
960 ARRAY_SIZE(ast_cursor_plane_formats),
961 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
962 if (ret) {
963 drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
964 goto err_hwc;
965 }
966 drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
967
968 return 0;
969
970err_hwc:
971 while (i) {
972 --i;
973 gbo = ast_cursor_plane->hwc[i].gbo;
974 map = ast_cursor_plane->hwc[i].map;
975err_drm_gem_vram_vunmap:
976 drm_gem_vram_vunmap(gbo, &map);
977err_drm_gem_vram_unpin:
978 drm_gem_vram_unpin(gbo);
979err_drm_gem_vram_put:
980 drm_gem_vram_put(gbo);
981 }
982 return ret;
983}
984
985
986
987
988
989static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
990{
991 struct ast_private *ast = to_ast_private(crtc->dev);
992
993
994
995
996 switch (mode) {
997 case DRM_MODE_DPMS_ON:
998 case DRM_MODE_DPMS_STANDBY:
999 case DRM_MODE_DPMS_SUSPEND:
1000 if (ast->tx_chip_type == AST_TX_DP501)
1001 ast_set_dp501_video_output(crtc->dev, 1);
1002 break;
1003 case DRM_MODE_DPMS_OFF:
1004 if (ast->tx_chip_type == AST_TX_DP501)
1005 ast_set_dp501_video_output(crtc->dev, 0);
1006 break;
1007 }
1008}
1009
1010static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1011 struct drm_atomic_state *state)
1012{
1013 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1014 crtc);
1015 struct drm_device *dev = crtc->dev;
1016 struct ast_crtc_state *ast_state;
1017 const struct drm_format_info *format;
1018 bool succ;
1019
1020 if (!crtc_state->enable)
1021 return 0;
1022
1023 ast_state = to_ast_crtc_state(crtc_state);
1024
1025 format = ast_state->format;
1026 if (drm_WARN_ON_ONCE(dev, !format))
1027 return -EINVAL;
1028
1029 succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1030 &crtc_state->adjusted_mode,
1031 &ast_state->vbios_mode_info);
1032 if (!succ)
1033 return -EINVAL;
1034
1035 return 0;
1036}
1037
1038static void
1039ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1040 struct drm_atomic_state *state)
1041{
1042 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1043 crtc);
1044 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1045 crtc);
1046 struct ast_private *ast = to_ast_private(crtc->dev);
1047 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1048 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1049
1050
1051
1052
1053
1054 if (old_ast_crtc_state->format != ast_crtc_state->format)
1055 ast_crtc_load_lut(ast, crtc);
1056}
1057
1058static void
1059ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1060 struct drm_atomic_state *state)
1061{
1062 struct drm_device *dev = crtc->dev;
1063 struct ast_private *ast = to_ast_private(dev);
1064 struct drm_crtc_state *crtc_state = crtc->state;
1065 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1066 struct ast_vbios_mode_info *vbios_mode_info =
1067 &ast_crtc_state->vbios_mode_info;
1068 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1069
1070 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1071 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1072 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1073 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1074 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1075 ast_set_crtthd_reg(ast);
1076 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1077
1078 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1079}
1080
1081static void
1082ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1083 struct drm_atomic_state *state)
1084{
1085 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1086 crtc);
1087 struct drm_device *dev = crtc->dev;
1088 struct ast_private *ast = to_ast_private(dev);
1089
1090 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1103
1104
1105
1106
1107
1108 ast_wait_for_vretrace(ast);
1109}
1110
1111static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1112 .atomic_check = ast_crtc_helper_atomic_check,
1113 .atomic_flush = ast_crtc_helper_atomic_flush,
1114 .atomic_enable = ast_crtc_helper_atomic_enable,
1115 .atomic_disable = ast_crtc_helper_atomic_disable,
1116};
1117
1118static void ast_crtc_reset(struct drm_crtc *crtc)
1119{
1120 struct ast_crtc_state *ast_state =
1121 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1122
1123 if (crtc->state)
1124 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1125
1126 if (ast_state)
1127 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1128 else
1129 __drm_atomic_helper_crtc_reset(crtc, NULL);
1130}
1131
1132static struct drm_crtc_state *
1133ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1134{
1135 struct ast_crtc_state *new_ast_state, *ast_state;
1136 struct drm_device *dev = crtc->dev;
1137
1138 if (drm_WARN_ON(dev, !crtc->state))
1139 return NULL;
1140
1141 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1142 if (!new_ast_state)
1143 return NULL;
1144 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1145
1146 ast_state = to_ast_crtc_state(crtc->state);
1147
1148 new_ast_state->format = ast_state->format;
1149 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1150 sizeof(new_ast_state->vbios_mode_info));
1151
1152 return &new_ast_state->base;
1153}
1154
1155static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1156 struct drm_crtc_state *state)
1157{
1158 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1159
1160 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1161 kfree(ast_state);
1162}
1163
1164static const struct drm_crtc_funcs ast_crtc_funcs = {
1165 .reset = ast_crtc_reset,
1166 .destroy = drm_crtc_cleanup,
1167 .set_config = drm_atomic_helper_set_config,
1168 .page_flip = drm_atomic_helper_page_flip,
1169 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1170 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1171};
1172
1173static int ast_crtc_init(struct drm_device *dev)
1174{
1175 struct ast_private *ast = to_ast_private(dev);
1176 struct drm_crtc *crtc = &ast->crtc;
1177 int ret;
1178
1179 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1180 &ast->cursor_plane.base, &ast_crtc_funcs,
1181 NULL);
1182 if (ret)
1183 return ret;
1184
1185 drm_mode_crtc_set_gamma_size(crtc, 256);
1186 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1187
1188 return 0;
1189}
1190
1191
1192
1193
1194
1195static int ast_encoder_init(struct drm_device *dev)
1196{
1197 struct ast_private *ast = to_ast_private(dev);
1198 struct drm_encoder *encoder = &ast->encoder;
1199 int ret;
1200
1201 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1202 if (ret)
1203 return ret;
1204
1205 encoder->possible_crtcs = 1;
1206
1207 return 0;
1208}
1209
1210
1211
1212
1213
1214static int ast_get_modes(struct drm_connector *connector)
1215{
1216 struct ast_connector *ast_connector = to_ast_connector(connector);
1217 struct ast_private *ast = to_ast_private(connector->dev);
1218 struct edid *edid;
1219 int ret;
1220 bool flags = false;
1221 if (ast->tx_chip_type == AST_TX_DP501) {
1222 ast->dp501_maxclk = 0xff;
1223 edid = kmalloc(128, GFP_KERNEL);
1224 if (!edid)
1225 return -ENOMEM;
1226
1227 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1228 if (flags)
1229 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1230 else
1231 kfree(edid);
1232 }
1233 if (!flags)
1234 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1235 if (edid) {
1236 drm_connector_update_edid_property(&ast_connector->base, edid);
1237 ret = drm_add_edid_modes(connector, edid);
1238 kfree(edid);
1239 return ret;
1240 } else
1241 drm_connector_update_edid_property(&ast_connector->base, NULL);
1242 return 0;
1243}
1244
1245static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1246 struct drm_display_mode *mode)
1247{
1248 struct ast_private *ast = to_ast_private(connector->dev);
1249 int flags = MODE_NOMODE;
1250 uint32_t jtemp;
1251
1252 if (ast->support_wide_screen) {
1253 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1254 return MODE_OK;
1255 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1256 return MODE_OK;
1257 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1258 return MODE_OK;
1259 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1260 return MODE_OK;
1261 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1262 return MODE_OK;
1263
1264 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1265 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1266 (ast->chip == AST2500)) {
1267 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1268 return MODE_OK;
1269
1270 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1271 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1272 if (jtemp & 0x01)
1273 return MODE_NOMODE;
1274 else
1275 return MODE_OK;
1276 }
1277 }
1278 }
1279 switch (mode->hdisplay) {
1280 case 640:
1281 if (mode->vdisplay == 480) flags = MODE_OK;
1282 break;
1283 case 800:
1284 if (mode->vdisplay == 600) flags = MODE_OK;
1285 break;
1286 case 1024:
1287 if (mode->vdisplay == 768) flags = MODE_OK;
1288 break;
1289 case 1280:
1290 if (mode->vdisplay == 1024) flags = MODE_OK;
1291 break;
1292 case 1600:
1293 if (mode->vdisplay == 1200) flags = MODE_OK;
1294 break;
1295 default:
1296 return flags;
1297 }
1298
1299 return flags;
1300}
1301
1302static void ast_connector_destroy(struct drm_connector *connector)
1303{
1304 struct ast_connector *ast_connector = to_ast_connector(connector);
1305 ast_i2c_destroy(ast_connector->i2c);
1306 drm_connector_cleanup(connector);
1307}
1308
1309static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1310 .get_modes = ast_get_modes,
1311 .mode_valid = ast_mode_valid,
1312};
1313
1314static const struct drm_connector_funcs ast_connector_funcs = {
1315 .reset = drm_atomic_helper_connector_reset,
1316 .fill_modes = drm_helper_probe_single_connector_modes,
1317 .destroy = ast_connector_destroy,
1318 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1319 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1320};
1321
1322static int ast_connector_init(struct drm_device *dev)
1323{
1324 struct ast_private *ast = to_ast_private(dev);
1325 struct ast_connector *ast_connector = &ast->connector;
1326 struct drm_connector *connector = &ast_connector->base;
1327 struct drm_encoder *encoder = &ast->encoder;
1328
1329 ast_connector->i2c = ast_i2c_create(dev);
1330 if (!ast_connector->i2c)
1331 drm_err(dev, "failed to add ddc bus for connector\n");
1332
1333 drm_connector_init_with_ddc(dev, connector,
1334 &ast_connector_funcs,
1335 DRM_MODE_CONNECTOR_VGA,
1336 &ast_connector->i2c->adapter);
1337
1338 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1339
1340 connector->interlace_allowed = 0;
1341 connector->doublescan_allowed = 0;
1342
1343 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1344
1345 drm_connector_attach_encoder(connector, encoder);
1346
1347 return 0;
1348}
1349
1350
1351
1352
1353
1354static const struct drm_mode_config_helper_funcs
1355ast_mode_config_helper_funcs = {
1356 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1357};
1358
1359static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1360 .fb_create = drm_gem_fb_create,
1361 .mode_valid = drm_vram_helper_mode_valid,
1362 .atomic_check = drm_atomic_helper_check,
1363 .atomic_commit = drm_atomic_helper_commit,
1364};
1365
1366int ast_mode_config_init(struct ast_private *ast)
1367{
1368 struct drm_device *dev = &ast->base;
1369 struct pci_dev *pdev = to_pci_dev(dev->dev);
1370 int ret;
1371
1372 ret = drmm_mode_config_init(dev);
1373 if (ret)
1374 return ret;
1375
1376 dev->mode_config.funcs = &ast_mode_config_funcs;
1377 dev->mode_config.min_width = 0;
1378 dev->mode_config.min_height = 0;
1379 dev->mode_config.preferred_depth = 24;
1380 dev->mode_config.prefer_shadow = 1;
1381 dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1382
1383 if (ast->chip == AST2100 ||
1384 ast->chip == AST2200 ||
1385 ast->chip == AST2300 ||
1386 ast->chip == AST2400 ||
1387 ast->chip == AST2500) {
1388 dev->mode_config.max_width = 1920;
1389 dev->mode_config.max_height = 2048;
1390 } else {
1391 dev->mode_config.max_width = 1600;
1392 dev->mode_config.max_height = 1200;
1393 }
1394
1395 dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1396
1397
1398 ret = ast_primary_plane_init(ast);
1399 if (ret)
1400 return ret;
1401
1402 ret = ast_cursor_plane_init(ast);
1403 if (ret)
1404 return ret;
1405
1406 ast_crtc_init(dev);
1407 ast_encoder_init(dev);
1408 ast_connector_init(dev);
1409
1410 drm_mode_config_reset(dev);
1411
1412 return 0;
1413}
1414
1415static int get_clock(void *i2c_priv)
1416{
1417 struct ast_i2c_chan *i2c = i2c_priv;
1418 struct ast_private *ast = to_ast_private(i2c->dev);
1419 uint32_t val, val2, count, pass;
1420
1421 count = 0;
1422 pass = 0;
1423 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1424 do {
1425 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1426 if (val == val2) {
1427 pass++;
1428 } else {
1429 pass = 0;
1430 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1431 }
1432 } while ((pass < 5) && (count++ < 0x10000));
1433
1434 return val & 1 ? 1 : 0;
1435}
1436
1437static int get_data(void *i2c_priv)
1438{
1439 struct ast_i2c_chan *i2c = i2c_priv;
1440 struct ast_private *ast = to_ast_private(i2c->dev);
1441 uint32_t val, val2, count, pass;
1442
1443 count = 0;
1444 pass = 0;
1445 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1446 do {
1447 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1448 if (val == val2) {
1449 pass++;
1450 } else {
1451 pass = 0;
1452 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1453 }
1454 } while ((pass < 5) && (count++ < 0x10000));
1455
1456 return val & 1 ? 1 : 0;
1457}
1458
1459static void set_clock(void *i2c_priv, int clock)
1460{
1461 struct ast_i2c_chan *i2c = i2c_priv;
1462 struct ast_private *ast = to_ast_private(i2c->dev);
1463 int i;
1464 u8 ujcrb7, jtemp;
1465
1466 for (i = 0; i < 0x10000; i++) {
1467 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1468 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1469 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1470 if (ujcrb7 == jtemp)
1471 break;
1472 }
1473}
1474
1475static void set_data(void *i2c_priv, int data)
1476{
1477 struct ast_i2c_chan *i2c = i2c_priv;
1478 struct ast_private *ast = to_ast_private(i2c->dev);
1479 int i;
1480 u8 ujcrb7, jtemp;
1481
1482 for (i = 0; i < 0x10000; i++) {
1483 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1484 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1485 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1486 if (ujcrb7 == jtemp)
1487 break;
1488 }
1489}
1490
1491static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1492{
1493 struct ast_i2c_chan *i2c;
1494 int ret;
1495
1496 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1497 if (!i2c)
1498 return NULL;
1499
1500 i2c->adapter.owner = THIS_MODULE;
1501 i2c->adapter.class = I2C_CLASS_DDC;
1502 i2c->adapter.dev.parent = dev->dev;
1503 i2c->dev = dev;
1504 i2c_set_adapdata(&i2c->adapter, i2c);
1505 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1506 "AST i2c bit bus");
1507 i2c->adapter.algo_data = &i2c->bit;
1508
1509 i2c->bit.udelay = 20;
1510 i2c->bit.timeout = 2;
1511 i2c->bit.data = i2c;
1512 i2c->bit.setsda = set_data;
1513 i2c->bit.setscl = set_clock;
1514 i2c->bit.getsda = get_data;
1515 i2c->bit.getscl = get_clock;
1516 ret = i2c_bit_add_bus(&i2c->adapter);
1517 if (ret) {
1518 drm_err(dev, "Failed to register bit i2c\n");
1519 goto out_free;
1520 }
1521
1522 return i2c;
1523out_free:
1524 kfree(i2c);
1525 return NULL;
1526}
1527
1528static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1529{
1530 if (!i2c)
1531 return;
1532 i2c_del_adapter(&i2c->adapter);
1533 kfree(i2c);
1534}
1535
