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31#ifndef __MGA_DRV_H__
32#define __MGA_DRV_H__
33
34#include <linux/irqreturn.h>
35#include <linux/pci.h>
36#include <linux/slab.h>
37
38#include <drm/drm_device.h>
39#include <drm/drm_file.h>
40#include <drm/drm_ioctl.h>
41#include <drm/drm_irq.h>
42#include <drm/drm_legacy.h>
43#include <drm/drm_print.h>
44#include <drm/drm_sarea.h>
45#include <drm/drm_vblank.h>
46#include <drm/mga_drm.h>
47
48
49
50
51#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
52
53#define DRIVER_NAME "mga"
54#define DRIVER_DESC "Matrox G200/G400"
55#define DRIVER_DATE "20051102"
56
57#define DRIVER_MAJOR 3
58#define DRIVER_MINOR 2
59#define DRIVER_PATCHLEVEL 1
60
61typedef struct drm_mga_primary_buffer {
62 u8 *start;
63 u8 *end;
64 int size;
65
66 u32 tail;
67 int space;
68 volatile long wrapped;
69
70 volatile u32 *status;
71
72 u32 last_flush;
73 u32 last_wrap;
74
75 u32 high_mark;
76} drm_mga_primary_buffer_t;
77
78typedef struct drm_mga_freelist {
79 struct drm_mga_freelist *next;
80 struct drm_mga_freelist *prev;
81 drm_mga_age_t age;
82 struct drm_buf *buf;
83} drm_mga_freelist_t;
84
85typedef struct {
86 drm_mga_freelist_t *list_entry;
87 int discard;
88 int dispatched;
89} drm_mga_buf_priv_t;
90
91typedef struct drm_mga_private {
92 drm_mga_primary_buffer_t prim;
93 drm_mga_sarea_t *sarea_priv;
94
95 drm_mga_freelist_t *head;
96 drm_mga_freelist_t *tail;
97
98 unsigned int warp_pipe;
99 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
100
101 int chipset;
102 int usec_timeout;
103
104
105
106
107
108
109 int used_new_dma_init;
110
111
112
113
114
115 u32 dma_access;
116
117
118
119
120
121
122 u32 wagp_enable;
123
124
125
126
127
128
129
130 resource_size_t mmio_base;
131 resource_size_t mmio_size;
132
133
134 u32 clear_cmd;
135 u32 maccess;
136
137 atomic_t vbl_received;
138 wait_queue_head_t fence_queue;
139 atomic_t last_fence_retired;
140 u32 next_fence_to_post;
141
142 unsigned int fb_cpp;
143 unsigned int front_offset;
144 unsigned int front_pitch;
145 unsigned int back_offset;
146 unsigned int back_pitch;
147
148 unsigned int depth_cpp;
149 unsigned int depth_offset;
150 unsigned int depth_pitch;
151
152 unsigned int texture_offset;
153 unsigned int texture_size;
154
155 drm_local_map_t *sarea;
156 drm_local_map_t *mmio;
157 drm_local_map_t *status;
158 drm_local_map_t *warp;
159 drm_local_map_t *primary;
160 drm_local_map_t *agp_textures;
161
162 unsigned long agp_handle;
163 unsigned int agp_size;
164} drm_mga_private_t;
165
166extern const struct drm_ioctl_desc mga_ioctls[];
167extern int mga_max_ioctl;
168
169
170extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
171 struct drm_file *file_priv);
172extern int mga_dma_init(struct drm_device *dev, void *data,
173 struct drm_file *file_priv);
174extern int mga_getparam(struct drm_device *dev, void *data,
175 struct drm_file *file_priv);
176extern int mga_dma_flush(struct drm_device *dev, void *data,
177 struct drm_file *file_priv);
178extern int mga_dma_reset(struct drm_device *dev, void *data,
179 struct drm_file *file_priv);
180extern int mga_dma_buffers(struct drm_device *dev, void *data,
181 struct drm_file *file_priv);
182extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
183extern void mga_driver_unload(struct drm_device *dev);
184extern void mga_driver_lastclose(struct drm_device *dev);
185extern int mga_driver_dma_quiescent(struct drm_device *dev);
186
187extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
188
189extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
190extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
191extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
192
193extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
194
195
196extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
197extern int mga_warp_init(drm_mga_private_t *dev_priv);
198
199
200extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
201extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
202extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
203extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
204extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
205extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
206extern void mga_driver_irq_preinstall(struct drm_device *dev);
207extern int mga_driver_irq_postinstall(struct drm_device *dev);
208extern void mga_driver_irq_uninstall(struct drm_device *dev);
209extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
210 unsigned long arg);
211
212#define mga_flush_write_combine() wmb()
213
214#define MGA_READ8(reg) \
215 readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
216#define MGA_READ(reg) \
217 readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
218#define MGA_WRITE8(reg, val) \
219 writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
220#define MGA_WRITE(reg, val) \
221 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
222
223#define DWGREG0 0x1c00
224#define DWGREG0_END 0x1dff
225#define DWGREG1 0x2c00
226#define DWGREG1_END 0x2dff
227
228#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
229#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
230#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
231#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
232
233
234
235
236
237#define MGA_EMIT_STATE(dev_priv, dirty) \
238do { \
239 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
240 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
241 mga_g400_emit_state(dev_priv); \
242 else \
243 mga_g200_emit_state(dev_priv); \
244 } \
245} while (0)
246
247#define WRAP_TEST_WITH_RETURN(dev_priv) \
248do { \
249 if (test_bit(0, &dev_priv->prim.wrapped)) { \
250 if (mga_is_idle(dev_priv)) { \
251 mga_do_dma_wrap_end(dev_priv); \
252 } else if (dev_priv->prim.space < \
253 dev_priv->prim.high_mark) { \
254 if (MGA_DMA_DEBUG) \
255 DRM_INFO("wrap...\n"); \
256 return -EBUSY; \
257 } \
258 } \
259} while (0)
260
261#define WRAP_WAIT_WITH_RETURN(dev_priv) \
262do { \
263 if (test_bit(0, &dev_priv->prim.wrapped)) { \
264 if (mga_do_wait_for_idle(dev_priv) < 0) { \
265 if (MGA_DMA_DEBUG) \
266 DRM_INFO("wrap...\n"); \
267 return -EBUSY; \
268 } \
269 mga_do_dma_wrap_end(dev_priv); \
270 } \
271} while (0)
272
273
274
275
276
277#define MGA_VERBOSE 0
278
279#define DMA_LOCALS unsigned int write; volatile u8 *prim;
280
281#define DMA_BLOCK_SIZE (5 * sizeof(u32))
282
283#define BEGIN_DMA(n) \
284do { \
285 if (MGA_VERBOSE) { \
286 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
287 DRM_INFO(" space=0x%x req=0x%zx\n", \
288 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
289 } \
290 prim = dev_priv->prim.start; \
291 write = dev_priv->prim.tail; \
292} while (0)
293
294#define BEGIN_DMA_WRAP() \
295do { \
296 if (MGA_VERBOSE) { \
297 DRM_INFO("BEGIN_DMA()\n"); \
298 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
299 } \
300 prim = dev_priv->prim.start; \
301 write = dev_priv->prim.tail; \
302} while (0)
303
304#define ADVANCE_DMA() \
305do { \
306 dev_priv->prim.tail = write; \
307 if (MGA_VERBOSE) \
308 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
309 write, dev_priv->prim.space); \
310} while (0)
311
312#define FLUSH_DMA() \
313do { \
314 if (0) { \
315 DRM_INFO("\n"); \
316 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
317 dev_priv->prim.tail, \
318 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
319 dev_priv->primary->offset)); \
320 } \
321 if (!test_bit(0, &dev_priv->prim.wrapped)) { \
322 if (dev_priv->prim.space < dev_priv->prim.high_mark) \
323 mga_do_dma_wrap_start(dev_priv); \
324 else \
325 mga_do_dma_flush(dev_priv); \
326 } \
327} while (0)
328
329
330
331#define DMA_WRITE(offset, val) \
332do { \
333 if (MGA_VERBOSE) \
334 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04zx\n", \
335 (u32)(val), write + (offset) * sizeof(u32)); \
336 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
337} while (0)
338
339#define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
340do { \
341 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
342 (DMAREG(reg1) << 8) | \
343 (DMAREG(reg2) << 16) | \
344 (DMAREG(reg3) << 24))); \
345 DMA_WRITE(1, val0); \
346 DMA_WRITE(2, val1); \
347 DMA_WRITE(3, val2); \
348 DMA_WRITE(4, val3); \
349 write += DMA_BLOCK_SIZE; \
350} while (0)
351
352
353
354
355#define SET_AGE(age, h, w) \
356do { \
357 (age)->head = h; \
358 (age)->wrap = w; \
359} while (0)
360
361#define TEST_AGE(age, h, w) ((age)->wrap < w || \
362 ((age)->wrap == w && \
363 (age)->head < h))
364
365#define AGE_BUFFER(buf_priv) \
366do { \
367 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
368 if ((buf_priv)->dispatched) { \
369 entry->age.head = (dev_priv->prim.tail + \
370 dev_priv->primary->offset); \
371 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
372 } else { \
373 entry->age.head = 0; \
374 entry->age.wrap = 0; \
375 } \
376} while (0)
377
378#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
379 MGA_DWGENGSTS | \
380 MGA_ENDPRDMASTS)
381#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
382 MGA_ENDPRDMASTS)
383
384#define MGA_DMA_DEBUG 0
385
386
387
388#define MGA_CRTC_INDEX 0x1fd4
389#define MGA_CRTC_DATA 0x1fd5
390
391
392#define MGA_VINTCLR (1 << 4)
393#define MGA_VINTEN (1 << 5)
394
395#define MGA_ALPHACTRL 0x2c7c
396#define MGA_AR0 0x1c60
397#define MGA_AR1 0x1c64
398#define MGA_AR2 0x1c68
399#define MGA_AR3 0x1c6c
400#define MGA_AR4 0x1c70
401#define MGA_AR5 0x1c74
402#define MGA_AR6 0x1c78
403
404#define MGA_CXBNDRY 0x1c80
405#define MGA_CXLEFT 0x1ca0
406#define MGA_CXRIGHT 0x1ca4
407
408#define MGA_DMAPAD 0x1c54
409#define MGA_DSTORG 0x2cb8
410#define MGA_DWGCTL 0x1c00
411# define MGA_OPCOD_MASK (15 << 0)
412# define MGA_OPCOD_TRAP (4 << 0)
413# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
414# define MGA_OPCOD_BITBLT (8 << 0)
415# define MGA_OPCOD_ILOAD (9 << 0)
416# define MGA_ATYPE_MASK (7 << 4)
417# define MGA_ATYPE_RPL (0 << 4)
418# define MGA_ATYPE_RSTR (1 << 4)
419# define MGA_ATYPE_ZI (3 << 4)
420# define MGA_ATYPE_BLK (4 << 4)
421# define MGA_ATYPE_I (7 << 4)
422# define MGA_LINEAR (1 << 7)
423# define MGA_ZMODE_MASK (7 << 8)
424# define MGA_ZMODE_NOZCMP (0 << 8)
425# define MGA_ZMODE_ZE (2 << 8)
426# define MGA_ZMODE_ZNE (3 << 8)
427# define MGA_ZMODE_ZLT (4 << 8)
428# define MGA_ZMODE_ZLTE (5 << 8)
429# define MGA_ZMODE_ZGT (6 << 8)
430# define MGA_ZMODE_ZGTE (7 << 8)
431# define MGA_SOLID (1 << 11)
432# define MGA_ARZERO (1 << 12)
433# define MGA_SGNZERO (1 << 13)
434# define MGA_SHIFTZERO (1 << 14)
435# define MGA_BOP_MASK (15 << 16)
436# define MGA_BOP_ZERO (0 << 16)
437# define MGA_BOP_DST (10 << 16)
438# define MGA_BOP_SRC (12 << 16)
439# define MGA_BOP_ONE (15 << 16)
440# define MGA_TRANS_SHIFT 20
441# define MGA_TRANS_MASK (15 << 20)
442# define MGA_BLTMOD_MASK (15 << 25)
443# define MGA_BLTMOD_BMONOLEF (0 << 25)
444# define MGA_BLTMOD_BMONOWF (4 << 25)
445# define MGA_BLTMOD_PLAN (1 << 25)
446# define MGA_BLTMOD_BFCOL (2 << 25)
447# define MGA_BLTMOD_BU32BGR (3 << 25)
448# define MGA_BLTMOD_BU32RGB (7 << 25)
449# define MGA_BLTMOD_BU24BGR (11 << 25)
450# define MGA_BLTMOD_BU24RGB (15 << 25)
451# define MGA_PATTERN (1 << 29)
452# define MGA_TRANSC (1 << 30)
453# define MGA_CLIPDIS (1 << 31)
454#define MGA_DWGSYNC 0x2c4c
455
456#define MGA_FCOL 0x1c24
457#define MGA_FIFOSTATUS 0x1e10
458#define MGA_FOGCOL 0x1cf4
459#define MGA_FXBNDRY 0x1c84
460#define MGA_FXLEFT 0x1ca8
461#define MGA_FXRIGHT 0x1cac
462
463#define MGA_ICLEAR 0x1e18
464# define MGA_SOFTRAPICLR (1 << 0)
465# define MGA_VLINEICLR (1 << 5)
466#define MGA_IEN 0x1e1c
467# define MGA_SOFTRAPIEN (1 << 0)
468# define MGA_VLINEIEN (1 << 5)
469
470#define MGA_LEN 0x1c5c
471
472#define MGA_MACCESS 0x1c04
473
474#define MGA_PITCH 0x1c8c
475#define MGA_PLNWT 0x1c1c
476#define MGA_PRIMADDRESS 0x1e58
477# define MGA_DMA_GENERAL (0 << 0)
478# define MGA_DMA_BLIT (1 << 0)
479# define MGA_DMA_VECTOR (2 << 0)
480# define MGA_DMA_VERTEX (3 << 0)
481#define MGA_PRIMEND 0x1e5c
482# define MGA_PRIMNOSTART (1 << 0)
483# define MGA_PAGPXFER (1 << 1)
484#define MGA_PRIMPTR 0x1e50
485# define MGA_PRIMPTREN0 (1 << 0)
486# define MGA_PRIMPTREN1 (1 << 1)
487
488#define MGA_RST 0x1e40
489# define MGA_SOFTRESET (1 << 0)
490# define MGA_SOFTEXTRST (1 << 1)
491
492#define MGA_SECADDRESS 0x2c40
493#define MGA_SECEND 0x2c44
494#define MGA_SETUPADDRESS 0x2cd0
495#define MGA_SETUPEND 0x2cd4
496#define MGA_SGN 0x1c58
497#define MGA_SOFTRAP 0x2c48
498#define MGA_SRCORG 0x2cb4
499# define MGA_SRMMAP_MASK (1 << 0)
500# define MGA_SRCMAP_FB (0 << 0)
501# define MGA_SRCMAP_SYSMEM (1 << 0)
502# define MGA_SRCACC_MASK (1 << 1)
503# define MGA_SRCACC_PCI (0 << 1)
504# define MGA_SRCACC_AGP (1 << 1)
505#define MGA_STATUS 0x1e14
506# define MGA_SOFTRAPEN (1 << 0)
507# define MGA_VSYNCPEN (1 << 4)
508# define MGA_VLINEPEN (1 << 5)
509# define MGA_DWGENGSTS (1 << 16)
510# define MGA_ENDPRDMASTS (1 << 17)
511#define MGA_STENCIL 0x2cc8
512#define MGA_STENCILCTL 0x2ccc
513
514#define MGA_TDUALSTAGE0 0x2cf8
515#define MGA_TDUALSTAGE1 0x2cfc
516#define MGA_TEXBORDERCOL 0x2c5c
517#define MGA_TEXCTL 0x2c30
518#define MGA_TEXCTL2 0x2c3c
519# define MGA_DUALTEX (1 << 7)
520# define MGA_G400_TC2_MAGIC (1 << 15)
521# define MGA_MAP1_ENABLE (1 << 31)
522#define MGA_TEXFILTER 0x2c58
523#define MGA_TEXHEIGHT 0x2c2c
524#define MGA_TEXORG 0x2c24
525# define MGA_TEXORGMAP_MASK (1 << 0)
526# define MGA_TEXORGMAP_FB (0 << 0)
527# define MGA_TEXORGMAP_SYSMEM (1 << 0)
528# define MGA_TEXORGACC_MASK (1 << 1)
529# define MGA_TEXORGACC_PCI (0 << 1)
530# define MGA_TEXORGACC_AGP (1 << 1)
531#define MGA_TEXORG1 0x2ca4
532#define MGA_TEXORG2 0x2ca8
533#define MGA_TEXORG3 0x2cac
534#define MGA_TEXORG4 0x2cb0
535#define MGA_TEXTRANS 0x2c34
536#define MGA_TEXTRANSHIGH 0x2c38
537#define MGA_TEXWIDTH 0x2c28
538
539#define MGA_WACCEPTSEQ 0x1dd4
540#define MGA_WCODEADDR 0x1e6c
541#define MGA_WFLAG 0x1dc4
542#define MGA_WFLAG1 0x1de0
543#define MGA_WFLAGNB 0x1e64
544#define MGA_WFLAGNB1 0x1e08
545#define MGA_WGETMSB 0x1dc8
546#define MGA_WIADDR 0x1dc0
547#define MGA_WIADDR2 0x1dd8
548# define MGA_WMODE_SUSPEND (0 << 0)
549# define MGA_WMODE_RESUME (1 << 0)
550# define MGA_WMODE_JUMP (2 << 0)
551# define MGA_WMODE_START (3 << 0)
552# define MGA_WAGP_ENABLE (1 << 2)
553#define MGA_WMISC 0x1e70
554# define MGA_WUCODECACHE_ENABLE (1 << 0)
555# define MGA_WMASTER_ENABLE (1 << 1)
556# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
557#define MGA_WVRTXSZ 0x1dcc
558
559#define MGA_YBOT 0x1c9c
560#define MGA_YDST 0x1c90
561#define MGA_YDSTLEN 0x1c88
562#define MGA_YDSTORG 0x1c94
563#define MGA_YTOP 0x1c98
564
565#define MGA_ZORG 0x1c0c
566
567
568
569#define MGA_EXEC 0x0100
570
571
572
573#define MGA_AGP_PLL 0x1e4c
574# define MGA_AGP2XPLL_DISABLE (0 << 0)
575# define MGA_AGP2XPLL_ENABLE (1 << 0)
576
577
578
579#define MGA_WR0 0x2d00
580#define MGA_WR1 0x2d04
581#define MGA_WR2 0x2d08
582#define MGA_WR3 0x2d0c
583#define MGA_WR4 0x2d10
584#define MGA_WR5 0x2d14
585#define MGA_WR6 0x2d18
586#define MGA_WR7 0x2d1c
587#define MGA_WR8 0x2d20
588#define MGA_WR9 0x2d24
589#define MGA_WR10 0x2d28
590#define MGA_WR11 0x2d2c
591#define MGA_WR12 0x2d30
592#define MGA_WR13 0x2d34
593#define MGA_WR14 0x2d38
594#define MGA_WR15 0x2d3c
595#define MGA_WR16 0x2d40
596#define MGA_WR17 0x2d44
597#define MGA_WR18 0x2d48
598#define MGA_WR19 0x2d4c
599#define MGA_WR20 0x2d50
600#define MGA_WR21 0x2d54
601#define MGA_WR22 0x2d58
602#define MGA_WR23 0x2d5c
603#define MGA_WR24 0x2d60
604#define MGA_WR25 0x2d64
605#define MGA_WR26 0x2d68
606#define MGA_WR27 0x2d6c
607#define MGA_WR28 0x2d70
608#define MGA_WR29 0x2d74
609#define MGA_WR30 0x2d78
610#define MGA_WR31 0x2d7c
611#define MGA_WR32 0x2d80
612#define MGA_WR33 0x2d84
613#define MGA_WR34 0x2d88
614#define MGA_WR35 0x2d8c
615#define MGA_WR36 0x2d90
616#define MGA_WR37 0x2d94
617#define MGA_WR38 0x2d98
618#define MGA_WR39 0x2d9c
619#define MGA_WR40 0x2da0
620#define MGA_WR41 0x2da4
621#define MGA_WR42 0x2da8
622#define MGA_WR43 0x2dac
623#define MGA_WR44 0x2db0
624#define MGA_WR45 0x2db4
625#define MGA_WR46 0x2db8
626#define MGA_WR47 0x2dbc
627#define MGA_WR48 0x2dc0
628#define MGA_WR49 0x2dc4
629#define MGA_WR50 0x2dc8
630#define MGA_WR51 0x2dcc
631#define MGA_WR52 0x2dd0
632#define MGA_WR53 0x2dd4
633#define MGA_WR54 0x2dd8
634#define MGA_WR55 0x2ddc
635#define MGA_WR56 0x2de0
636#define MGA_WR57 0x2de4
637#define MGA_WR58 0x2de8
638#define MGA_WR59 0x2dec
639#define MGA_WR60 0x2df0
640#define MGA_WR61 0x2df4
641#define MGA_WR62 0x2df8
642#define MGA_WR63 0x2dfc
643# define MGA_G400_WR_MAGIC (1 << 6)
644# define MGA_G400_WR56_MAGIC 0x46480000
645
646#define MGA_ILOAD_ALIGN 64
647#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
648
649#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
650 MGA_ATYPE_I | \
651 MGA_ZMODE_NOZCMP | \
652 MGA_ARZERO | \
653 MGA_SGNZERO | \
654 MGA_BOP_SRC | \
655 (15 << MGA_TRANS_SHIFT))
656
657#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
658 MGA_ZMODE_NOZCMP | \
659 MGA_SOLID | \
660 MGA_ARZERO | \
661 MGA_SGNZERO | \
662 MGA_SHIFTZERO | \
663 MGA_BOP_SRC | \
664 (0 << MGA_TRANS_SHIFT) | \
665 MGA_BLTMOD_BMONOLEF | \
666 MGA_TRANSC | \
667 MGA_CLIPDIS)
668
669#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
670 MGA_ATYPE_RPL | \
671 MGA_SGNZERO | \
672 MGA_SHIFTZERO | \
673 MGA_BOP_SRC | \
674 (0 << MGA_TRANS_SHIFT) | \
675 MGA_BLTMOD_BFCOL | \
676 MGA_CLIPDIS)
677
678
679
680static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
681{
682 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
683 return (status == MGA_ENDPRDMASTS);
684}
685
686#endif
687
