LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs <bskeggs@redhat.com>
  23 */
  24#include "gf100.h"
  25#include "gk104.h"
  26#include "ctxgf100.h"
  27
  28#include <subdev/timer.h>
  29
  30#include <nvif/class.h>
  31
  32/*******************************************************************************
  33 * PGRAPH register lists
  34 ******************************************************************************/
  35
  36const struct gf100_gr_init
  37gk110_gr_init_fe_0[] = {
  38        { 0x40415c,   1, 0x04, 0x00000000 },
  39        { 0x404170,   1, 0x04, 0x00000000 },
  40        { 0x4041b4,   1, 0x04, 0x00000000 },
  41        {}
  42};
  43
  44const struct gf100_gr_init
  45gk110_gr_init_ds_0[] = {
  46        { 0x405844,   1, 0x04, 0x00ffffff },
  47        { 0x405850,   1, 0x04, 0x00000000 },
  48        { 0x405900,   1, 0x04, 0x0000ff00 },
  49        { 0x405908,   1, 0x04, 0x00000000 },
  50        { 0x405928,   2, 0x04, 0x00000000 },
  51        {}
  52};
  53
  54const struct gf100_gr_init
  55gk110_gr_init_sked_0[] = {
  56        { 0x407010,   1, 0x04, 0x00000000 },
  57        { 0x407040,   1, 0x04, 0x80440424 },
  58        { 0x407048,   1, 0x04, 0x0000000a },
  59        {}
  60};
  61
  62const struct gf100_gr_init
  63gk110_gr_init_cwd_0[] = {
  64        { 0x405b44,   1, 0x04, 0x00000000 },
  65        { 0x405b50,   1, 0x04, 0x00000000 },
  66        {}
  67};
  68
  69const struct gf100_gr_init
  70gk110_gr_init_gpc_unk_1[] = {
  71        { 0x418d00,   1, 0x04, 0x00000000 },
  72        { 0x418d28,   2, 0x04, 0x00000000 },
  73        { 0x418f00,   1, 0x04, 0x00000400 },
  74        { 0x418f08,   1, 0x04, 0x00000000 },
  75        { 0x418f20,   2, 0x04, 0x00000000 },
  76        { 0x418e00,   1, 0x04, 0x00000000 },
  77        { 0x418e08,   1, 0x04, 0x00000000 },
  78        { 0x418e1c,   2, 0x04, 0x00000000 },
  79        {}
  80};
  81
  82const struct gf100_gr_init
  83gk110_gr_init_tex_0[] = {
  84        { 0x419ab0,   1, 0x04, 0x00000000 },
  85        { 0x419ac8,   1, 0x04, 0x00000000 },
  86        { 0x419ab8,   1, 0x04, 0x000000e7 },
  87        { 0x419aec,   1, 0x04, 0x00000000 },
  88        { 0x419abc,   2, 0x04, 0x00000000 },
  89        { 0x419ab4,   1, 0x04, 0x00000000 },
  90        { 0x419aa8,   2, 0x04, 0x00000000 },
  91        {}
  92};
  93
  94static const struct gf100_gr_init
  95gk110_gr_init_l1c_0[] = {
  96        { 0x419c98,   1, 0x04, 0x00000000 },
  97        { 0x419ca8,   1, 0x04, 0x00000000 },
  98        { 0x419cb0,   1, 0x04, 0x01000000 },
  99        { 0x419cb4,   1, 0x04, 0x00000000 },
 100        { 0x419cb8,   1, 0x04, 0x00b08bea },
 101        { 0x419c84,   1, 0x04, 0x00010384 },
 102        { 0x419cbc,   1, 0x04, 0x281b3646 },
 103        { 0x419cc0,   2, 0x04, 0x00000000 },
 104        { 0x419c80,   1, 0x04, 0x00020230 },
 105        { 0x419ccc,   2, 0x04, 0x00000000 },
 106        {}
 107};
 108
 109const struct gf100_gr_init
 110gk110_gr_init_sm_0[] = {
 111        { 0x419e00,   1, 0x04, 0x00000080 },
 112        { 0x419ea0,   1, 0x04, 0x00000000 },
 113        { 0x419ee4,   1, 0x04, 0x00000000 },
 114        { 0x419ea4,   1, 0x04, 0x00000100 },
 115        { 0x419ea8,   1, 0x04, 0x00000000 },
 116        { 0x419eb4,   1, 0x04, 0x00000000 },
 117        { 0x419ebc,   2, 0x04, 0x00000000 },
 118        { 0x419edc,   1, 0x04, 0x00000000 },
 119        { 0x419f00,   1, 0x04, 0x00000000 },
 120        { 0x419ed0,   1, 0x04, 0x00003234 },
 121        { 0x419f74,   1, 0x04, 0x00015555 },
 122        { 0x419f80,   4, 0x04, 0x00000000 },
 123        {}
 124};
 125
 126static const struct gf100_gr_pack
 127gk110_gr_pack_mmio[] = {
 128        { gk104_gr_init_main_0 },
 129        { gk110_gr_init_fe_0 },
 130        { gf100_gr_init_pri_0 },
 131        { gf100_gr_init_rstr2d_0 },
 132        { gf119_gr_init_pd_0 },
 133        { gk110_gr_init_ds_0 },
 134        { gf100_gr_init_scc_0 },
 135        { gk110_gr_init_sked_0 },
 136        { gk110_gr_init_cwd_0 },
 137        { gf119_gr_init_prop_0 },
 138        { gf108_gr_init_gpc_unk_0 },
 139        { gf100_gr_init_setup_0 },
 140        { gf100_gr_init_crstr_0 },
 141        { gf108_gr_init_setup_1 },
 142        { gf100_gr_init_zcull_0 },
 143        { gf119_gr_init_gpm_0 },
 144        { gk110_gr_init_gpc_unk_1 },
 145        { gf100_gr_init_gcc_0 },
 146        { gk104_gr_init_gpc_unk_2 },
 147        { gk104_gr_init_tpccs_0 },
 148        { gk110_gr_init_tex_0 },
 149        { gk104_gr_init_pe_0 },
 150        { gk110_gr_init_l1c_0 },
 151        { gf100_gr_init_mpc_0 },
 152        { gk110_gr_init_sm_0 },
 153        { gf117_gr_init_pes_0 },
 154        { gf117_gr_init_wwdx_0 },
 155        { gf117_gr_init_cbm_0 },
 156        { gk104_gr_init_be_0 },
 157        { gf100_gr_init_fe_1 },
 158        {}
 159};
 160
 161static const struct nvkm_therm_clkgate_init
 162gk110_clkgate_blcg_init_sked_0[] = {
 163        { 0x407000, 1, 0x00004041 },
 164        {}
 165};
 166
 167static const struct nvkm_therm_clkgate_init
 168gk110_clkgate_blcg_init_gpc_gcc_0[] = {
 169        { 0x419020, 1, 0x00000042 },
 170        { 0x419038, 1, 0x00000042 },
 171        {}
 172};
 173
 174static const struct nvkm_therm_clkgate_init
 175gk110_clkgate_blcg_init_gpc_l1c_0[] = {
 176        { 0x419cd4, 2, 0x00004042 },
 177        {}
 178};
 179
 180static const struct nvkm_therm_clkgate_init
 181gk110_clkgate_blcg_init_gpc_mp_0[] = {
 182        { 0x419fd0, 1, 0x00004043 },
 183        { 0x419fd8, 1, 0x00004049 },
 184        { 0x419fe0, 2, 0x00004042 },
 185        { 0x419ff0, 1, 0x00000046 },
 186        { 0x419ff8, 1, 0x00004042 },
 187        { 0x419f90, 1, 0x00004042 },
 188        {}
 189};
 190
 191static const struct nvkm_therm_clkgate_init
 192gk110_clkgate_slcg_init_main_0[] = {
 193        { 0x4041f4, 1, 0x00000000 },
 194        { 0x409894, 1, 0x00000000 },
 195        {}
 196};
 197
 198static const struct nvkm_therm_clkgate_init
 199gk110_clkgate_slcg_init_unk_0[] = {
 200        { 0x406004, 1, 0x00000000 },
 201        {}
 202};
 203
 204static const struct nvkm_therm_clkgate_init
 205gk110_clkgate_slcg_init_sked_0[] = {
 206        { 0x407004, 1, 0x00000000 },
 207        {}
 208};
 209
 210static const struct nvkm_therm_clkgate_init
 211gk110_clkgate_slcg_init_gpc_ctxctl_0[] = {
 212        { 0x41a894, 1, 0x00000000 },
 213        {}
 214};
 215
 216static const struct nvkm_therm_clkgate_init
 217gk110_clkgate_slcg_init_gpc_unk_0[] = {
 218        { 0x418504, 1, 0x00000000 },
 219        { 0x41860c, 1, 0x00000000 },
 220        { 0x41868c, 1, 0x00000000 },
 221        {}
 222};
 223
 224static const struct nvkm_therm_clkgate_init
 225gk110_clkgate_slcg_init_gpc_esetup_0[] = {
 226        { 0x41882c, 1, 0x00000000 },
 227        {}
 228};
 229
 230static const struct nvkm_therm_clkgate_init
 231gk110_clkgate_slcg_init_gpc_zcull_0[] = {
 232        { 0x418974, 1, 0x00000000 },
 233        {}
 234};
 235
 236static const struct nvkm_therm_clkgate_init
 237gk110_clkgate_slcg_init_gpc_l1c_0[] = {
 238        { 0x419cd8, 2, 0x00000000 },
 239        {}
 240};
 241
 242static const struct nvkm_therm_clkgate_init
 243gk110_clkgate_slcg_init_gpc_unk_1[] = {
 244        { 0x419c74, 1, 0x00000000 },
 245        {}
 246};
 247
 248static const struct nvkm_therm_clkgate_init
 249gk110_clkgate_slcg_init_gpc_mp_0[] = {
 250        { 0x419fd4, 1, 0x00004a4a },
 251        { 0x419fdc, 1, 0x00000014 },
 252        { 0x419fe4, 1, 0x00000000 },
 253        { 0x419ff4, 1, 0x00001724 },
 254        {}
 255};
 256
 257static const struct nvkm_therm_clkgate_init
 258gk110_clkgate_slcg_init_gpc_ppc_0[] = {
 259        { 0x41be2c, 1, 0x00000000 },
 260        {}
 261};
 262
 263static const struct nvkm_therm_clkgate_init
 264gk110_clkgate_slcg_init_pcounter_0[] = {
 265        { 0x1be018, 1, 0x000001ff },
 266        { 0x1bc018, 1, 0x000001ff },
 267        { 0x1b8018, 1, 0x000001ff },
 268        { 0x1b4124, 1, 0x00000000 },
 269        {}
 270};
 271
 272static const struct nvkm_therm_clkgate_pack
 273gk110_clkgate_pack[] = {
 274        { gk104_clkgate_blcg_init_main_0 },
 275        { gk104_clkgate_blcg_init_rstr2d_0 },
 276        { gk104_clkgate_blcg_init_unk_0 },
 277        { gk104_clkgate_blcg_init_gcc_0 },
 278        { gk110_clkgate_blcg_init_sked_0 },
 279        { gk104_clkgate_blcg_init_unk_1 },
 280        { gk104_clkgate_blcg_init_gpc_ctxctl_0 },
 281        { gk104_clkgate_blcg_init_gpc_unk_0 },
 282        { gk104_clkgate_blcg_init_gpc_esetup_0 },
 283        { gk104_clkgate_blcg_init_gpc_tpbus_0 },
 284        { gk104_clkgate_blcg_init_gpc_zcull_0 },
 285        { gk104_clkgate_blcg_init_gpc_tpconf_0 },
 286        { gk104_clkgate_blcg_init_gpc_unk_1 },
 287        { gk110_clkgate_blcg_init_gpc_gcc_0 },
 288        { gk104_clkgate_blcg_init_gpc_ffb_0 },
 289        { gk104_clkgate_blcg_init_gpc_tex_0 },
 290        { gk104_clkgate_blcg_init_gpc_poly_0 },
 291        { gk110_clkgate_blcg_init_gpc_l1c_0 },
 292        { gk104_clkgate_blcg_init_gpc_unk_2 },
 293        { gk110_clkgate_blcg_init_gpc_mp_0 },
 294        { gk104_clkgate_blcg_init_gpc_ppc_0 },
 295        { gk104_clkgate_blcg_init_rop_zrop_0 },
 296        { gk104_clkgate_blcg_init_rop_0 },
 297        { gk104_clkgate_blcg_init_rop_crop_0 },
 298        { gk104_clkgate_blcg_init_pxbar_0 },
 299        { gk110_clkgate_slcg_init_main_0 },
 300        { gk110_clkgate_slcg_init_unk_0 },
 301        { gk110_clkgate_slcg_init_sked_0 },
 302        { gk110_clkgate_slcg_init_gpc_ctxctl_0 },
 303        { gk110_clkgate_slcg_init_gpc_unk_0 },
 304        { gk110_clkgate_slcg_init_gpc_esetup_0 },
 305        { gk110_clkgate_slcg_init_gpc_zcull_0 },
 306        { gk110_clkgate_slcg_init_gpc_l1c_0 },
 307        { gk110_clkgate_slcg_init_gpc_unk_1 },
 308        { gk110_clkgate_slcg_init_gpc_mp_0 },
 309        { gk110_clkgate_slcg_init_gpc_ppc_0 },
 310        { gk110_clkgate_slcg_init_pcounter_0 },
 311        {}
 312};
 313
 314/*******************************************************************************
 315 * PGRAPH engine/subdev functions
 316 ******************************************************************************/
 317
 318#include "fuc/hubgk110.fuc3.h"
 319
 320struct gf100_gr_ucode
 321gk110_gr_fecs_ucode = {
 322        .code.data = gk110_grhub_code,
 323        .code.size = sizeof(gk110_grhub_code),
 324        .data.data = gk110_grhub_data,
 325        .data.size = sizeof(gk110_grhub_data),
 326};
 327
 328#include "fuc/gpcgk110.fuc3.h"
 329
 330struct gf100_gr_ucode
 331gk110_gr_gpccs_ucode = {
 332        .code.data = gk110_grgpc_code,
 333        .code.size = sizeof(gk110_grgpc_code),
 334        .data.data = gk110_grgpc_data,
 335        .data.size = sizeof(gk110_grgpc_data),
 336};
 337
 338void
 339gk110_gr_init_419eb4(struct gf100_gr *gr)
 340{
 341        struct nvkm_device *device = gr->base.engine.subdev.device;
 342        nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
 343        nvkm_mask(device, 0x419eb4, 0x00002000, 0x00002000);
 344        nvkm_mask(device, 0x419eb4, 0x00004000, 0x00004000);
 345        nvkm_mask(device, 0x419eb4, 0x00008000, 0x00008000);
 346        nvkm_mask(device, 0x419eb4, 0x00001000, 0x00000000);
 347        nvkm_mask(device, 0x419eb4, 0x00002000, 0x00000000);
 348        nvkm_mask(device, 0x419eb4, 0x00004000, 0x00000000);
 349        nvkm_mask(device, 0x419eb4, 0x00008000, 0x00000000);
 350}
 351
 352static const struct gf100_gr_func
 353gk110_gr = {
 354        .oneinit_tiles = gf100_gr_oneinit_tiles,
 355        .oneinit_sm_id = gf100_gr_oneinit_sm_id,
 356        .init = gf100_gr_init,
 357        .init_gpc_mmu = gf100_gr_init_gpc_mmu,
 358        .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
 359        .init_zcull = gf117_gr_init_zcull,
 360        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
 361        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
 362        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
 363        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
 364        .init_419cc0 = gf100_gr_init_419cc0,
 365        .init_419eb4 = gk110_gr_init_419eb4,
 366        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
 367        .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
 368        .init_shader_exceptions = gf100_gr_init_shader_exceptions,
 369        .init_400054 = gf100_gr_init_400054,
 370        .trap_mp = gf100_gr_trap_mp,
 371        .mmio = gk110_gr_pack_mmio,
 372        .fecs.ucode = &gk110_gr_fecs_ucode,
 373        .gpccs.ucode = &gk110_gr_gpccs_ucode,
 374        .rops = gf100_gr_rops,
 375        .ppc_nr = 2,
 376        .grctx = &gk110_grctx,
 377        .clkgate_pack = gk110_clkgate_pack,
 378        .zbc = &gf100_gr_zbc,
 379        .sclass = {
 380                { -1, -1, FERMI_TWOD_A },
 381                { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 382                { -1, -1, KEPLER_B, &gf100_fermi },
 383                { -1, -1, KEPLER_COMPUTE_B },
 384                {}
 385        }
 386};
 387
 388static const struct gf100_gr_fwif
 389gk110_gr_fwif[] = {
 390        { -1, gf100_gr_load, &gk110_gr },
 391        { -1, gf100_gr_nofw, &gk110_gr },
 392        {}
 393};
 394
 395int
 396gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
 397{
 398        return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr);
 399}
 400