linux/drivers/hwmon/aspeed-pwm-tacho.c
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   1/*
   2 * Copyright (c) 2016 Google, Inc
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 or later as
   6 * published by the Free Software Foundation.
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/delay.h>
  11#include <linux/errno.h>
  12#include <linux/gpio/consumer.h>
  13#include <linux/hwmon.h>
  14#include <linux/hwmon-sysfs.h>
  15#include <linux/io.h>
  16#include <linux/kernel.h>
  17#include <linux/module.h>
  18#include <linux/of_device.h>
  19#include <linux/of_platform.h>
  20#include <linux/platform_device.h>
  21#include <linux/regmap.h>
  22#include <linux/reset.h>
  23#include <linux/sysfs.h>
  24#include <linux/thermal.h>
  25
  26/* ASPEED PWM & FAN Tach Register Definition */
  27#define ASPEED_PTCR_CTRL                0x00
  28#define ASPEED_PTCR_CLK_CTRL            0x04
  29#define ASPEED_PTCR_DUTY0_CTRL          0x08
  30#define ASPEED_PTCR_DUTY1_CTRL          0x0c
  31#define ASPEED_PTCR_TYPEM_CTRL          0x10
  32#define ASPEED_PTCR_TYPEM_CTRL1         0x14
  33#define ASPEED_PTCR_TYPEN_CTRL          0x18
  34#define ASPEED_PTCR_TYPEN_CTRL1         0x1c
  35#define ASPEED_PTCR_TACH_SOURCE         0x20
  36#define ASPEED_PTCR_TRIGGER             0x28
  37#define ASPEED_PTCR_RESULT              0x2c
  38#define ASPEED_PTCR_INTR_CTRL           0x30
  39#define ASPEED_PTCR_INTR_STS            0x34
  40#define ASPEED_PTCR_TYPEM_LIMIT         0x38
  41#define ASPEED_PTCR_TYPEN_LIMIT         0x3C
  42#define ASPEED_PTCR_CTRL_EXT            0x40
  43#define ASPEED_PTCR_CLK_CTRL_EXT        0x44
  44#define ASPEED_PTCR_DUTY2_CTRL          0x48
  45#define ASPEED_PTCR_DUTY3_CTRL          0x4c
  46#define ASPEED_PTCR_TYPEO_CTRL          0x50
  47#define ASPEED_PTCR_TYPEO_CTRL1         0x54
  48#define ASPEED_PTCR_TACH_SOURCE_EXT     0x60
  49#define ASPEED_PTCR_TYPEO_LIMIT         0x78
  50
  51/* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
  52#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1    15
  53#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2    6
  54#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK     (BIT(7) | BIT(15))
  55
  56#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1    14
  57#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2    5
  58#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK     (BIT(6) | BIT(14))
  59
  60#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1    13
  61#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2    4
  62#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK     (BIT(5) | BIT(13))
  63
  64#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1    12
  65#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2    3
  66#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK     (BIT(4) | BIT(12))
  67
  68#define ASPEED_PTCR_CTRL_FAN_NUM_EN(x)  BIT(16 + (x))
  69
  70#define ASPEED_PTCR_CTRL_PWMD_EN        BIT(11)
  71#define ASPEED_PTCR_CTRL_PWMC_EN        BIT(10)
  72#define ASPEED_PTCR_CTRL_PWMB_EN        BIT(9)
  73#define ASPEED_PTCR_CTRL_PWMA_EN        BIT(8)
  74
  75#define ASPEED_PTCR_CTRL_CLK_SRC        BIT(1)
  76#define ASPEED_PTCR_CTRL_CLK_EN         BIT(0)
  77
  78/* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
  79/* TYPE N */
  80#define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK         GENMASK(31, 16)
  81#define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT         24
  82#define ASPEED_PTCR_CLK_CTRL_TYPEN_H            20
  83#define ASPEED_PTCR_CLK_CTRL_TYPEN_L            16
  84/* TYPE M */
  85#define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
  86#define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT         8
  87#define ASPEED_PTCR_CLK_CTRL_TYPEM_H            4
  88#define ASPEED_PTCR_CLK_CTRL_TYPEM_L            0
  89
  90/*
  91 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
  92 * 0/1/2/3 register
  93 */
  94#define DUTY_CTRL_PWM2_FALL_POINT       24
  95#define DUTY_CTRL_PWM2_RISE_POINT       16
  96#define DUTY_CTRL_PWM2_RISE_FALL_MASK   GENMASK(31, 16)
  97#define DUTY_CTRL_PWM1_FALL_POINT       8
  98#define DUTY_CTRL_PWM1_RISE_POINT       0
  99#define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
 100
 101/* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
 102#define TYPE_CTRL_FAN_MASK              (GENMASK(5, 1) | GENMASK(31, 16))
 103#define TYPE_CTRL_FAN1_MASK             GENMASK(31, 0)
 104#define TYPE_CTRL_FAN_PERIOD            16
 105#define TYPE_CTRL_FAN_MODE              4
 106#define TYPE_CTRL_FAN_DIVISION          1
 107#define TYPE_CTRL_FAN_TYPE_EN           1
 108
 109/* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
 110/* bit [0,1] at 0x20, bit [2] at 0x60 */
 111#define TACH_PWM_SOURCE_BIT01(x)        ((x) * 2)
 112#define TACH_PWM_SOURCE_BIT2(x)         ((x) * 2)
 113#define TACH_PWM_SOURCE_MASK_BIT01(x)   (0x3 << ((x) * 2))
 114#define TACH_PWM_SOURCE_MASK_BIT2(x)    BIT((x) * 2)
 115
 116/* ASPEED_PTCR_RESULT : 0x2c - Result Register */
 117#define RESULT_STATUS_MASK              BIT(31)
 118#define RESULT_VALUE_MASK               0xfffff
 119
 120/* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
 121#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1    15
 122#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2    6
 123#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK     (BIT(7) | BIT(15))
 124
 125#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1    14
 126#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2    5
 127#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK     (BIT(6) | BIT(14))
 128
 129#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1    13
 130#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2    4
 131#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK     (BIT(5) | BIT(13))
 132
 133#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1    12
 134#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2    3
 135#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK     (BIT(4) | BIT(12))
 136
 137#define ASPEED_PTCR_CTRL_PWMH_EN        BIT(11)
 138#define ASPEED_PTCR_CTRL_PWMG_EN        BIT(10)
 139#define ASPEED_PTCR_CTRL_PWMF_EN        BIT(9)
 140#define ASPEED_PTCR_CTRL_PWME_EN        BIT(8)
 141
 142/* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
 143/* TYPE O */
 144#define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
 145#define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT         8
 146#define ASPEED_PTCR_CLK_CTRL_TYPEO_H            4
 147#define ASPEED_PTCR_CLK_CTRL_TYPEO_L            0
 148
 149#define PWM_MAX 255
 150
 151#define BOTH_EDGES 0x02 /* 10b */
 152
 153#define M_PWM_DIV_H 0x00
 154#define M_PWM_DIV_L 0x05
 155#define M_PWM_PERIOD 0x5F
 156#define M_TACH_CLK_DIV 0x00
 157/*
 158 * 5:4 Type N fan tach mode selection bit:
 159 * 00: falling
 160 * 01: rising
 161 * 10: both
 162 * 11: reserved.
 163 */
 164#define M_TACH_MODE 0x02 /* 10b */
 165#define M_TACH_UNIT 0x0210
 166#define INIT_FAN_CTRL 0xFF
 167
 168/* How long we sleep in us while waiting for an RPM result. */
 169#define ASPEED_RPM_STATUS_SLEEP_USEC    500
 170
 171#define MAX_CDEV_NAME_LEN 16
 172
 173struct aspeed_cooling_device {
 174        char name[16];
 175        struct aspeed_pwm_tacho_data *priv;
 176        struct thermal_cooling_device *tcdev;
 177        int pwm_port;
 178        u8 *cooling_levels;
 179        u8 max_state;
 180        u8 cur_state;
 181};
 182
 183struct aspeed_pwm_tacho_data {
 184        struct regmap *regmap;
 185        struct reset_control *rst;
 186        unsigned long clk_freq;
 187        bool pwm_present[8];
 188        bool fan_tach_present[16];
 189        u8 type_pwm_clock_unit[3];
 190        u8 type_pwm_clock_division_h[3];
 191        u8 type_pwm_clock_division_l[3];
 192        u8 type_fan_tach_clock_division[3];
 193        u8 type_fan_tach_mode[3];
 194        u16 type_fan_tach_unit[3];
 195        u8 pwm_port_type[8];
 196        u8 pwm_port_fan_ctrl[8];
 197        u8 fan_tach_ch_source[16];
 198        struct aspeed_cooling_device *cdev[8];
 199        const struct attribute_group *groups[3];
 200};
 201
 202enum type { TYPEM, TYPEN, TYPEO };
 203
 204struct type_params {
 205        u32 l_value;
 206        u32 h_value;
 207        u32 unit_value;
 208        u32 clk_ctrl_mask;
 209        u32 clk_ctrl_reg;
 210        u32 ctrl_reg;
 211        u32 ctrl_reg1;
 212};
 213
 214static const struct type_params type_params[] = {
 215        [TYPEM] = {
 216                .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
 217                .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
 218                .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
 219                .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
 220                .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 221                .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
 222                .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
 223        },
 224        [TYPEN] = {
 225                .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
 226                .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
 227                .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
 228                .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
 229                .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
 230                .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
 231                .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
 232        },
 233        [TYPEO] = {
 234                .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
 235                .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
 236                .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
 237                .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
 238                .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
 239                .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
 240                .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
 241        }
 242};
 243
 244enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
 245
 246struct pwm_port_params {
 247        u32 pwm_en;
 248        u32 ctrl_reg;
 249        u32 type_part1;
 250        u32 type_part2;
 251        u32 type_mask;
 252        u32 duty_ctrl_rise_point;
 253        u32 duty_ctrl_fall_point;
 254        u32 duty_ctrl_reg;
 255        u32 duty_ctrl_rise_fall_mask;
 256};
 257
 258static const struct pwm_port_params pwm_port_params[] = {
 259        [PWMA] = {
 260                .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
 261                .ctrl_reg = ASPEED_PTCR_CTRL,
 262                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
 263                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
 264                .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
 265                .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 266                .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 267                .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 268                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 269        },
 270        [PWMB] = {
 271                .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
 272                .ctrl_reg = ASPEED_PTCR_CTRL,
 273                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
 274                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
 275                .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
 276                .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 277                .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 278                .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
 279                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 280        },
 281        [PWMC] = {
 282                .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
 283                .ctrl_reg = ASPEED_PTCR_CTRL,
 284                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
 285                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
 286                .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
 287                .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 288                .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 289                .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 290                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 291        },
 292        [PWMD] = {
 293                .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
 294                .ctrl_reg = ASPEED_PTCR_CTRL,
 295                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
 296                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
 297                .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
 298                .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 299                .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 300                .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
 301                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 302        },
 303        [PWME] = {
 304                .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
 305                .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 306                .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
 307                .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
 308                .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
 309                .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 310                .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 311                .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 312                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 313        },
 314        [PWMF] = {
 315                .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
 316                .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 317                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
 318                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
 319                .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
 320                .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 321                .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 322                .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
 323                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 324        },
 325        [PWMG] = {
 326                .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
 327                .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 328                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
 329                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
 330                .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
 331                .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
 332                .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
 333                .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 334                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
 335        },
 336        [PWMH] = {
 337                .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
 338                .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
 339                .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
 340                .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
 341                .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
 342                .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
 343                .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
 344                .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
 345                .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
 346        }
 347};
 348
 349static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
 350                                             unsigned int val)
 351{
 352        void __iomem *regs = (void __iomem *)context;
 353
 354        writel(val, regs + reg);
 355        return 0;
 356}
 357
 358static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
 359                                            unsigned int *val)
 360{
 361        void __iomem *regs = (void __iomem *)context;
 362
 363        *val = readl(regs + reg);
 364        return 0;
 365}
 366
 367static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
 368        .reg_bits = 32,
 369        .val_bits = 32,
 370        .reg_stride = 4,
 371        .max_register = ASPEED_PTCR_TYPEO_LIMIT,
 372        .reg_write = regmap_aspeed_pwm_tacho_reg_write,
 373        .reg_read = regmap_aspeed_pwm_tacho_reg_read,
 374        .fast_io = true,
 375};
 376
 377static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
 378{
 379        regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 380                           ASPEED_PTCR_CTRL_CLK_EN,
 381                           val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
 382}
 383
 384static void aspeed_set_clock_source(struct regmap *regmap, int val)
 385{
 386        regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 387                           ASPEED_PTCR_CTRL_CLK_SRC,
 388                           val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
 389}
 390
 391static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
 392                                        u8 div_high, u8 div_low, u8 unit)
 393{
 394        u32 reg_value = ((div_high << type_params[type].h_value) |
 395                         (div_low << type_params[type].l_value) |
 396                         (unit << type_params[type].unit_value));
 397
 398        regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
 399                           type_params[type].clk_ctrl_mask, reg_value);
 400}
 401
 402static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
 403                                       bool enable)
 404{
 405        regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 406                           pwm_port_params[pwm_port].pwm_en,
 407                           enable ? pwm_port_params[pwm_port].pwm_en : 0);
 408}
 409
 410static void aspeed_set_pwm_port_type(struct regmap *regmap,
 411                                     u8 pwm_port, u8 type)
 412{
 413        u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
 414
 415        reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
 416
 417        regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
 418                           pwm_port_params[pwm_port].type_mask, reg_value);
 419}
 420
 421static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
 422                                                    u8 pwm_port, u8 rising,
 423                                                    u8 falling)
 424{
 425        u32 reg_value = (rising <<
 426                         pwm_port_params[pwm_port].duty_ctrl_rise_point);
 427        reg_value |= (falling <<
 428                      pwm_port_params[pwm_port].duty_ctrl_fall_point);
 429
 430        regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
 431                           pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
 432                           reg_value);
 433}
 434
 435static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
 436                                         bool enable)
 437{
 438        regmap_update_bits(regmap, type_params[type].ctrl_reg,
 439                           TYPE_CTRL_FAN_TYPE_EN,
 440                           enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
 441}
 442
 443static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
 444                                         u8 mode, u16 unit, u8 division)
 445{
 446        u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
 447                         (unit << TYPE_CTRL_FAN_PERIOD) |
 448                         (division << TYPE_CTRL_FAN_DIVISION));
 449
 450        regmap_update_bits(regmap, type_params[type].ctrl_reg,
 451                           TYPE_CTRL_FAN_MASK, reg_value);
 452        regmap_update_bits(regmap, type_params[type].ctrl_reg1,
 453                           TYPE_CTRL_FAN1_MASK, unit << 16);
 454}
 455
 456static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
 457                                          bool enable)
 458{
 459        regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
 460                           ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
 461                           enable ?
 462                           ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
 463}
 464
 465static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
 466                                          u8 fan_tach_ch_source)
 467{
 468        u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
 469                          TACH_PWM_SOURCE_BIT01(fan_tach_ch));
 470        u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
 471                          TACH_PWM_SOURCE_BIT2(fan_tach_ch));
 472
 473        regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
 474                           TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
 475                           reg_value1);
 476
 477        regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
 478                           TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
 479                           reg_value2);
 480}
 481
 482static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
 483                                         u8 index, u8 fan_ctrl)
 484{
 485        u16 period, dc_time_on;
 486
 487        period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
 488        period += 1;
 489        dc_time_on = (fan_ctrl * period) / PWM_MAX;
 490
 491        if (dc_time_on == 0) {
 492                aspeed_set_pwm_port_enable(priv->regmap, index, false);
 493        } else {
 494                if (dc_time_on == period)
 495                        dc_time_on = 0;
 496
 497                aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
 498                                                        dc_time_on);
 499                aspeed_set_pwm_port_enable(priv->regmap, index, true);
 500        }
 501}
 502
 503static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
 504                                                 *priv, u8 type)
 505{
 506        u32 clk;
 507        u16 tacho_unit;
 508        u8 clk_unit, div_h, div_l, tacho_div;
 509
 510        clk = priv->clk_freq;
 511        clk_unit = priv->type_pwm_clock_unit[type];
 512        div_h = priv->type_pwm_clock_division_h[type];
 513        div_h = 0x1 << div_h;
 514        div_l = priv->type_pwm_clock_division_l[type];
 515        if (div_l == 0)
 516                div_l = 1;
 517        else
 518                div_l = div_l * 2;
 519
 520        tacho_unit = priv->type_fan_tach_unit[type];
 521        tacho_div = priv->type_fan_tach_clock_division[type];
 522
 523        tacho_div = 0x4 << (tacho_div * 2);
 524        return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
 525}
 526
 527static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
 528                                      u8 fan_tach_ch)
 529{
 530        u32 raw_data, tach_div, clk_source, msec, usec, val;
 531        u8 fan_tach_ch_source, type, mode, both;
 532        int ret;
 533
 534        regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
 535        regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
 536
 537        fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
 538        type = priv->pwm_port_type[fan_tach_ch_source];
 539
 540        msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
 541        usec = msec * 1000;
 542
 543        ret = regmap_read_poll_timeout(
 544                priv->regmap,
 545                ASPEED_PTCR_RESULT,
 546                val,
 547                (val & RESULT_STATUS_MASK),
 548                ASPEED_RPM_STATUS_SLEEP_USEC,
 549                usec);
 550
 551        /* return -ETIMEDOUT if we didn't get an answer. */
 552        if (ret)
 553                return ret;
 554
 555        raw_data = val & RESULT_VALUE_MASK;
 556        tach_div = priv->type_fan_tach_clock_division[type];
 557        /*
 558         * We need the mode to determine if the raw_data is double (from
 559         * counting both edges).
 560         */
 561        mode = priv->type_fan_tach_mode[type];
 562        both = (mode & BOTH_EDGES) ? 1 : 0;
 563
 564        tach_div = (0x4 << both) << (tach_div * 2);
 565        clk_source = priv->clk_freq;
 566
 567        if (raw_data == 0)
 568                return 0;
 569
 570        return (clk_source * 60) / (2 * raw_data * tach_div);
 571}
 572
 573static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
 574                       const char *buf, size_t count)
 575{
 576        struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 577        int index = sensor_attr->index;
 578        int ret;
 579        struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 580        long fan_ctrl;
 581
 582        ret = kstrtol(buf, 10, &fan_ctrl);
 583        if (ret != 0)
 584                return ret;
 585
 586        if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
 587                return -EINVAL;
 588
 589        if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
 590                return count;
 591
 592        priv->pwm_port_fan_ctrl[index] = fan_ctrl;
 593        aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
 594
 595        return count;
 596}
 597
 598static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
 599                        char *buf)
 600{
 601        struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 602        int index = sensor_attr->index;
 603        struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 604
 605        return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
 606}
 607
 608static ssize_t show_rpm(struct device *dev, struct device_attribute *attr,
 609                        char *buf)
 610{
 611        struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
 612        int index = sensor_attr->index;
 613        int rpm;
 614        struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 615
 616        rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
 617        if (rpm < 0)
 618                return rpm;
 619
 620        return sprintf(buf, "%d\n", rpm);
 621}
 622
 623static umode_t pwm_is_visible(struct kobject *kobj,
 624                              struct attribute *a, int index)
 625{
 626        struct device *dev = container_of(kobj, struct device, kobj);
 627        struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 628
 629        if (!priv->pwm_present[index])
 630                return 0;
 631        return a->mode;
 632}
 633
 634static umode_t fan_dev_is_visible(struct kobject *kobj,
 635                                  struct attribute *a, int index)
 636{
 637        struct device *dev = container_of(kobj, struct device, kobj);
 638        struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
 639
 640        if (!priv->fan_tach_present[index])
 641                return 0;
 642        return a->mode;
 643}
 644
 645static SENSOR_DEVICE_ATTR(pwm1, 0644,
 646                        show_pwm, set_pwm, 0);
 647static SENSOR_DEVICE_ATTR(pwm2, 0644,
 648                        show_pwm, set_pwm, 1);
 649static SENSOR_DEVICE_ATTR(pwm3, 0644,
 650                        show_pwm, set_pwm, 2);
 651static SENSOR_DEVICE_ATTR(pwm4, 0644,
 652                        show_pwm, set_pwm, 3);
 653static SENSOR_DEVICE_ATTR(pwm5, 0644,
 654                        show_pwm, set_pwm, 4);
 655static SENSOR_DEVICE_ATTR(pwm6, 0644,
 656                        show_pwm, set_pwm, 5);
 657static SENSOR_DEVICE_ATTR(pwm7, 0644,
 658                        show_pwm, set_pwm, 6);
 659static SENSOR_DEVICE_ATTR(pwm8, 0644,
 660                        show_pwm, set_pwm, 7);
 661static struct attribute *pwm_dev_attrs[] = {
 662        &sensor_dev_attr_pwm1.dev_attr.attr,
 663        &sensor_dev_attr_pwm2.dev_attr.attr,
 664        &sensor_dev_attr_pwm3.dev_attr.attr,
 665        &sensor_dev_attr_pwm4.dev_attr.attr,
 666        &sensor_dev_attr_pwm5.dev_attr.attr,
 667        &sensor_dev_attr_pwm6.dev_attr.attr,
 668        &sensor_dev_attr_pwm7.dev_attr.attr,
 669        &sensor_dev_attr_pwm8.dev_attr.attr,
 670        NULL,
 671};
 672
 673static const struct attribute_group pwm_dev_group = {
 674        .attrs = pwm_dev_attrs,
 675        .is_visible = pwm_is_visible,
 676};
 677
 678static SENSOR_DEVICE_ATTR(fan1_input, 0444,
 679                show_rpm, NULL, 0);
 680static SENSOR_DEVICE_ATTR(fan2_input, 0444,
 681                show_rpm, NULL, 1);
 682static SENSOR_DEVICE_ATTR(fan3_input, 0444,
 683                show_rpm, NULL, 2);
 684static SENSOR_DEVICE_ATTR(fan4_input, 0444,
 685                show_rpm, NULL, 3);
 686static SENSOR_DEVICE_ATTR(fan5_input, 0444,
 687                show_rpm, NULL, 4);
 688static SENSOR_DEVICE_ATTR(fan6_input, 0444,
 689                show_rpm, NULL, 5);
 690static SENSOR_DEVICE_ATTR(fan7_input, 0444,
 691                show_rpm, NULL, 6);
 692static SENSOR_DEVICE_ATTR(fan8_input, 0444,
 693                show_rpm, NULL, 7);
 694static SENSOR_DEVICE_ATTR(fan9_input, 0444,
 695                show_rpm, NULL, 8);
 696static SENSOR_DEVICE_ATTR(fan10_input, 0444,
 697                show_rpm, NULL, 9);
 698static SENSOR_DEVICE_ATTR(fan11_input, 0444,
 699                show_rpm, NULL, 10);
 700static SENSOR_DEVICE_ATTR(fan12_input, 0444,
 701                show_rpm, NULL, 11);
 702static SENSOR_DEVICE_ATTR(fan13_input, 0444,
 703                show_rpm, NULL, 12);
 704static SENSOR_DEVICE_ATTR(fan14_input, 0444,
 705                show_rpm, NULL, 13);
 706static SENSOR_DEVICE_ATTR(fan15_input, 0444,
 707                show_rpm, NULL, 14);
 708static SENSOR_DEVICE_ATTR(fan16_input, 0444,
 709                show_rpm, NULL, 15);
 710static struct attribute *fan_dev_attrs[] = {
 711        &sensor_dev_attr_fan1_input.dev_attr.attr,
 712        &sensor_dev_attr_fan2_input.dev_attr.attr,
 713        &sensor_dev_attr_fan3_input.dev_attr.attr,
 714        &sensor_dev_attr_fan4_input.dev_attr.attr,
 715        &sensor_dev_attr_fan5_input.dev_attr.attr,
 716        &sensor_dev_attr_fan6_input.dev_attr.attr,
 717        &sensor_dev_attr_fan7_input.dev_attr.attr,
 718        &sensor_dev_attr_fan8_input.dev_attr.attr,
 719        &sensor_dev_attr_fan9_input.dev_attr.attr,
 720        &sensor_dev_attr_fan10_input.dev_attr.attr,
 721        &sensor_dev_attr_fan11_input.dev_attr.attr,
 722        &sensor_dev_attr_fan12_input.dev_attr.attr,
 723        &sensor_dev_attr_fan13_input.dev_attr.attr,
 724        &sensor_dev_attr_fan14_input.dev_attr.attr,
 725        &sensor_dev_attr_fan15_input.dev_attr.attr,
 726        &sensor_dev_attr_fan16_input.dev_attr.attr,
 727        NULL
 728};
 729
 730static const struct attribute_group fan_dev_group = {
 731        .attrs = fan_dev_attrs,
 732        .is_visible = fan_dev_is_visible,
 733};
 734
 735/*
 736 * The clock type is type M :
 737 * The PWM frequency = 24MHz / (type M clock division L bit *
 738 * type M clock division H bit * (type M PWM period bit + 1))
 739 */
 740static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
 741{
 742        priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
 743        priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
 744        priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
 745        aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
 746                                    M_PWM_DIV_L, M_PWM_PERIOD);
 747        aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
 748        priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
 749        priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
 750        priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
 751        aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
 752                                     M_TACH_UNIT, M_TACH_CLK_DIV);
 753}
 754
 755static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
 756                                   u8 pwm_port)
 757{
 758        aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
 759        priv->pwm_present[pwm_port] = true;
 760
 761        priv->pwm_port_type[pwm_port] = TYPEM;
 762        aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
 763
 764        priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
 765        aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
 766}
 767
 768static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
 769                                           u8 *fan_tach_ch,
 770                                           int count,
 771                                           u8 pwm_source)
 772{
 773        u8 val, index;
 774
 775        for (val = 0; val < count; val++) {
 776                index = fan_tach_ch[val];
 777                aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
 778                priv->fan_tach_present[index] = true;
 779                priv->fan_tach_ch_source[index] = pwm_source;
 780                aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
 781        }
 782}
 783
 784static int
 785aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
 786                            unsigned long *state)
 787{
 788        struct aspeed_cooling_device *cdev = tcdev->devdata;
 789
 790        *state = cdev->max_state;
 791
 792        return 0;
 793}
 794
 795static int
 796aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
 797                            unsigned long *state)
 798{
 799        struct aspeed_cooling_device *cdev = tcdev->devdata;
 800
 801        *state = cdev->cur_state;
 802
 803        return 0;
 804}
 805
 806static int
 807aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
 808                            unsigned long state)
 809{
 810        struct aspeed_cooling_device *cdev = tcdev->devdata;
 811
 812        if (state > cdev->max_state)
 813                return -EINVAL;
 814
 815        cdev->cur_state = state;
 816        cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
 817                                        cdev->cooling_levels[cdev->cur_state];
 818        aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
 819                                     cdev->cooling_levels[cdev->cur_state]);
 820
 821        return 0;
 822}
 823
 824static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
 825        .get_max_state = aspeed_pwm_cz_get_max_state,
 826        .get_cur_state = aspeed_pwm_cz_get_cur_state,
 827        .set_cur_state = aspeed_pwm_cz_set_cur_state,
 828};
 829
 830static int aspeed_create_pwm_cooling(struct device *dev,
 831                                     struct device_node *child,
 832                                     struct aspeed_pwm_tacho_data *priv,
 833                                     u32 pwm_port, u8 num_levels)
 834{
 835        int ret;
 836        struct aspeed_cooling_device *cdev;
 837
 838        cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
 839
 840        if (!cdev)
 841                return -ENOMEM;
 842
 843        cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
 844        if (!cdev->cooling_levels)
 845                return -ENOMEM;
 846
 847        cdev->max_state = num_levels - 1;
 848        ret = of_property_read_u8_array(child, "cooling-levels",
 849                                        cdev->cooling_levels,
 850                                        num_levels);
 851        if (ret) {
 852                dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
 853                return ret;
 854        }
 855        snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%s%d", child->name, pwm_port);
 856
 857        cdev->tcdev = thermal_of_cooling_device_register(child,
 858                                                         cdev->name,
 859                                                         cdev,
 860                                                         &aspeed_pwm_cool_ops);
 861        if (IS_ERR(cdev->tcdev))
 862                return PTR_ERR(cdev->tcdev);
 863
 864        cdev->priv = priv;
 865        cdev->pwm_port = pwm_port;
 866
 867        priv->cdev[pwm_port] = cdev;
 868
 869        return 0;
 870}
 871
 872static int aspeed_create_fan(struct device *dev,
 873                             struct device_node *child,
 874                             struct aspeed_pwm_tacho_data *priv)
 875{
 876        u8 *fan_tach_ch;
 877        u32 pwm_port;
 878        int ret, count;
 879
 880        ret = of_property_read_u32(child, "reg", &pwm_port);
 881        if (ret)
 882                return ret;
 883        aspeed_create_pwm_port(priv, (u8)pwm_port);
 884
 885        ret = of_property_count_u8_elems(child, "cooling-levels");
 886
 887        if (ret > 0) {
 888                ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
 889                                                ret);
 890                if (ret)
 891                        return ret;
 892        }
 893
 894        count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
 895        if (count < 1)
 896                return -EINVAL;
 897        fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
 898                                   GFP_KERNEL);
 899        if (!fan_tach_ch)
 900                return -ENOMEM;
 901        ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
 902                                        fan_tach_ch, count);
 903        if (ret)
 904                return ret;
 905        aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
 906
 907        return 0;
 908}
 909
 910static void aspeed_pwm_tacho_remove(void *data)
 911{
 912        struct aspeed_pwm_tacho_data *priv = data;
 913
 914        reset_control_assert(priv->rst);
 915}
 916
 917static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
 918{
 919        struct device *dev = &pdev->dev;
 920        struct device_node *np, *child;
 921        struct aspeed_pwm_tacho_data *priv;
 922        void __iomem *regs;
 923        struct resource *res;
 924        struct device *hwmon;
 925        struct clk *clk;
 926        int ret;
 927
 928        np = dev->of_node;
 929
 930        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 931        if (!res)
 932                return -ENOENT;
 933        regs = devm_ioremap_resource(dev, res);
 934        if (IS_ERR(regs))
 935                return PTR_ERR(regs);
 936        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 937        if (!priv)
 938                return -ENOMEM;
 939        priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
 940                        &aspeed_pwm_tacho_regmap_config);
 941        if (IS_ERR(priv->regmap))
 942                return PTR_ERR(priv->regmap);
 943
 944        priv->rst = devm_reset_control_get_exclusive(dev, NULL);
 945        if (IS_ERR(priv->rst)) {
 946                dev_err(dev,
 947                        "missing or invalid reset controller device tree entry");
 948                return PTR_ERR(priv->rst);
 949        }
 950        reset_control_deassert(priv->rst);
 951
 952        ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
 953        if (ret)
 954                return ret;
 955
 956        regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
 957        regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
 958
 959        clk = devm_clk_get(dev, NULL);
 960        if (IS_ERR(clk))
 961                return -ENODEV;
 962        priv->clk_freq = clk_get_rate(clk);
 963        aspeed_set_clock_enable(priv->regmap, true);
 964        aspeed_set_clock_source(priv->regmap, 0);
 965
 966        aspeed_create_type(priv);
 967
 968        for_each_child_of_node(np, child) {
 969                ret = aspeed_create_fan(dev, child, priv);
 970                if (ret) {
 971                        of_node_put(child);
 972                        return ret;
 973                }
 974        }
 975
 976        priv->groups[0] = &pwm_dev_group;
 977        priv->groups[1] = &fan_dev_group;
 978        priv->groups[2] = NULL;
 979        hwmon = devm_hwmon_device_register_with_groups(dev,
 980                                                       "aspeed_pwm_tacho",
 981                                                       priv, priv->groups);
 982        return PTR_ERR_OR_ZERO(hwmon);
 983}
 984
 985static const struct of_device_id of_pwm_tacho_match_table[] = {
 986        { .compatible = "aspeed,ast2400-pwm-tacho", },
 987        { .compatible = "aspeed,ast2500-pwm-tacho", },
 988        {},
 989};
 990MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
 991
 992static struct platform_driver aspeed_pwm_tacho_driver = {
 993        .probe          = aspeed_pwm_tacho_probe,
 994        .driver         = {
 995                .name   = "aspeed_pwm_tacho",
 996                .of_match_table = of_pwm_tacho_match_table,
 997        },
 998};
 999
1000module_platform_driver(aspeed_pwm_tacho_driver);
1001
1002MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
1003MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
1004MODULE_LICENSE("GPL");
1005