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33#ifndef _HNS_ROCE_HW_V2_H
34#define _HNS_ROCE_HW_V2_H
35
36#include <linux/bitops.h>
37
38#define HNS_ROCE_VF_QPC_BT_NUM 256
39#define HNS_ROCE_VF_SRQC_BT_NUM 64
40#define HNS_ROCE_VF_CQC_BT_NUM 64
41#define HNS_ROCE_VF_MPT_BT_NUM 64
42#define HNS_ROCE_VF_EQC_NUM 64
43#define HNS_ROCE_VF_SMAC_NUM 32
44#define HNS_ROCE_VF_SGID_NUM 32
45#define HNS_ROCE_VF_SL_NUM 8
46
47#define HNS_ROCE_V2_MAX_QP_NUM 0x2000
48#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
49#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
50#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
51#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
52#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
53#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
54#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
55#define HNS_ROCE_V2_UAR_NUM 256
56#define HNS_ROCE_V2_PHY_UAR_NUM 1
57#define HNS_ROCE_V2_MAX_IRQ_NUM 65
58#define HNS_ROCE_V2_COMP_VEC_NUM 63
59#define HNS_ROCE_V2_AEQE_VEC_NUM 1
60#define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
61#define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
62#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
63#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
64#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
65#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
66#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
67#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
68#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
69#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
70#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
71#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
72#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
73#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
74#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
75#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
76#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
77#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
78#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
79#define HNS_ROCE_INVALID_LKEY 0x100
80#define HNS_ROCE_CMQ_TX_TIMEOUT 30000
81#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
82#define HNS_ROCE_V2_RSV_QPS 8
83
84#define HNS_ROCE_CONTEXT_HOP_NUM 1
85#define HNS_ROCE_MTT_HOP_NUM 1
86#define HNS_ROCE_CQE_HOP_NUM 1
87#define HNS_ROCE_PBL_HOP_NUM 2
88#define HNS_ROCE_EQE_HOP_NUM 2
89
90#define HNS_ROCE_V2_GID_INDEX_NUM 256
91
92#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
93
94#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
95#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
96#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
97#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
98#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
99#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
100
101#define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
102#define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
103#define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
104#define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
105#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
106#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
107
108#define HNS_ROCE_CMQ_DESC_NUM_S 3
109#define HNS_ROCE_CMQ_EN_B 16
110#define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
111
112#define check_whether_last_step(hop_num, step_idx) \
113 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
114 (step_idx == 1 && hop_num == 1) || \
115 (step_idx == 2 && hop_num == 2))
116#define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
117#define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
118
119#define CMD_CSQ_DESC_NUM 1024
120#define CMD_CRQ_DESC_NUM 1024
121
122enum {
123 NO_ARMED = 0x0,
124 REG_NXT_CEQE = 0x2,
125 REG_NXT_SE_CEQE = 0x3
126};
127
128#define V2_CQ_DB_REQ_NOT_SOL 0
129#define V2_CQ_DB_REQ_NOT 1
130
131#define V2_CQ_STATE_VALID 1
132#define V2_QKEY_VAL 0x80010000
133
134#define GID_LEN_V2 16
135
136#define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
137
138enum {
139 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
140 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
141 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
142 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
143 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
144 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
145 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
146 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
147 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
148 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
149 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
150 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
151 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
152 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
153};
154
155enum {
156 HNS_ROCE_SQ_OPCODE_SEND = 0x0,
157 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
158 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
159 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
160 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
161 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
162 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
163 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
164 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
165 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
166 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
167 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
168 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
169};
170
171enum {
172
173 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
174 HNS_ROCE_V2_OPCODE_SEND = 0x1,
175 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
176 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
177};
178
179enum {
180 HNS_ROCE_V2_SQ_DB = 0x0,
181 HNS_ROCE_V2_RQ_DB = 0x1,
182 HNS_ROCE_V2_SRQ_DB = 0x2,
183 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
184 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
185};
186
187enum {
188 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
189 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
190 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
191 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
192 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
193 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
194 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
195 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
196 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
197 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
198 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
199 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
200 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
201 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
202
203 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
204};
205
206
207enum hns_roce_opcode_type {
208 HNS_QUERY_FW_VER = 0x0001,
209 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
210 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
211 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
212 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
213 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
214 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
215 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
216 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
217 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
218 HNS_ROCE_OPC_POST_MB = 0x8504,
219 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
220 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
221 HNS_SWITCH_PARAMETER_CFG = 0x1033,
222};
223
224enum {
225 TYPE_CRQ,
226 TYPE_CSQ,
227};
228
229enum hns_roce_cmd_return_status {
230 CMD_EXEC_SUCCESS = 0,
231 CMD_NO_AUTH = 1,
232 CMD_NOT_EXEC = 2,
233 CMD_QUEUE_FULL = 3,
234};
235
236enum hns_roce_sgid_type {
237 GID_TYPE_FLAG_ROCE_V1 = 0,
238 GID_TYPE_FLAG_ROCE_V2_IPV4,
239 GID_TYPE_FLAG_ROCE_V2_IPV6,
240};
241
242struct hns_roce_v2_cq_context {
243 __le32 byte_4_pg_ceqn;
244 __le32 byte_8_cqn;
245 __le32 cqe_cur_blk_addr;
246 __le32 byte_16_hop_addr;
247 __le32 cqe_nxt_blk_addr;
248 __le32 byte_24_pgsz_addr;
249 __le32 byte_28_cq_pi;
250 __le32 byte_32_cq_ci;
251 __le32 cqe_ba;
252 __le32 byte_40_cqe_ba;
253 __le32 byte_44_db_record;
254 __le32 db_record_addr;
255 __le32 byte_52_cqe_cnt;
256 __le32 byte_56_cqe_period_maxcnt;
257 __le32 cqe_report_timer;
258 __le32 byte_64_se_cqe_idx;
259};
260#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
261#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
262
263#define V2_CQC_BYTE_4_CQ_ST_S 0
264#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
265
266#define V2_CQC_BYTE_4_POLL_S 2
267
268#define V2_CQC_BYTE_4_SE_S 3
269
270#define V2_CQC_BYTE_4_OVER_IGNORE_S 4
271
272#define V2_CQC_BYTE_4_COALESCE_S 5
273
274#define V2_CQC_BYTE_4_ARM_ST_S 6
275#define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
276
277#define V2_CQC_BYTE_4_SHIFT_S 8
278#define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
279
280#define V2_CQC_BYTE_4_CMD_SN_S 13
281#define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
282
283#define V2_CQC_BYTE_4_CEQN_S 15
284#define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
285
286#define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
287#define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
288
289#define V2_CQC_BYTE_8_CQN_S 0
290#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
291
292#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
293#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
294
295#define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
296#define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
297
298#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
299#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
300
301#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
302#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
303
304#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
305#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
306
307#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
308#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
309
310#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
311#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
312
313#define V2_CQC_BYTE_40_CQE_BA_S 0
314#define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
315
316#define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
317
318#define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
319#define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
320
321#define V2_CQC_BYTE_52_CQE_CNT_S 0
322#define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
323
324#define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
325#define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
326
327#define V2_CQC_BYTE_56_CQ_PERIOD_S 16
328#define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
329
330#define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
331#define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
332
333enum{
334 V2_MPT_ST_VALID = 0x1,
335};
336
337enum hns_roce_v2_qp_state {
338 HNS_ROCE_QP_ST_RST,
339 HNS_ROCE_QP_ST_INIT,
340 HNS_ROCE_QP_ST_RTR,
341 HNS_ROCE_QP_ST_RTS,
342 HNS_ROCE_QP_ST_SQER,
343 HNS_ROCE_QP_ST_SQD,
344 HNS_ROCE_QP_ST_ERR,
345 HNS_ROCE_QP_ST_SQ_DRAINING,
346 HNS_ROCE_QP_NUM_ST
347};
348
349struct hns_roce_v2_qp_context {
350 __le32 byte_4_sqpn_tst;
351 __le32 wqe_sge_ba;
352 __le32 byte_12_sq_hop;
353 __le32 byte_16_buf_ba_pg_sz;
354 __le32 byte_20_smac_sgid_idx;
355 __le32 byte_24_mtu_tc;
356 __le32 byte_28_at_fl;
357 u8 dgid[GID_LEN_V2];
358 __le32 dmac;
359 __le32 byte_52_udpspn_dmac;
360 __le32 byte_56_dqpn_err;
361 __le32 byte_60_qpst_tempid;
362 __le32 qkey_xrcd;
363 __le32 byte_68_rq_db;
364 __le32 rq_db_record_addr;
365 __le32 byte_76_srqn_op_en;
366 __le32 byte_80_rnr_rx_cqn;
367 __le32 byte_84_rq_ci_pi;
368 __le32 rq_cur_blk_addr;
369 __le32 byte_92_srq_info;
370 __le32 byte_96_rx_reqmsn;
371 __le32 rq_nxt_blk_addr;
372 __le32 byte_104_rq_sge;
373 __le32 byte_108_rx_reqepsn;
374 __le32 rq_rnr_timer;
375 __le32 rx_msg_len;
376 __le32 rx_rkey_pkt_info;
377 __le64 rx_va;
378 __le32 byte_132_trrl;
379 __le32 trrl_ba;
380 __le32 byte_140_raq;
381 __le32 byte_144_raq;
382 __le32 byte_148_raq;
383 __le32 byte_152_raq;
384 __le32 byte_156_raq;
385 __le32 byte_160_sq_ci_pi;
386 __le32 sq_cur_blk_addr;
387 __le32 byte_168_irrl_idx;
388 __le32 byte_172_sq_psn;
389 __le32 byte_176_msg_pktn;
390 __le32 sq_cur_sge_blk_addr;
391 __le32 byte_184_irrl_idx;
392 __le32 cur_sge_offset;
393 __le32 byte_192_ext_sge;
394 __le32 byte_196_sq_psn;
395 __le32 byte_200_sq_max;
396 __le32 irrl_ba;
397 __le32 byte_208_irrl;
398 __le32 byte_212_lsn;
399 __le32 sq_timer;
400 __le32 byte_220_retry_psn_msn;
401 __le32 byte_224_retry_msg;
402 __le32 rx_sq_cur_blk_addr;
403 __le32 byte_232_irrl_sge;
404 __le32 irrl_cur_sge_offset;
405 __le32 byte_240_irrl_tail;
406 __le32 byte_244_rnr_rxack;
407 __le32 byte_248_ack_psn;
408 __le32 byte_252_err_txcqn;
409 __le32 byte_256_sqflush_rqcqe;
410};
411
412#define V2_QPC_BYTE_4_TST_S 0
413#define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
414
415#define V2_QPC_BYTE_4_SGE_SHIFT_S 3
416#define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
417
418#define V2_QPC_BYTE_4_SQPN_S 8
419#define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
420
421#define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
422#define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
423
424#define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
425#define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
426
427#define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
428
429#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
430#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
431
432#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
433#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
434
435#define V2_QPC_BYTE_16_PD_S 8
436#define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
437
438#define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
439#define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
440
441#define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
442#define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
443
444#define V2_QPC_BYTE_20_RQWS_S 4
445#define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
446
447#define V2_QPC_BYTE_20_SQ_SHIFT_S 8
448#define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
449
450#define V2_QPC_BYTE_20_RQ_SHIFT_S 12
451#define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
452
453#define V2_QPC_BYTE_20_SGID_IDX_S 16
454#define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
455
456#define V2_QPC_BYTE_20_SMAC_IDX_S 24
457#define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
458
459#define V2_QPC_BYTE_24_HOP_LIMIT_S 0
460#define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
461
462#define V2_QPC_BYTE_24_TC_S 8
463#define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
464
465#define V2_QPC_BYTE_24_VLAN_ID_S 16
466#define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
467
468#define V2_QPC_BYTE_24_MTU_S 28
469#define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
470
471#define V2_QPC_BYTE_28_FL_S 0
472#define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
473
474#define V2_QPC_BYTE_28_SL_S 20
475#define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
476
477#define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
478
479#define V2_QPC_BYTE_28_CE_FLAG_S 25
480
481#define V2_QPC_BYTE_28_LBI_S 26
482
483#define V2_QPC_BYTE_28_AT_S 27
484#define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
485
486#define V2_QPC_BYTE_52_DMAC_S 0
487#define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
488
489#define V2_QPC_BYTE_52_UDPSPN_S 16
490#define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
491
492#define V2_QPC_BYTE_56_DQPN_S 0
493#define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
494
495#define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
496#define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
497#define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
498#define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
499
500#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
501#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
502
503#define V2_QPC_BYTE_60_TEMPID_S 0
504#define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
505
506#define V2_QPC_BYTE_60_SCC_TOKEN_S 8
507#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
508
509#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
510
511#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
512
513#define V2_QPC_BYTE_60_QP_ST_S 29
514#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
515
516#define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
517
518#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
519#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
520
521#define V2_QPC_BYTE_76_SRQN_S 0
522#define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
523
524#define V2_QPC_BYTE_76_SRQ_EN_S 24
525
526#define V2_QPC_BYTE_76_RRE_S 25
527
528#define V2_QPC_BYTE_76_RWE_S 26
529
530#define V2_QPC_BYTE_76_ATE_S 27
531
532#define V2_QPC_BYTE_76_RQIE_S 28
533
534#define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
535#define V2_QPC_BYTE_80_RX_CQN_S 0
536#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
537
538#define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
539#define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
540
541#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
542#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
543
544#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
545#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
546
547#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
548#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
549
550#define V2_QPC_BYTE_92_SRQ_INFO_S 20
551#define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
552
553#define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
554#define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
555
556#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
557#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
558
559#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
560#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
561
562#define V2_QPC_BYTE_108_INV_CREDIT_S 0
563
564#define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
565
566#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
567#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
568
569#define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
570
571#define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
572#define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
573
574#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
575#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
576
577#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
578#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
579
580#define V2_QPC_BYTE_132_TRRL_BA_S 16
581#define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
582
583#define V2_QPC_BYTE_140_TRRL_BA_S 0
584#define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
585
586#define V2_QPC_BYTE_140_RR_MAX_S 12
587#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
588
589#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
590
591#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
592#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
593
594#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
595#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
596
597#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
598#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
599
600#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
601#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
602
603#define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
604
605#define V2_QPC_BYTE_148_RQ_MSN_S 0
606#define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
607
608#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
609#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
610
611#define V2_QPC_BYTE_152_RAQ_PSN_S 8
612#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8)
613
614#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
615#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
616
617#define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
618#define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
619
620#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
621#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
622
623#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
624#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
625
626#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
627#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
628
629#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
630
631#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
632
633#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
634#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
635
636#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
637#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
638#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
639#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
640#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
641#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
642
643#define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
644#define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
645
646#define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
647
648#define V2_QPC_BYTE_172_FRE_S 7
649
650#define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
651#define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
652
653#define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
654#define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
655
656#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
657#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
658
659#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
660#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
661
662#define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
663#define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
664
665#define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
666#define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
667
668#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
669#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
670
671#define V2_QPC_BYTE_196_IRRL_HEAD_S 0
672#define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
673
674#define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
675#define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
676
677#define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
678#define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
679
680#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
681#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
682
683#define V2_QPC_BYTE_208_IRRL_BA_S 0
684#define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
685
686#define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
687
688#define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
689
690#define V2_QPC_BYTE_208_RMT_E2E_S 28
691
692#define V2_QPC_BYTE_208_SR_MAX_S 29
693#define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
694
695#define V2_QPC_BYTE_212_LSN_S 0
696#define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
697
698#define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
699#define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
700
701#define V2_QPC_BYTE_212_CHECK_FLG_S 27
702#define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
703
704#define V2_QPC_BYTE_212_RETRY_CNT_S 29
705#define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
706
707#define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
708#define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
709
710#define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
711#define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
712
713#define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
714#define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
715
716#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
717#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
718
719#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
720#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
721
722#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
723#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
724
725#define V2_QPC_BYTE_232_SO_LP_VLD_S 29
726#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
727#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
728
729#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
730#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
731
732#define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
733#define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
734
735#define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
736#define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
737
738#define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
739#define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
740
741#define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
742#define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
743
744#define V2_QPC_BYTE_244_RNR_CNT_S 27
745#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
746
747#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
748#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
749
750#define V2_QPC_BYTE_248_IRRL_PSN_S 0
751#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
752
753#define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
754
755#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
756#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
757
758#define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
759
760#define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
761
762#define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
763
764#define V2_QPC_BYTE_252_TX_CQN_S 0
765#define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
766
767#define V2_QPC_BYTE_252_SIG_TYPE_S 24
768
769#define V2_QPC_BYTE_252_ERR_TYPE_S 25
770#define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
771
772#define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
773#define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
774
775#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
776#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
777
778struct hns_roce_v2_cqe {
779 __le32 byte_4;
780 union {
781 __le32 rkey;
782 __le32 immtdata;
783 };
784 __le32 byte_12;
785 __le32 byte_16;
786 __le32 byte_cnt;
787 u8 smac[4];
788 __le32 byte_28;
789 __le32 byte_32;
790};
791
792#define V2_CQE_BYTE_4_OPCODE_S 0
793#define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
794
795#define V2_CQE_BYTE_4_RQ_INLINE_S 5
796
797#define V2_CQE_BYTE_4_S_R_S 6
798
799#define V2_CQE_BYTE_4_OWNER_S 7
800
801#define V2_CQE_BYTE_4_STATUS_S 8
802#define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
803
804#define V2_CQE_BYTE_4_WQE_INDX_S 16
805#define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
806
807#define V2_CQE_BYTE_12_XRC_SRQN_S 0
808#define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
809
810#define V2_CQE_BYTE_16_LCL_QPN_S 0
811#define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
812
813#define V2_CQE_BYTE_16_SUB_STATUS_S 24
814#define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
815
816#define V2_CQE_BYTE_28_SMAC_4_S 0
817#define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
818
819#define V2_CQE_BYTE_28_SMAC_5_S 8
820#define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
821
822#define V2_CQE_BYTE_28_PORT_TYPE_S 16
823#define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
824
825#define V2_CQE_BYTE_32_RMT_QPN_S 0
826#define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
827
828#define V2_CQE_BYTE_32_SL_S 24
829#define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
830
831#define V2_CQE_BYTE_32_PORTN_S 27
832#define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
833
834#define V2_CQE_BYTE_32_GRH_S 30
835
836#define V2_CQE_BYTE_32_LPK_S 31
837
838struct hns_roce_v2_mpt_entry {
839 __le32 byte_4_pd_hop_st;
840 __le32 byte_8_mw_cnt_en;
841 __le32 byte_12_mw_pa;
842 __le32 bound_lkey;
843 __le32 len_l;
844 __le32 len_h;
845 __le32 lkey;
846 __le32 va_l;
847 __le32 va_h;
848 __le32 pbl_size;
849 __le32 pbl_ba_l;
850 __le32 byte_48_mode_ba;
851 __le32 pa0_l;
852 __le32 byte_56_pa0_h;
853 __le32 pa1_l;
854 __le32 byte_64_buf_pa1;
855};
856
857#define V2_MPT_BYTE_4_MPT_ST_S 0
858#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
859
860#define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
861#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
862
863#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
864#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
865
866#define V2_MPT_BYTE_4_PD_S 8
867#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
868
869#define V2_MPT_BYTE_8_RA_EN_S 0
870
871#define V2_MPT_BYTE_8_R_INV_EN_S 1
872
873#define V2_MPT_BYTE_8_L_INV_EN_S 2
874
875#define V2_MPT_BYTE_8_BIND_EN_S 3
876
877#define V2_MPT_BYTE_8_ATOMIC_EN_S 4
878
879#define V2_MPT_BYTE_8_RR_EN_S 5
880
881#define V2_MPT_BYTE_8_RW_EN_S 6
882
883#define V2_MPT_BYTE_8_LW_EN_S 7
884
885#define V2_MPT_BYTE_12_PA_S 1
886
887#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
888
889#define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
890#define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
891
892#define V2_MPT_BYTE_48_PBL_BA_H_S 0
893#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
894
895#define V2_MPT_BYTE_48_BLK_MODE_S 29
896
897#define V2_MPT_BYTE_56_PA0_H_S 0
898#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
899
900#define V2_MPT_BYTE_64_PA1_H_S 0
901#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
902
903#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
904#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
905
906#define V2_DB_BYTE_4_TAG_S 0
907#define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
908
909#define V2_DB_BYTE_4_CMD_S 24
910#define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
911
912#define V2_DB_PARAMETER_IDX_S 0
913#define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
914
915#define V2_DB_PARAMETER_SL_S 16
916#define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
917
918struct hns_roce_v2_cq_db {
919 __le32 byte_4;
920 __le32 parameter;
921};
922
923#define V2_CQ_DB_BYTE_4_TAG_S 0
924#define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
925
926#define V2_CQ_DB_BYTE_4_CMD_S 24
927#define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
928
929#define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
930#define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
931
932#define V2_CQ_DB_PARAMETER_CMD_SN_S 25
933#define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
934
935#define V2_CQ_DB_PARAMETER_NOTIFY_S 24
936
937struct hns_roce_v2_ud_send_wqe {
938 __le32 byte_4;
939 __le32 msg_len;
940 __le32 immtdata;
941 __le32 byte_16;
942 __le32 byte_20;
943 __le32 byte_24;
944 __le32 qkey;
945 __le32 byte_32;
946 __le32 byte_36;
947 __le32 byte_40;
948 __le32 dmac;
949 __le32 byte_48;
950 u8 dgid[GID_LEN_V2];
951
952};
953#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
954#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
955
956#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
957
958#define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
959
960#define V2_UD_SEND_WQE_BYTE_4_SE_S 11
961
962#define V2_UD_SEND_WQE_BYTE_16_PD_S 0
963#define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
964
965#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
966#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
967
968#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
969#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
970
971#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
972#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
973
974#define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
975#define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
976
977#define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
978#define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
979
980#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
981#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
982
983#define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
984#define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
985
986#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
987#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
988
989#define V2_UD_SEND_WQE_BYTE_40_SL_S 20
990#define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
991
992#define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
993#define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
994
995#define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
996
997#define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
998
999#define V2_UD_SEND_WQE_DMAC_0_S 0
1000#define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
1001
1002#define V2_UD_SEND_WQE_DMAC_1_S 8
1003#define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
1004
1005#define V2_UD_SEND_WQE_DMAC_2_S 16
1006#define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1007
1008#define V2_UD_SEND_WQE_DMAC_3_S 24
1009#define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1010
1011#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1012#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1013
1014#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
1015#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
1016
1017#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
1018#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1019
1020#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
1021#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1022
1023struct hns_roce_v2_rc_send_wqe {
1024 __le32 byte_4;
1025 __le32 msg_len;
1026 union {
1027 __le32 inv_key;
1028 __le32 immtdata;
1029 };
1030 __le32 byte_16;
1031 __le32 byte_20;
1032 __le32 rkey;
1033 __le64 va;
1034};
1035
1036#define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1037#define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1038
1039#define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1040
1041#define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1042
1043#define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1044
1045#define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1046
1047#define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1048
1049#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1050
1051#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1052#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1053
1054#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1055#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1056
1057#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1058#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1059
1060struct hns_roce_v2_wqe_data_seg {
1061 __le32 len;
1062 __le32 lkey;
1063 __le64 addr;
1064};
1065
1066struct hns_roce_v2_db {
1067 __le32 byte_4;
1068 __le32 parameter;
1069};
1070
1071struct hns_roce_query_version {
1072 __le16 rocee_vendor_id;
1073 __le16 rocee_hw_version;
1074 __le32 rsv[5];
1075};
1076
1077struct hns_roce_query_fw_info {
1078 __le32 fw_ver;
1079 __le32 rsv[5];
1080};
1081
1082struct hns_roce_cfg_llm_a {
1083 __le32 base_addr_l;
1084 __le32 base_addr_h;
1085 __le32 depth_pgsz_init_en;
1086 __le32 head_ba_l;
1087 __le32 head_ba_h_nxtptr;
1088 __le32 head_ptr;
1089};
1090
1091#define CFG_LLM_QUE_DEPTH_S 0
1092#define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1093
1094#define CFG_LLM_QUE_PGSZ_S 16
1095#define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1096
1097#define CFG_LLM_INIT_EN_S 20
1098#define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1099
1100#define CFG_LLM_HEAD_PTR_S 0
1101#define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1102
1103struct hns_roce_cfg_llm_b {
1104 __le32 tail_ba_l;
1105 __le32 tail_ba_h;
1106 __le32 tail_ptr;
1107 __le32 rsv[3];
1108};
1109
1110#define CFG_LLM_TAIL_BA_H_S 0
1111#define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1112
1113#define CFG_LLM_TAIL_PTR_S 0
1114#define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1115
1116struct hns_roce_cfg_global_param {
1117 __le32 time_cfg_udp_port;
1118 __le32 rsv[5];
1119};
1120
1121#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1122#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1123
1124#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1125#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1126
1127struct hns_roce_pf_res_a {
1128 __le32 rsv;
1129 __le32 qpc_bt_idx_num;
1130 __le32 srqc_bt_idx_num;
1131 __le32 cqc_bt_idx_num;
1132 __le32 mpt_bt_idx_num;
1133 __le32 eqc_bt_idx_num;
1134};
1135
1136#define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1137#define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1138
1139#define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1140#define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1141
1142#define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1143#define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1144
1145#define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1146#define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1147
1148#define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1149#define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1150
1151#define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1152#define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1153
1154#define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1155#define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1156
1157#define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1158#define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1159
1160#define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1161#define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1162
1163#define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1164#define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1165
1166struct hns_roce_pf_res_b {
1167 __le32 rsv0;
1168 __le32 smac_idx_num;
1169 __le32 sgid_idx_num;
1170 __le32 qid_idx_sl_num;
1171 __le32 rsv[2];
1172};
1173
1174#define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1175#define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1176
1177#define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1178#define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1179
1180#define PF_RES_DATA_2_PF_SGID_IDX_S 0
1181#define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1182
1183#define PF_RES_DATA_2_PF_SGID_NUM_S 8
1184#define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1185
1186#define PF_RES_DATA_3_PF_QID_IDX_S 0
1187#define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1188
1189#define PF_RES_DATA_3_PF_SL_NUM_S 16
1190#define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1191
1192struct hns_roce_vf_res_a {
1193 __le32 vf_id;
1194 __le32 vf_qpc_bt_idx_num;
1195 __le32 vf_srqc_bt_idx_num;
1196 __le32 vf_cqc_bt_idx_num;
1197 __le32 vf_mpt_bt_idx_num;
1198 __le32 vf_eqc_bt_idx_num;
1199};
1200
1201#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1202#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1203
1204#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1205#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1206
1207#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1208#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1209
1210#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1211#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1212
1213#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1214#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1215
1216#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1217#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1218
1219#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1220#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1221
1222#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1223#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1224
1225#define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1226#define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1227
1228#define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1229#define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1230
1231struct hns_roce_vf_res_b {
1232 __le32 rsv0;
1233 __le32 vf_smac_idx_num;
1234 __le32 vf_sgid_idx_num;
1235 __le32 vf_qid_idx_sl_num;
1236 __le32 rsv[2];
1237};
1238
1239#define VF_RES_B_DATA_0_VF_ID_S 0
1240#define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1241
1242#define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1243#define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1244
1245#define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1246#define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1247
1248#define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1249#define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1250
1251#define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1252#define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1253
1254#define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1255#define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1256
1257#define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1258#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1259
1260struct hns_roce_vf_switch {
1261 __le32 rocee_sel;
1262 __le32 fun_id;
1263 __le32 cfg;
1264 __le32 resv1;
1265 __le32 resv2;
1266 __le32 resv3;
1267};
1268
1269#define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1270#define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1271
1272#define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1273#define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1274#define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1275
1276struct hns_roce_post_mbox {
1277 __le32 in_param_l;
1278 __le32 in_param_h;
1279 __le32 out_param_l;
1280 __le32 out_param_h;
1281 __le32 cmd_tag;
1282 __le32 token_event_en;
1283};
1284
1285struct hns_roce_mbox_status {
1286 __le32 mb_status_hw_run;
1287 __le32 rsv[5];
1288};
1289
1290struct hns_roce_cfg_bt_attr {
1291 __le32 vf_qpc_cfg;
1292 __le32 vf_srqc_cfg;
1293 __le32 vf_cqc_cfg;
1294 __le32 vf_mpt_cfg;
1295 __le32 rsv[2];
1296};
1297
1298#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1299#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1300
1301#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1302#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1303
1304#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1305#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1306
1307#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1308#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1309
1310#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1311#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1312
1313#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1314#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1315
1316#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1317#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1318
1319#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1320#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1321
1322#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1323#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1324
1325#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1326#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1327
1328#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1329#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1330
1331#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1332#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1333
1334struct hns_roce_cfg_sgid_tb {
1335 __le32 table_idx_rsv;
1336 __le32 vf_sgid_l;
1337 __le32 vf_sgid_ml;
1338 __le32 vf_sgid_mh;
1339 __le32 vf_sgid_h;
1340 __le32 vf_sgid_type_rsv;
1341};
1342#define CFG_SGID_TB_TABLE_IDX_S 0
1343#define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1344
1345#define CFG_SGID_TB_VF_SGID_TYPE_S 0
1346#define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1347
1348struct hns_roce_cfg_smac_tb {
1349 __le32 tb_idx_rsv;
1350 __le32 vf_smac_l;
1351 __le32 vf_smac_h_rsv;
1352 __le32 rsv[3];
1353};
1354#define CFG_SMAC_TB_IDX_S 0
1355#define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1356
1357#define CFG_SMAC_TB_VF_SMAC_H_S 0
1358#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1359
1360struct hns_roce_cmq_desc {
1361 __le16 opcode;
1362 __le16 flag;
1363 __le16 retval;
1364 __le16 rsv;
1365 __le32 data[6];
1366};
1367
1368#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1369
1370#define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1371#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1372
1373struct hns_roce_v2_cmq_ring {
1374 dma_addr_t desc_dma_addr;
1375 struct hns_roce_cmq_desc *desc;
1376 u32 head;
1377 u32 tail;
1378
1379 u16 buf_size;
1380 u16 desc_num;
1381 int next_to_use;
1382 int next_to_clean;
1383 u8 flag;
1384 spinlock_t lock;
1385};
1386
1387struct hns_roce_v2_cmq {
1388 struct hns_roce_v2_cmq_ring csq;
1389 struct hns_roce_v2_cmq_ring crq;
1390 u16 tx_timeout;
1391 u16 last_status;
1392};
1393
1394enum hns_roce_link_table_type {
1395 TSQ_LINK_TABLE,
1396 TPQ_LINK_TABLE,
1397};
1398
1399struct hns_roce_link_table {
1400 struct hns_roce_buf_list table;
1401 struct hns_roce_buf_list *pg_list;
1402 u32 npages;
1403 u32 pg_sz;
1404};
1405
1406struct hns_roce_link_table_entry {
1407 u32 blk_ba0;
1408 u32 blk_ba1_nxt_ptr;
1409};
1410#define HNS_ROCE_LINK_TABLE_BA1_S 0
1411#define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1412
1413#define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1414#define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1415
1416struct hns_roce_v2_priv {
1417 struct hns_roce_v2_cmq cmq;
1418 struct hns_roce_link_table tsq;
1419 struct hns_roce_link_table tpq;
1420};
1421
1422struct hns_roce_eq_context {
1423 __le32 byte_4;
1424 __le32 byte_8;
1425 __le32 byte_12;
1426 __le32 eqe_report_timer;
1427 __le32 eqe_ba0;
1428 __le32 eqe_ba1;
1429 __le32 byte_28;
1430 __le32 byte_32;
1431 __le32 byte_36;
1432 __le32 nxt_eqe_ba0;
1433 __le32 nxt_eqe_ba1;
1434 __le32 rsv[5];
1435};
1436
1437#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1438#define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1439#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1440#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1441
1442#define HNS_ROCE_V2_EQ_STATE_INVALID 0
1443#define HNS_ROCE_V2_EQ_STATE_VALID 1
1444#define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1445#define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1446
1447#define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1448#define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1449
1450#define HNS_ROCE_V2_EQ_COALESCE_0 0
1451#define HNS_ROCE_V2_EQ_COALESCE_1 1
1452
1453#define HNS_ROCE_V2_EQ_FIRED 0
1454#define HNS_ROCE_V2_EQ_ARMED 1
1455#define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1456
1457#define HNS_ROCE_EQ_INIT_EQE_CNT 0
1458#define HNS_ROCE_EQ_INIT_PROD_IDX 0
1459#define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1460#define HNS_ROCE_EQ_INIT_MSI_IDX 0
1461#define HNS_ROCE_EQ_INIT_CONS_IDX 0
1462#define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1463
1464#define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1465#define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1466
1467#define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1468#define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1469
1470#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1471#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1
1472#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2
1473
1474#define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1475#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1476#define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1477#define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1478
1479#define EQ_ENABLE 1
1480#define EQ_DISABLE 0
1481
1482#define EQ_REG_OFFSET 0x4
1483
1484#define HNS_ROCE_INT_NAME_LEN 32
1485#define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1486
1487#define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1488
1489#define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1490#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1491#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1492#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1493#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1494
1495
1496#define HNS_ROCE_EQC_EQ_ST_S 0
1497#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1498
1499#define HNS_ROCE_EQC_HOP_NUM_S 2
1500#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1501
1502#define HNS_ROCE_EQC_OVER_IGNORE_S 4
1503#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1504
1505#define HNS_ROCE_EQC_COALESCE_S 5
1506#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1507
1508#define HNS_ROCE_EQC_ARM_ST_S 6
1509#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1510
1511#define HNS_ROCE_EQC_EQN_S 8
1512#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1513
1514#define HNS_ROCE_EQC_EQE_CNT_S 16
1515#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1516
1517
1518#define HNS_ROCE_EQC_BA_PG_SZ_S 0
1519#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1520
1521#define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1522#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1523
1524#define HNS_ROCE_EQC_PROD_INDX_S 8
1525#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1526
1527
1528#define HNS_ROCE_EQC_MAX_CNT_S 0
1529#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1530
1531#define HNS_ROCE_EQC_PERIOD_S 16
1532#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1533
1534
1535#define HNS_ROCE_EQC_REPORT_TIMER_S 0
1536#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1537
1538
1539#define HNS_ROCE_EQC_EQE_BA_L_S 0
1540#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1541
1542
1543#define HNS_ROCE_EQC_EQE_BA_H_S 0
1544#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1545
1546
1547#define HNS_ROCE_EQC_SHIFT_S 0
1548#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1549
1550#define HNS_ROCE_EQC_MSI_INDX_S 8
1551#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1552
1553#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1554#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1555
1556
1557#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1558#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1559
1560
1561#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1562#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1563
1564#define HNS_ROCE_EQC_CONS_INDX_S 8
1565#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1566
1567
1568#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1569#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1570
1571
1572#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1573#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1574
1575#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1576#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1577
1578#define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1579#define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1580
1581#define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1582#define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1583
1584#define HNS_ROCE_V2_EQ_DB_CMD_S 16
1585#define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16)
1586
1587#define HNS_ROCE_V2_EQ_DB_TAG_S 0
1588#define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1589
1590#define HNS_ROCE_V2_EQ_DB_PARA_S 0
1591#define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1592
1593#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1594#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1595
1596#endif
1597