1
2
3#ifndef IRDMA_H
4#define IRDMA_H
5
6#define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20)
7
8#define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0)
9#define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31)
10
11#define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0)
12#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16)
13#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4)
14#define IRDMA_GLINT_RATE_INTERVAL GENMASK(5, 0)
15#define IRDMA_GLINT_RATE_INTRL_ENA BIT(6)
16#define IRDMA_GLINT_DYN_CTL_INTENA BIT(0)
17#define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1)
18#define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3)
19#define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5)
20#define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11)
21#define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30)
22#define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0)
23#define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0)
24#define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11)
25#define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30)
26#define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0)
27#define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15)
28#define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16)
29#define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0)
30#define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1)
31#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2)
32#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12)
33#define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31)
34
35#define IRDMA_INVALID_CQ_IDX 0xffffffff
36enum irdma_registers {
37 IRDMA_CQPTAIL,
38 IRDMA_CQPDB,
39 IRDMA_CCQPSTATUS,
40 IRDMA_CCQPHIGH,
41 IRDMA_CCQPLOW,
42 IRDMA_CQARM,
43 IRDMA_CQACK,
44 IRDMA_AEQALLOC,
45 IRDMA_CQPERRCODES,
46 IRDMA_WQEALLOC,
47 IRDMA_GLINT_DYN_CTL,
48 IRDMA_DB_ADDR_OFFSET,
49 IRDMA_GLPCI_LBARCTRL,
50 IRDMA_GLPE_CPUSTATUS0,
51 IRDMA_GLPE_CPUSTATUS1,
52 IRDMA_GLPE_CPUSTATUS2,
53 IRDMA_PFINT_AEQCTL,
54 IRDMA_GLINT_CEQCTL,
55 IRDMA_VSIQF_PE_CTL1,
56 IRDMA_PFHMC_PDINV,
57 IRDMA_GLHMC_VFPDINV,
58 IRDMA_GLPE_CRITERR,
59 IRDMA_GLINT_RATE,
60 IRDMA_MAX_REGS,
61};
62
63enum irdma_shifts {
64 IRDMA_CCQPSTATUS_CCQP_DONE_S,
65 IRDMA_CCQPSTATUS_CCQP_ERR_S,
66 IRDMA_CQPSQ_STAG_PDID_S,
67 IRDMA_CQPSQ_CQ_CEQID_S,
68 IRDMA_CQPSQ_CQ_CQID_S,
69 IRDMA_COMMIT_FPM_CQCNT_S,
70 IRDMA_MAX_SHIFTS,
71};
72
73enum irdma_masks {
74 IRDMA_CCQPSTATUS_CCQP_DONE_M,
75 IRDMA_CCQPSTATUS_CCQP_ERR_M,
76 IRDMA_CQPSQ_STAG_PDID_M,
77 IRDMA_CQPSQ_CQ_CEQID_M,
78 IRDMA_CQPSQ_CQ_CQID_M,
79 IRDMA_COMMIT_FPM_CQCNT_M,
80 IRDMA_MAX_MASKS,
81};
82
83#define IRDMA_MAX_MGS_PER_CTX 8
84
85struct irdma_mcast_grp_ctx_entry_info {
86 u32 qp_id;
87 bool valid_entry;
88 u16 dest_port;
89 u32 use_cnt;
90};
91
92struct irdma_mcast_grp_info {
93 u8 dest_mac_addr[ETH_ALEN];
94 u16 vlan_id;
95 u8 hmc_fcn_id;
96 bool ipv4_valid:1;
97 bool vlan_valid:1;
98 u16 mg_id;
99 u32 no_of_mgs;
100 u32 dest_ip_addr[4];
101 u16 qs_handle;
102 struct irdma_dma_mem dma_mem_mc;
103 struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX];
104};
105
106enum irdma_vers {
107 IRDMA_GEN_RSVD,
108 IRDMA_GEN_1,
109 IRDMA_GEN_2,
110};
111
112struct irdma_uk_attrs {
113 u64 feature_flags;
114 u32 max_hw_wq_frags;
115 u32 max_hw_read_sges;
116 u32 max_hw_inline;
117 u32 max_hw_rq_quanta;
118 u32 max_hw_wq_quanta;
119 u32 min_hw_cq_size;
120 u32 max_hw_cq_size;
121 u16 max_hw_sq_chunk;
122 u8 hw_rev;
123};
124
125struct irdma_hw_attrs {
126 struct irdma_uk_attrs uk_attrs;
127 u64 max_hw_outbound_msg_size;
128 u64 max_hw_inbound_msg_size;
129 u64 max_mr_size;
130 u32 min_hw_qp_id;
131 u32 min_hw_aeq_size;
132 u32 max_hw_aeq_size;
133 u32 min_hw_ceq_size;
134 u32 max_hw_ceq_size;
135 u32 max_hw_device_pages;
136 u32 max_hw_vf_fpm_id;
137 u32 first_hw_vf_fpm_id;
138 u32 max_hw_ird;
139 u32 max_hw_ord;
140 u32 max_hw_wqes;
141 u32 max_hw_pds;
142 u32 max_hw_ena_vf_count;
143 u32 max_qp_wr;
144 u32 max_pe_ready_count;
145 u32 max_done_count;
146 u32 max_sleep_count;
147 u32 max_cqp_compl_wait_time_ms;
148 u16 max_stat_inst;
149};
150
151void i40iw_init_hw(struct irdma_sc_dev *dev);
152void icrdma_init_hw(struct irdma_sc_dev *dev);
153#endif
154
