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19#include "cx23885.h"
20#include "cx23888-ir.h"
21
22#include <linux/kfifo.h>
23#include <linux/slab.h>
24
25#include <media/v4l2-device.h>
26#include <media/rc-core.h>
27
28static unsigned int ir_888_debug;
29module_param(ir_888_debug, int, 0644);
30MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
31
32#define CX23888_IR_REG_BASE 0x170000
33
34
35
36
37#define CX23888_IR_CNTRL_REG 0x170000
38#define CNTRL_WIN_3_3 0x00000000
39#define CNTRL_WIN_4_3 0x00000001
40#define CNTRL_WIN_3_4 0x00000002
41#define CNTRL_WIN_4_4 0x00000003
42#define CNTRL_WIN 0x00000003
43#define CNTRL_EDG_NONE 0x00000000
44#define CNTRL_EDG_FALL 0x00000004
45#define CNTRL_EDG_RISE 0x00000008
46#define CNTRL_EDG_BOTH 0x0000000C
47#define CNTRL_EDG 0x0000000C
48#define CNTRL_DMD 0x00000010
49#define CNTRL_MOD 0x00000020
50#define CNTRL_RFE 0x00000040
51#define CNTRL_TFE 0x00000080
52#define CNTRL_RXE 0x00000100
53#define CNTRL_TXE 0x00000200
54#define CNTRL_RIC 0x00000400
55#define CNTRL_TIC 0x00000800
56#define CNTRL_CPL 0x00001000
57#define CNTRL_LBM 0x00002000
58#define CNTRL_R 0x00004000
59
60#define CNTRL_IVO 0x00008000
61
62#define CX23888_IR_TXCLK_REG 0x170004
63#define TXCLK_TCD 0x0000FFFF
64
65#define CX23888_IR_RXCLK_REG 0x170008
66#define RXCLK_RCD 0x0000FFFF
67
68#define CX23888_IR_CDUTY_REG 0x17000C
69#define CDUTY_CDC 0x0000000F
70
71#define CX23888_IR_STATS_REG 0x170010
72#define STATS_RTO 0x00000001
73#define STATS_ROR 0x00000002
74#define STATS_RBY 0x00000004
75#define STATS_TBY 0x00000008
76#define STATS_RSR 0x00000010
77#define STATS_TSR 0x00000020
78
79#define CX23888_IR_IRQEN_REG 0x170014
80#define IRQEN_RTE 0x00000001
81#define IRQEN_ROE 0x00000002
82#define IRQEN_RSE 0x00000010
83#define IRQEN_TSE 0x00000020
84
85#define CX23888_IR_FILTR_REG 0x170018
86#define FILTR_LPF 0x0000FFFF
87
88
89#define CX23888_IR_FIFO_REG 0x170040
90#define FIFO_RXTX 0x0000FFFF
91#define FIFO_RXTX_LVL 0x00010000
92#define FIFO_RXTX_RTO 0x0001FFFF
93#define FIFO_RX_NDV 0x00020000
94#define FIFO_RX_DEPTH 8
95#define FIFO_TX_DEPTH 8
96
97
98#define CX23888_IR_SEEDP_REG 0x17001C
99#define CX23888_IR_TIMOL_REG 0x170020
100#define CX23888_IR_WAKE0_REG 0x170024
101#define CX23888_IR_WAKE1_REG 0x170028
102#define CX23888_IR_WAKE2_REG 0x17002C
103#define CX23888_IR_MASK0_REG 0x170030
104#define CX23888_IR_MASK1_REG 0x170034
105#define CX23888_IR_MAKS2_REG 0x170038
106#define CX23888_IR_DPIPG_REG 0x17003C
107#define CX23888_IR_LEARN_REG 0x170044
108
109#define CX23888_VIDCLK_FREQ 108000000
110#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
111
112
113
114
115
116
117union cx23888_ir_fifo_rec {
118 u32 hw_fifo_data;
119 struct ir_raw_event ir_core_data;
120};
121
122#define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
123#define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
124
125struct cx23888_ir_state {
126 struct v4l2_subdev sd;
127 struct cx23885_dev *dev;
128
129 struct v4l2_subdev_ir_parameters rx_params;
130 struct mutex rx_params_lock;
131 atomic_t rxclk_divider;
132 atomic_t rx_invert;
133
134 struct kfifo rx_kfifo;
135 spinlock_t rx_kfifo_lock;
136
137 struct v4l2_subdev_ir_parameters tx_params;
138 struct mutex tx_params_lock;
139 atomic_t txclk_divider;
140};
141
142static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
143{
144 return v4l2_get_subdevdata(sd);
145}
146
147
148
149
150static
151inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
152{
153 cx_write(addr, value);
154 return 0;
155}
156
157static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
158{
159 return cx_read(addr);
160}
161
162static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
163 u32 and_mask, u32 or_value)
164{
165 cx_andor(addr, ~and_mask, or_value);
166 return 0;
167}
168
169
170
171
172
173
174
175
176static inline u16 count_to_clock_divider(unsigned int d)
177{
178 if (d > RXCLK_RCD + 1)
179 d = RXCLK_RCD;
180 else if (d < 2)
181 d = 1;
182 else
183 d--;
184 return (u16) d;
185}
186
187static inline u16 ns_to_clock_divider(unsigned int ns)
188{
189 return count_to_clock_divider(
190 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
191}
192
193static inline unsigned int clock_divider_to_ns(unsigned int divider)
194{
195
196 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
197 CX23888_IR_REFCLK_FREQ / 1000000);
198}
199
200static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
201{
202 return count_to_clock_divider(
203 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
204}
205
206static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
207{
208 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
209}
210
211static inline u16 freq_to_clock_divider(unsigned int freq,
212 unsigned int rollovers)
213{
214 return count_to_clock_divider(
215 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
216}
217
218static inline unsigned int clock_divider_to_freq(unsigned int divider,
219 unsigned int rollovers)
220{
221 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
222 (divider + 1) * rollovers);
223}
224
225
226
227
228
229
230
231
232static inline u16 count_to_lpf_count(unsigned int d)
233{
234 if (d > FILTR_LPF)
235 d = FILTR_LPF;
236 else if (d < 4)
237 d = 0;
238 return (u16) d;
239}
240
241static inline u16 ns_to_lpf_count(unsigned int ns)
242{
243 return count_to_lpf_count(
244 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
245}
246
247static inline unsigned int lpf_count_to_ns(unsigned int count)
248{
249
250 return DIV_ROUND_CLOSEST(count * 1000,
251 CX23888_IR_REFCLK_FREQ / 1000000);
252}
253
254static inline unsigned int lpf_count_to_us(unsigned int count)
255{
256
257 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
258}
259
260
261
262
263static u32 clock_divider_to_resolution(u16 divider)
264{
265
266
267
268
269
270 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
271 CX23888_IR_REFCLK_FREQ / 1000000);
272}
273
274static u64 pulse_width_count_to_ns(u16 count, u16 divider)
275{
276 u64 n;
277 u32 rem;
278
279
280
281
282
283 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000;
284 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000);
285 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
286 n++;
287 return n;
288}
289
290static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
291{
292 u64 n;
293 u32 rem;
294
295
296
297
298
299 n = (((u64) count << 2) | 0x3) * (divider + 1);
300 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000);
301 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
302 n++;
303 return (unsigned int) n;
304}
305
306
307
308
309
310
311
312
313
314static u64 ns_to_pulse_clocks(u32 ns)
315{
316 u64 clocks;
317 u32 rem;
318 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns;
319 rem = do_div(clocks, 1000);
320 if (rem >= 1000 / 2)
321 clocks++;
322 return clocks;
323}
324
325static u16 pulse_clocks_to_clock_divider(u64 count)
326{
327 do_div(count, (FIFO_RXTX << 2) | 0x3);
328
329
330 if (count > RXCLK_RCD + 1)
331 count = RXCLK_RCD;
332 else if (count < 2)
333 count = 1;
334 else
335 count--;
336 return (u16) count;
337}
338
339
340
341
342enum tx_fifo_watermark {
343 TX_FIFO_HALF_EMPTY = 0,
344 TX_FIFO_EMPTY = CNTRL_TIC,
345};
346
347enum rx_fifo_watermark {
348 RX_FIFO_HALF_FULL = 0,
349 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
350};
351
352static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
353 enum tx_fifo_watermark level)
354{
355 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
356}
357
358static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
359 enum rx_fifo_watermark level)
360{
361 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
362}
363
364static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
365{
366 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
367 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
368}
369
370static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
371{
372 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
373 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
374}
375
376static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
377 bool enable)
378{
379 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
380 enable ? CNTRL_MOD : 0);
381}
382
383static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
384 bool enable)
385{
386 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
387 enable ? CNTRL_DMD : 0);
388}
389
390static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
391 u32 edge_types)
392{
393 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
394 edge_types & CNTRL_EDG_BOTH);
395}
396
397static void control_rx_s_carrier_window(struct cx23885_dev *dev,
398 unsigned int carrier,
399 unsigned int *carrier_range_low,
400 unsigned int *carrier_range_high)
401{
402 u32 v;
403 unsigned int c16 = carrier * 16;
404
405 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
406 v = CNTRL_WIN_3_4;
407 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
408 } else {
409 v = CNTRL_WIN_3_3;
410 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
411 }
412
413 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
414 v |= CNTRL_WIN_4_3;
415 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
416 } else {
417 v |= CNTRL_WIN_3_3;
418 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
419 }
420 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
421}
422
423static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
424 bool invert)
425{
426 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
427 invert ? CNTRL_CPL : 0);
428}
429
430static inline void control_tx_level_invert(struct cx23885_dev *dev,
431 bool invert)
432{
433 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
434 invert ? CNTRL_IVO : 0);
435}
436
437
438
439
440static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
441 unsigned int freq,
442 u16 *divider)
443{
444 *divider = carrier_freq_to_clock_divider(freq);
445 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
446 return clock_divider_to_carrier_freq(*divider);
447}
448
449static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
450 unsigned int freq,
451 u16 *divider)
452{
453 *divider = carrier_freq_to_clock_divider(freq);
454 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
455 return clock_divider_to_carrier_freq(*divider);
456}
457
458static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
459 u16 *divider)
460{
461 u64 pulse_clocks;
462
463 if (ns > IR_MAX_DURATION)
464 ns = IR_MAX_DURATION;
465 pulse_clocks = ns_to_pulse_clocks(ns);
466 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
467 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
468 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
469}
470
471static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
472 u16 *divider)
473{
474 u64 pulse_clocks;
475
476 if (ns > IR_MAX_DURATION)
477 ns = IR_MAX_DURATION;
478 pulse_clocks = ns_to_pulse_clocks(ns);
479 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
480 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
481 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
482}
483
484
485
486
487static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
488 unsigned int duty_cycle)
489{
490 u32 n;
491 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625);
492 if (n != 0)
493 n--;
494 if (n > 15)
495 n = 15;
496 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
497 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
498}
499
500
501
502
503static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
504{
505 u32 count = ns_to_lpf_count(min_width_ns);
506 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
507 return lpf_count_to_ns(count);
508}
509
510
511
512
513static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
514{
515 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
516 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
517 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
518}
519
520static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
521{
522 mask &= IRQEN_TSE;
523 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
524}
525
526
527
528
529static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
530 bool *handled)
531{
532 struct cx23888_ir_state *state = to_state(sd);
533 struct cx23885_dev *dev = state->dev;
534 unsigned long flags;
535
536 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
537 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
538 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
539
540 union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
541 unsigned int i, j, k;
542 u32 events, v;
543 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
544
545 tsr = stats & STATS_TSR;
546 rsr = stats & STATS_RSR;
547 rto = stats & STATS_RTO;
548 ror = stats & STATS_ROR;
549
550 tse = irqen & IRQEN_TSE;
551 rse = irqen & IRQEN_RSE;
552 rte = irqen & IRQEN_RTE;
553 roe = irqen & IRQEN_ROE;
554
555 *handled = false;
556 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
557 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
558 rto ? "rto" : " ", ror ? "ror" : " ",
559 stats & STATS_TBY ? "tby" : " ",
560 stats & STATS_RBY ? "rby" : " ");
561
562 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
563 tse ? "tse" : " ", rse ? "rse" : " ",
564 rte ? "rte" : " ", roe ? "roe" : " ");
565
566
567
568
569 if (tse && tsr) {
570
571
572
573
574
575
576
577
578
579
580
581 irqenable_tx(dev, 0);
582 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
583 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
584 *handled = true;
585 }
586
587
588
589
590 kror = 0;
591 if ((rse && rsr) || (rte && rto)) {
592
593
594
595
596
597 for (i = 0, v = FIFO_RX_NDV;
598 (v & FIFO_RX_NDV) && !kror; i = 0) {
599 for (j = 0;
600 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
601 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
602 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
603 i++;
604 }
605 if (i == 0)
606 break;
607 j = i * sizeof(union cx23888_ir_fifo_rec);
608 k = kfifo_in_locked(&state->rx_kfifo,
609 (unsigned char *) rx_data, j,
610 &state->rx_kfifo_lock);
611 if (k != j)
612 kror++;
613 }
614 *handled = true;
615 }
616
617 events = 0;
618 v = 0;
619 if (kror) {
620 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
621 v4l2_err(sd, "IR receiver software FIFO overrun\n");
622 }
623 if (roe && ror) {
624
625
626
627
628 v |= CNTRL_RFE;
629 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
630 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
631 }
632 if (rte && rto) {
633
634
635
636
637 v |= CNTRL_RXE;
638 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
639 }
640 if (v) {
641
642 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
643 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
644 *handled = true;
645 }
646
647 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
648 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
649 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
650 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
651
652 if (events)
653 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
654 return 0;
655}
656
657
658static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
659 ssize_t *num)
660{
661 struct cx23888_ir_state *state = to_state(sd);
662 bool invert = (bool) atomic_read(&state->rx_invert);
663 u16 divider = (u16) atomic_read(&state->rxclk_divider);
664
665 unsigned int i, n;
666 union cx23888_ir_fifo_rec *p;
667 unsigned u, v, w;
668
669 n = count / sizeof(union cx23888_ir_fifo_rec)
670 * sizeof(union cx23888_ir_fifo_rec);
671 if (n == 0) {
672 *num = 0;
673 return 0;
674 }
675
676 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
677
678 n /= sizeof(union cx23888_ir_fifo_rec);
679 *num = n * sizeof(union cx23888_ir_fifo_rec);
680
681 for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
682
683 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
684
685 u = 0;
686 w = 1;
687 } else {
688 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
689 if (invert)
690 u = u ? 0 : 1;
691 w = 0;
692 }
693
694 v = (unsigned) pulse_width_count_to_ns(
695 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
696 if (v > IR_MAX_DURATION)
697 v = IR_MAX_DURATION;
698
699 init_ir_raw_event(&p->ir_core_data);
700 p->ir_core_data.pulse = u;
701 p->ir_core_data.duration = v;
702 p->ir_core_data.timeout = w;
703
704 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n",
705 v, u ? "mark" : "space", w ? "(timed out)" : "");
706 if (w)
707 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
708 }
709 return 0;
710}
711
712static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
713 struct v4l2_subdev_ir_parameters *p)
714{
715 struct cx23888_ir_state *state = to_state(sd);
716 mutex_lock(&state->rx_params_lock);
717 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
718 mutex_unlock(&state->rx_params_lock);
719 return 0;
720}
721
722static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
723{
724 struct cx23888_ir_state *state = to_state(sd);
725 struct cx23885_dev *dev = state->dev;
726
727 mutex_lock(&state->rx_params_lock);
728
729
730 irqenable_rx(dev, 0);
731 control_rx_enable(dev, false);
732 control_rx_demodulation_enable(dev, false);
733 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
734 filter_rx_s_min_width(dev, 0);
735 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
736
737 state->rx_params.shutdown = true;
738
739 mutex_unlock(&state->rx_params_lock);
740 return 0;
741}
742
743static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
744 struct v4l2_subdev_ir_parameters *p)
745{
746 struct cx23888_ir_state *state = to_state(sd);
747 struct cx23885_dev *dev = state->dev;
748 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
749 u16 rxclk_divider;
750
751 if (p->shutdown)
752 return cx23888_ir_rx_shutdown(sd);
753
754 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
755 return -ENOSYS;
756
757 mutex_lock(&state->rx_params_lock);
758
759 o->shutdown = p->shutdown;
760
761 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
762
763 o->bytes_per_data_element = p->bytes_per_data_element
764 = sizeof(union cx23888_ir_fifo_rec);
765
766
767 irqenable_rx(dev, 0);
768 control_rx_enable(dev, false);
769
770 control_rx_demodulation_enable(dev, p->modulation);
771 o->modulation = p->modulation;
772
773 if (p->modulation) {
774 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
775 &rxclk_divider);
776
777 o->carrier_freq = p->carrier_freq;
778
779 o->duty_cycle = p->duty_cycle = 50;
780
781 control_rx_s_carrier_window(dev, p->carrier_freq,
782 &p->carrier_range_lower,
783 &p->carrier_range_upper);
784 o->carrier_range_lower = p->carrier_range_lower;
785 o->carrier_range_upper = p->carrier_range_upper;
786
787 p->max_pulse_width =
788 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
789 } else {
790 p->max_pulse_width =
791 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
792 &rxclk_divider);
793 }
794 o->max_pulse_width = p->max_pulse_width;
795 atomic_set(&state->rxclk_divider, rxclk_divider);
796
797 p->noise_filter_min_width =
798 filter_rx_s_min_width(dev, p->noise_filter_min_width);
799 o->noise_filter_min_width = p->noise_filter_min_width;
800
801 p->resolution = clock_divider_to_resolution(rxclk_divider);
802 o->resolution = p->resolution;
803
804
805 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
806
807 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
808
809 o->invert_level = p->invert_level;
810 atomic_set(&state->rx_invert, p->invert_level);
811
812 o->interrupt_enable = p->interrupt_enable;
813 o->enable = p->enable;
814 if (p->enable) {
815 unsigned long flags;
816
817 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
818 kfifo_reset(&state->rx_kfifo);
819
820 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
821 if (p->interrupt_enable)
822 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
823 control_rx_enable(dev, p->enable);
824 }
825
826 mutex_unlock(&state->rx_params_lock);
827 return 0;
828}
829
830
831static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
832 ssize_t *num)
833{
834 struct cx23888_ir_state *state = to_state(sd);
835 struct cx23885_dev *dev = state->dev;
836
837 irqenable_tx(dev, IRQEN_TSE);
838 *num = count;
839 return 0;
840}
841
842static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
843 struct v4l2_subdev_ir_parameters *p)
844{
845 struct cx23888_ir_state *state = to_state(sd);
846 mutex_lock(&state->tx_params_lock);
847 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
848 mutex_unlock(&state->tx_params_lock);
849 return 0;
850}
851
852static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
853{
854 struct cx23888_ir_state *state = to_state(sd);
855 struct cx23885_dev *dev = state->dev;
856
857 mutex_lock(&state->tx_params_lock);
858
859
860 irqenable_tx(dev, 0);
861 control_tx_enable(dev, false);
862 control_tx_modulation_enable(dev, false);
863 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
864
865 state->tx_params.shutdown = true;
866
867 mutex_unlock(&state->tx_params_lock);
868 return 0;
869}
870
871static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
872 struct v4l2_subdev_ir_parameters *p)
873{
874 struct cx23888_ir_state *state = to_state(sd);
875 struct cx23885_dev *dev = state->dev;
876 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
877 u16 txclk_divider;
878
879 if (p->shutdown)
880 return cx23888_ir_tx_shutdown(sd);
881
882 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
883 return -ENOSYS;
884
885 mutex_lock(&state->tx_params_lock);
886
887 o->shutdown = p->shutdown;
888
889 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
890
891 o->bytes_per_data_element = p->bytes_per_data_element
892 = sizeof(union cx23888_ir_fifo_rec);
893
894
895 irqenable_tx(dev, 0);
896 control_tx_enable(dev, false);
897
898 control_tx_modulation_enable(dev, p->modulation);
899 o->modulation = p->modulation;
900
901 if (p->modulation) {
902 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
903 &txclk_divider);
904 o->carrier_freq = p->carrier_freq;
905
906 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
907 o->duty_cycle = p->duty_cycle;
908
909 p->max_pulse_width =
910 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
911 } else {
912 p->max_pulse_width =
913 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
914 &txclk_divider);
915 }
916 o->max_pulse_width = p->max_pulse_width;
917 atomic_set(&state->txclk_divider, txclk_divider);
918
919 p->resolution = clock_divider_to_resolution(txclk_divider);
920 o->resolution = p->resolution;
921
922
923 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
924
925 control_tx_polarity_invert(dev, p->invert_carrier_sense);
926 o->invert_carrier_sense = p->invert_carrier_sense;
927
928 control_tx_level_invert(dev, p->invert_level);
929 o->invert_level = p->invert_level;
930
931 o->interrupt_enable = p->interrupt_enable;
932 o->enable = p->enable;
933 if (p->enable) {
934 if (p->interrupt_enable)
935 irqenable_tx(dev, IRQEN_TSE);
936 control_tx_enable(dev, p->enable);
937 }
938
939 mutex_unlock(&state->tx_params_lock);
940 return 0;
941}
942
943
944
945
946
947static int cx23888_ir_log_status(struct v4l2_subdev *sd)
948{
949 struct cx23888_ir_state *state = to_state(sd);
950 struct cx23885_dev *dev = state->dev;
951 char *s;
952 int i, j;
953
954 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
955 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
956 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
957 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
958 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
959 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
960 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
961
962 v4l2_info(sd, "IR Receiver:\n");
963 v4l2_info(sd, "\tEnabled: %s\n",
964 cntrl & CNTRL_RXE ? "yes" : "no");
965 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
966 cntrl & CNTRL_DMD ? "enabled" : "disabled");
967 v4l2_info(sd, "\tFIFO: %s\n",
968 cntrl & CNTRL_RFE ? "enabled" : "disabled");
969 switch (cntrl & CNTRL_EDG) {
970 case CNTRL_EDG_NONE:
971 s = "disabled";
972 break;
973 case CNTRL_EDG_FALL:
974 s = "falling edge";
975 break;
976 case CNTRL_EDG_RISE:
977 s = "rising edge";
978 break;
979 case CNTRL_EDG_BOTH:
980 s = "rising & falling edges";
981 break;
982 default:
983 s = "??? edge";
984 break;
985 }
986 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
987 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
988 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
989 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
990 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
991 v4l2_info(sd, "\tLoopback mode: %s\n",
992 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
993 if (cntrl & CNTRL_DMD) {
994 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
995 clock_divider_to_carrier_freq(rxclk));
996 switch (cntrl & CNTRL_WIN) {
997 case CNTRL_WIN_3_3:
998 i = 3;
999 j = 3;
1000 break;
1001 case CNTRL_WIN_4_3:
1002 i = 4;
1003 j = 3;
1004 break;
1005 case CNTRL_WIN_3_4:
1006 i = 3;
1007 j = 4;
1008 break;
1009 case CNTRL_WIN_4_4:
1010 i = 4;
1011 j = 4;
1012 break;
1013 default:
1014 i = 0;
1015 j = 0;
1016 break;
1017 }
1018 v4l2_info(sd, "\tNext carrier edge window: 16 clocks -%1d/+%1d, %u to %u Hz\n",
1019 i, j,
1020 clock_divider_to_freq(rxclk, 16 + j),
1021 clock_divider_to_freq(rxclk, 16 - i));
1022 }
1023 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1024 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1025 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1026 v4l2_info(sd, "\tLow pass filter: %s\n",
1027 filtr ? "enabled" : "disabled");
1028 if (filtr)
1029 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, %u ns\n",
1030 lpf_count_to_us(filtr),
1031 lpf_count_to_ns(filtr));
1032 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1033 stats & STATS_RTO ? "yes" : "no");
1034 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1035 irqen & IRQEN_RTE ? "enabled" : "disabled");
1036 v4l2_info(sd, "\tFIFO overrun: %s\n",
1037 stats & STATS_ROR ? "yes" : "no");
1038 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1039 irqen & IRQEN_ROE ? "enabled" : "disabled");
1040 v4l2_info(sd, "\tBusy: %s\n",
1041 stats & STATS_RBY ? "yes" : "no");
1042 v4l2_info(sd, "\tFIFO service requested: %s\n",
1043 stats & STATS_RSR ? "yes" : "no");
1044 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1045 irqen & IRQEN_RSE ? "enabled" : "disabled");
1046
1047 v4l2_info(sd, "IR Transmitter:\n");
1048 v4l2_info(sd, "\tEnabled: %s\n",
1049 cntrl & CNTRL_TXE ? "yes" : "no");
1050 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1051 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1052 v4l2_info(sd, "\tFIFO: %s\n",
1053 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1054 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1055 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1056 v4l2_info(sd, "\tOutput pin level inversion %s\n",
1057 cntrl & CNTRL_IVO ? "yes" : "no");
1058 v4l2_info(sd, "\tCarrier polarity: %s\n",
1059 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1060 : "space:noburst mark:burst");
1061 if (cntrl & CNTRL_MOD) {
1062 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1063 clock_divider_to_carrier_freq(txclk));
1064 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1065 cduty + 1);
1066 }
1067 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1068 pulse_width_count_to_us(FIFO_RXTX, txclk),
1069 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1070 v4l2_info(sd, "\tBusy: %s\n",
1071 stats & STATS_TBY ? "yes" : "no");
1072 v4l2_info(sd, "\tFIFO service requested: %s\n",
1073 stats & STATS_TSR ? "yes" : "no");
1074 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1075 irqen & IRQEN_TSE ? "enabled" : "disabled");
1076
1077 return 0;
1078}
1079
1080#ifdef CONFIG_VIDEO_ADV_DEBUG
1081static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1082 struct v4l2_dbg_register *reg)
1083{
1084 struct cx23888_ir_state *state = to_state(sd);
1085 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1086
1087 if ((addr & 0x3) != 0)
1088 return -EINVAL;
1089 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1090 return -EINVAL;
1091 reg->size = 4;
1092 reg->val = cx23888_ir_read4(state->dev, addr);
1093 return 0;
1094}
1095
1096static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1097 const struct v4l2_dbg_register *reg)
1098{
1099 struct cx23888_ir_state *state = to_state(sd);
1100 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1101
1102 if ((addr & 0x3) != 0)
1103 return -EINVAL;
1104 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1105 return -EINVAL;
1106 cx23888_ir_write4(state->dev, addr, reg->val);
1107 return 0;
1108}
1109#endif
1110
1111static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1112 .log_status = cx23888_ir_log_status,
1113#ifdef CONFIG_VIDEO_ADV_DEBUG
1114 .g_register = cx23888_ir_g_register,
1115 .s_register = cx23888_ir_s_register,
1116#endif
1117 .interrupt_service_routine = cx23888_ir_irq_handler,
1118};
1119
1120static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1121 .rx_read = cx23888_ir_rx_read,
1122 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1123 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1124
1125 .tx_write = cx23888_ir_tx_write,
1126 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1127 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1128};
1129
1130static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1131 .core = &cx23888_ir_core_ops,
1132 .ir = &cx23888_ir_ir_ops,
1133};
1134
1135static const struct v4l2_subdev_ir_parameters default_rx_params = {
1136 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1137 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1138
1139 .enable = false,
1140 .interrupt_enable = false,
1141 .shutdown = true,
1142
1143 .modulation = true,
1144 .carrier_freq = 36000,
1145
1146
1147
1148 .noise_filter_min_width = 333333,
1149 .carrier_range_lower = 35000,
1150 .carrier_range_upper = 37000,
1151 .invert_level = false,
1152};
1153
1154static const struct v4l2_subdev_ir_parameters default_tx_params = {
1155 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1156 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1157
1158 .enable = false,
1159 .interrupt_enable = false,
1160 .shutdown = true,
1161
1162 .modulation = true,
1163 .carrier_freq = 36000,
1164 .duty_cycle = 25,
1165 .invert_level = false,
1166 .invert_carrier_sense = false,
1167};
1168
1169int cx23888_ir_probe(struct cx23885_dev *dev)
1170{
1171 struct cx23888_ir_state *state;
1172 struct v4l2_subdev *sd;
1173 struct v4l2_subdev_ir_parameters default_params;
1174 int ret;
1175
1176 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1177 if (state == NULL)
1178 return -ENOMEM;
1179
1180 spin_lock_init(&state->rx_kfifo_lock);
1181 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1182 return -ENOMEM;
1183
1184 state->dev = dev;
1185 sd = &state->sd;
1186
1187 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1188 v4l2_set_subdevdata(sd, state);
1189
1190 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1191 sd->grp_id = CX23885_HW_888_IR;
1192
1193 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1194 if (ret == 0) {
1195
1196
1197
1198
1199
1200 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1201
1202 mutex_init(&state->rx_params_lock);
1203 default_params = default_rx_params;
1204 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1205
1206 mutex_init(&state->tx_params_lock);
1207 default_params = default_tx_params;
1208 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1209 } else {
1210 kfifo_free(&state->rx_kfifo);
1211 }
1212 return ret;
1213}
1214
1215int cx23888_ir_remove(struct cx23885_dev *dev)
1216{
1217 struct v4l2_subdev *sd;
1218 struct cx23888_ir_state *state;
1219
1220 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1221 if (sd == NULL)
1222 return -ENODEV;
1223
1224 cx23888_ir_rx_shutdown(sd);
1225 cx23888_ir_tx_shutdown(sd);
1226
1227 state = to_state(sd);
1228 v4l2_device_unregister_subdev(sd);
1229 kfifo_free(&state->rx_kfifo);
1230 kfree(state);
1231
1232 return 0;
1233}
1234