LXR linux/drivers/media/pci/smipcie/smipcie.h

   1/*
   2 * SMI PCIe driver for DVBSky cards.
   3 *
   4 * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
   5 *
   6 *    This program is free software; you can redistribute it and/or modify
   7 *    it under the terms of the GNU General Public License as published by
   8 *    the Free Software Foundation; either version 2 of the License, or
   9 *    (at your option) any later version.
  10 *
  11 *    This program is distributed in the hope that it will be useful,
  12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 *    GNU General Public License for more details.
  15 */
  16
  17#ifndef _SMI_PCIE_H_
  18#define _SMI_PCIE_H_
  19
  20#include <linux/i2c.h>
  21#include <linux/i2c-algo-bit.h>
  22#include <linux/init.h>
  23#include <linux/interrupt.h>
  24#include <linux/kernel.h>
  25#include <linux/module.h>
  26#include <linux/pci.h>
  27#include <linux/dma-mapping.h>
  28#include <linux/slab.h>
  29#include <media/rc-core.h>
  30
  31#include <media/demux.h>
  32#include <media/dmxdev.h>
  33#include <media/dvb_demux.h>
  34#include <media/dvb_frontend.h>
  35#include <media/dvb_net.h>
  36#include <media/dvbdev.h>
  37
  38/* -------- Register Base -------- */
  39#define    MSI_CONTROL_REG_BASE                 0x0800
  40#define    SYSTEM_CONTROL_REG_BASE              0x0880
  41#define    PCIE_EP_DEBUG_REG_BASE               0x08C0
  42#define    IR_CONTROL_REG_BASE                  0x0900
  43#define    I2C_A_CONTROL_REG_BASE               0x0940
  44#define    I2C_B_CONTROL_REG_BASE               0x0980
  45#define    ATV_PORTA_CONTROL_REG_BASE           0x09C0
  46#define    DTV_PORTA_CONTROL_REG_BASE           0x0A00
  47#define    AES_PORTA_CONTROL_REG_BASE           0x0A80
  48#define    DMA_PORTA_CONTROL_REG_BASE           0x0AC0
  49#define    ATV_PORTB_CONTROL_REG_BASE           0x0B00
  50#define    DTV_PORTB_CONTROL_REG_BASE           0x0B40
  51#define    AES_PORTB_CONTROL_REG_BASE           0x0BC0
  52#define    DMA_PORTB_CONTROL_REG_BASE           0x0C00
  53#define    UART_A_REGISTER_BASE                 0x0C40
  54#define    UART_B_REGISTER_BASE                 0x0C80
  55#define    GPS_CONTROL_REG_BASE                 0x0CC0
  56#define    DMA_PORTC_CONTROL_REG_BASE           0x0D00
  57#define    DMA_PORTD_CONTROL_REG_BASE           0x0D00
  58#define    AES_RANDOM_DATA_BASE                 0x0D80
  59#define    AES_KEY_IN_BASE                      0x0D90
  60#define    RANDOM_DATA_LIB_BASE                 0x0E00
  61#define    IR_DATA_BUFFER_BASE                  0x0F00
  62#define    PORTA_TS_BUFFER_BASE                 0x1000
  63#define    PORTA_I2S_BUFFER_BASE                0x1400
  64#define    PORTB_TS_BUFFER_BASE                 0x1800
  65#define    PORTB_I2S_BUFFER_BASE                0x1C00
  66
  67/* -------- MSI control and state register -------- */
  68#define MSI_DELAY_TIMER             (MSI_CONTROL_REG_BASE + 0x00)
  69#define MSI_INT_STATUS              (MSI_CONTROL_REG_BASE + 0x08)
  70#define MSI_INT_STATUS_CLR          (MSI_CONTROL_REG_BASE + 0x0C)
  71#define MSI_INT_STATUS_SET          (MSI_CONTROL_REG_BASE + 0x10)
  72#define MSI_INT_ENA                 (MSI_CONTROL_REG_BASE + 0x14)
  73#define MSI_INT_ENA_CLR             (MSI_CONTROL_REG_BASE + 0x18)
  74#define MSI_INT_ENA_SET             (MSI_CONTROL_REG_BASE + 0x1C)
  75#define MSI_SOFT_RESET              (MSI_CONTROL_REG_BASE + 0x20)
  76#define MSI_CFG_SRC0                (MSI_CONTROL_REG_BASE + 0x24)
  77
  78/* -------- Hybird Controller System Control register -------- */
  79#define MUX_MODE_CTRL         (SYSTEM_CONTROL_REG_BASE + 0x00)
  80        #define rbPaMSMask        0x07
  81        #define rbPaMSDtvNoGpio   0x00 /*[2:0], DTV Simple mode */
  82        #define rbPaMSDtv4bitGpio 0x01 /*[2:0], DTV TS2 Serial mode)*/
  83        #define rbPaMSDtv7bitGpio 0x02 /*[2:0], DTV TS0 Serial mode*/
  84        #define rbPaMS8bitGpio    0x03 /*[2:0], GPIO mode selected;(8bit GPIO)*/
  85        #define rbPaMSAtv         0x04 /*[2:0], 3'b1xx: ATV mode select*/
  86        #define rbPbMSMask        0x38
  87        #define rbPbMSDtvNoGpio   0x00 /*[5:3], DTV Simple mode */
  88        #define rbPbMSDtv4bitGpio 0x08 /*[5:3], DTV TS2 Serial mode*/
  89        #define rbPbMSDtv7bitGpio 0x10 /*[5:3], DTV TS0 Serial mode*/
  90        #define rbPbMS8bitGpio    0x18 /*[5:3], GPIO mode selected;(8bit GPIO)*/
  91        #define rbPbMSAtv         0x20 /*[5:3], 3'b1xx: ATV mode select*/
  92        #define rbPaAESEN         0x40 /*[6], port A AES enable bit*/
  93        #define rbPbAESEN         0x80 /*[7], port B AES enable bit*/
  94
  95#define INTERNAL_RST                (SYSTEM_CONTROL_REG_BASE + 0x04)
  96#define PERIPHERAL_CTRL             (SYSTEM_CONTROL_REG_BASE + 0x08)
  97#define GPIO_0to7_CTRL              (SYSTEM_CONTROL_REG_BASE + 0x0C)
  98#define GPIO_8to15_CTRL             (SYSTEM_CONTROL_REG_BASE + 0x10)
  99#define GPIO_16to24_CTRL            (SYSTEM_CONTROL_REG_BASE + 0x14)
 100#define GPIO_INT_SRC_CFG            (SYSTEM_CONTROL_REG_BASE + 0x18)
 101#define SYS_BUF_STATUS              (SYSTEM_CONTROL_REG_BASE + 0x1C)
 102#define PCIE_IP_REG_ACS             (SYSTEM_CONTROL_REG_BASE + 0x20)
 103#define PCIE_IP_REG_ACS_ADDR        (SYSTEM_CONTROL_REG_BASE + 0x24)
 104#define PCIE_IP_REG_ACS_DATA        (SYSTEM_CONTROL_REG_BASE + 0x28)
 105
 106/* -------- IR Control register -------- */
 107#define   IR_Init_Reg         (IR_CONTROL_REG_BASE + 0x00)
 108#define   IR_Idle_Cnt_Low     (IR_CONTROL_REG_BASE + 0x04)
 109#define   IR_Idle_Cnt_High    (IR_CONTROL_REG_BASE + 0x05)
 110#define   IR_Unit_Cnt_Low     (IR_CONTROL_REG_BASE + 0x06)
 111#define   IR_Unit_Cnt_High    (IR_CONTROL_REG_BASE + 0x07)
 112#define   IR_Data_Cnt         (IR_CONTROL_REG_BASE + 0x08)
 113#define   rbIRen            0x80
 114#define   rbIRhighidle      0x10
 115#define   rbIRlowidle       0x00
 116#define   rbIRVld           0x04
 117
 118/* -------- I2C A control and state register -------- */
 119#define I2C_A_CTL_STATUS                 (I2C_A_CONTROL_REG_BASE + 0x00)
 120#define I2C_A_ADDR                       (I2C_A_CONTROL_REG_BASE + 0x04)
 121#define I2C_A_SW_CTL                     (I2C_A_CONTROL_REG_BASE + 0x08)
 122#define I2C_A_TIME_OUT_CNT               (I2C_A_CONTROL_REG_BASE + 0x0C)
 123#define I2C_A_FIFO_STATUS                (I2C_A_CONTROL_REG_BASE + 0x10)
 124#define I2C_A_FS_EN                      (I2C_A_CONTROL_REG_BASE + 0x14)
 125#define I2C_A_FIFO_DATA                  (I2C_A_CONTROL_REG_BASE + 0x20)
 126
 127/* -------- I2C B control and state register -------- */
 128#define I2C_B_CTL_STATUS                 (I2C_B_CONTROL_REG_BASE + 0x00)
 129#define I2C_B_ADDR                       (I2C_B_CONTROL_REG_BASE + 0x04)
 130#define I2C_B_SW_CTL                     (I2C_B_CONTROL_REG_BASE + 0x08)
 131#define I2C_B_TIME_OUT_CNT               (I2C_B_CONTROL_REG_BASE + 0x0C)
 132#define I2C_B_FIFO_STATUS                (I2C_B_CONTROL_REG_BASE + 0x10)
 133#define I2C_B_FS_EN                      (I2C_B_CONTROL_REG_BASE + 0x14)
 134#define I2C_B_FIFO_DATA                  (I2C_B_CONTROL_REG_BASE + 0x20)
 135
 136#define VIDEO_CTRL_STATUS_A     (ATV_PORTA_CONTROL_REG_BASE + 0x04)
 137
 138/* -------- Digital TV control register, Port A -------- */
 139#define MPEG2_CTRL_A            (DTV_PORTA_CONTROL_REG_BASE + 0x00)
 140#define SERIAL_IN_ADDR_A        (DTV_PORTA_CONTROL_REG_BASE + 0x4C)
 141#define VLD_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x60)
 142#define ERR_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x64)
 143#define BRD_CNT_ADDR_A          (DTV_PORTA_CONTROL_REG_BASE + 0x68)
 144
 145/* -------- DMA Control Register, Port A  -------- */
 146#define DMA_PORTA_CHAN0_ADDR_LOW        (DMA_PORTA_CONTROL_REG_BASE + 0x00)
 147#define DMA_PORTA_CHAN0_ADDR_HI         (DMA_PORTA_CONTROL_REG_BASE + 0x04)
 148#define DMA_PORTA_CHAN0_TRANS_STATE     (DMA_PORTA_CONTROL_REG_BASE + 0x08)
 149#define DMA_PORTA_CHAN0_CONTROL         (DMA_PORTA_CONTROL_REG_BASE + 0x0C)
 150#define DMA_PORTA_CHAN1_ADDR_LOW        (DMA_PORTA_CONTROL_REG_BASE + 0x10)
 151#define DMA_PORTA_CHAN1_ADDR_HI         (DMA_PORTA_CONTROL_REG_BASE + 0x14)
 152#define DMA_PORTA_CHAN1_TRANS_STATE     (DMA_PORTA_CONTROL_REG_BASE + 0x18)
 153#define DMA_PORTA_CHAN1_CONTROL         (DMA_PORTA_CONTROL_REG_BASE + 0x1C)
 154#define DMA_PORTA_MANAGEMENT            (DMA_PORTA_CONTROL_REG_BASE + 0x20)
 155#define VIDEO_CTRL_STATUS_B             (ATV_PORTB_CONTROL_REG_BASE + 0x04)
 156
 157/* -------- Digital TV control register, Port B -------- */
 158#define MPEG2_CTRL_B            (DTV_PORTB_CONTROL_REG_BASE + 0x00)
 159#define SERIAL_IN_ADDR_B        (DTV_PORTB_CONTROL_REG_BASE + 0x4C)
 160#define VLD_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x60)
 161#define ERR_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x64)
 162#define BRD_CNT_ADDR_B          (DTV_PORTB_CONTROL_REG_BASE + 0x68)
 163
 164/* -------- AES control register, Port B -------- */
 165#define AES_CTRL_B              (AES_PORTB_CONTROL_REG_BASE + 0x00)
 166#define AES_KEY_BASE_B  (AES_PORTB_CONTROL_REG_BASE + 0x04)
 167
 168/* -------- DMA Control Register, Port B  -------- */
 169#define DMA_PORTB_CHAN0_ADDR_LOW        (DMA_PORTB_CONTROL_REG_BASE + 0x00)
 170#define DMA_PORTB_CHAN0_ADDR_HI         (DMA_PORTB_CONTROL_REG_BASE + 0x04)
 171#define DMA_PORTB_CHAN0_TRANS_STATE     (DMA_PORTB_CONTROL_REG_BASE + 0x08)
 172#define DMA_PORTB_CHAN0_CONTROL         (DMA_PORTB_CONTROL_REG_BASE + 0x0C)
 173#define DMA_PORTB_CHAN1_ADDR_LOW        (DMA_PORTB_CONTROL_REG_BASE + 0x10)
 174#define DMA_PORTB_CHAN1_ADDR_HI         (DMA_PORTB_CONTROL_REG_BASE + 0x14)
 175#define DMA_PORTB_CHAN1_TRANS_STATE     (DMA_PORTB_CONTROL_REG_BASE + 0x18)
 176#define DMA_PORTB_CHAN1_CONTROL         (DMA_PORTB_CONTROL_REG_BASE + 0x1C)
 177#define DMA_PORTB_MANAGEMENT            (DMA_PORTB_CONTROL_REG_BASE + 0x20)
 178
 179#define DMA_TRANS_UNIT_188 (0x00000007)
 180
 181/* -------- Macro define of 24 interrupt resource --------*/
 182#define DMA_A_CHAN0_DONE_INT   (0x00000001)
 183#define DMA_A_CHAN1_DONE_INT   (0x00000002)
 184#define DMA_B_CHAN0_DONE_INT   (0x00000004)
 185#define DMA_B_CHAN1_DONE_INT   (0x00000008)
 186#define DMA_C_CHAN0_DONE_INT   (0x00000010)
 187#define DMA_C_CHAN1_DONE_INT   (0x00000020)
 188#define DMA_D_CHAN0_DONE_INT   (0x00000040)
 189#define DMA_D_CHAN1_DONE_INT   (0x00000080)
 190#define DATA_BUF_OVERFLOW_INT  (0x00000100)
 191#define UART_0_X_INT           (0x00000200)
 192#define UART_1_X_INT           (0x00000400)
 193#define IR_X_INT               (0x00000800)
 194#define GPIO_0_INT             (0x00001000)
 195#define GPIO_1_INT             (0x00002000)
 196#define GPIO_2_INT             (0x00004000)
 197#define GPIO_3_INT             (0x00008000)
 198#define ALL_INT                (0x0000FFFF)
 199
 200/* software I2C bit mask */
 201#define SW_I2C_MSK_MODE         0x01
 202#define SW_I2C_MSK_CLK_OUT      0x02
 203#define SW_I2C_MSK_DAT_OUT      0x04
 204#define SW_I2C_MSK_CLK_EN       0x08
 205#define SW_I2C_MSK_DAT_EN       0x10
 206#define SW_I2C_MSK_DAT_IN       0x40
 207#define SW_I2C_MSK_CLK_IN       0x80
 208
 209#define SMI_VID         0x1ADE
 210#define SMI_PID         0x3038
 211#define SMI_TS_DMA_BUF_SIZE     (1024 * 188)
 212
 213struct smi_cfg_info {
 214#define SMI_DVBSKY_S952         0
 215#define SMI_DVBSKY_S950         1
 216#define SMI_DVBSKY_T9580        2
 217#define SMI_DVBSKY_T982         3
 218#define SMI_TECHNOTREND_S2_4200 4
 219        int type;
 220        char *name;
 221#define SMI_TS_NULL             0
 222#define SMI_TS_DMA_SINGLE       1
 223#define SMI_TS_DMA_BOTH         3
 224/* SMI_TS_NULL: not use;
 225 * SMI_TS_DMA_SINGLE: use DMA 0 only;
 226 * SMI_TS_DMA_BOTH:use DMA 0 and 1.*/
 227        int ts_0;
 228        int ts_1;
 229#define DVBSKY_FE_NULL          0
 230#define DVBSKY_FE_M88RS6000     1
 231#define DVBSKY_FE_M88DS3103     2
 232#define DVBSKY_FE_SIT2          3
 233        int fe_0;
 234        int fe_1;
 235        char *rc_map;
 236};
 237
 238struct smi_rc {
 239        struct smi_dev *dev;
 240        struct rc_dev *rc_dev;
 241        char input_phys[64];
 242        char device_name[64];
 243        struct work_struct work;
 244        u8 irData[256];
 245
 246        int users;
 247};
 248
 249struct smi_port {
 250        struct smi_dev *dev;
 251        int idx;
 252        int enable;
 253        int fe_type;
 254        /* regs */
 255        u32 DMA_CHAN0_ADDR_LOW;
 256        u32 DMA_CHAN0_ADDR_HI;
 257        u32 DMA_CHAN0_TRANS_STATE;
 258        u32 DMA_CHAN0_CONTROL;
 259        u32 DMA_CHAN1_ADDR_LOW;
 260        u32 DMA_CHAN1_ADDR_HI;
 261        u32 DMA_CHAN1_TRANS_STATE;
 262        u32 DMA_CHAN1_CONTROL;
 263        u32 DMA_MANAGEMENT;
 264        /* dma */
 265        dma_addr_t dma_addr[2];
 266        u8 *cpu_addr[2];
 267        u32 _dmaInterruptCH0;
 268        u32 _dmaInterruptCH1;
 269        u32 _int_status;
 270        struct tasklet_struct tasklet;
 271        /* dvb */
 272        struct dmx_frontend hw_frontend;
 273        struct dmx_frontend mem_frontend;
 274        struct dmxdev dmxdev;
 275        struct dvb_adapter dvb_adapter;
 276        struct dvb_demux demux;
 277        struct dvb_net dvbnet;
 278        int users;
 279        struct dvb_frontend *fe;
 280        /* frontend i2c module */
 281        struct i2c_client *i2c_client_demod;
 282        struct i2c_client *i2c_client_tuner;
 283};
 284
 285struct smi_dev {
 286        int nr;
 287        struct smi_cfg_info *info;
 288
 289        /* pcie */
 290        struct pci_dev *pci_dev;
 291        u32 __iomem *lmmio;
 292
 293        /* ts port */
 294        struct smi_port ts_port[2];
 295
 296        /* i2c */
 297        struct i2c_adapter i2c_bus[2];
 298        struct i2c_algo_bit_data i2c_bit[2];
 299
 300        /* ir */
 301        struct smi_rc ir;
 302};
 303
 304#define smi_read(reg)             readl(dev->lmmio + ((reg)>>2))
 305#define smi_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))
 306
 307#define smi_andor(reg, mask, value) \
 308        writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
 309        ((value) & (mask)), dev->lmmio+((reg)>>2))
 310
 311#define smi_set(reg, bit)          smi_andor((reg), (bit), (bit))
 312#define smi_clear(reg, bit)        smi_andor((reg), (bit), 0)
 313
 314int smi_ir_irq(struct smi_rc *ir, u32 int_status);
 315void smi_ir_start(struct smi_rc *ir);
 316void smi_ir_exit(struct smi_dev *dev);
 317int smi_ir_init(struct smi_dev *dev);
 318
 319#endif /* #ifndef _SMI_PCIE_H_ */
 320