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14#ifndef _DW_MMC_H_
15#define _DW_MMC_H_
16
17#include <linux/scatterlist.h>
18#include <linux/mmc/core.h>
19#include <linux/dmaengine.h>
20#include <linux/reset.h>
21#include <linux/interrupt.h>
22
23enum dw_mci_state {
24 STATE_IDLE = 0,
25 STATE_SENDING_CMD,
26 STATE_SENDING_DATA,
27 STATE_DATA_BUSY,
28 STATE_SENDING_STOP,
29 STATE_DATA_ERROR,
30 STATE_SENDING_CMD11,
31 STATE_WAITING_CMD11_DONE,
32};
33
34enum {
35 EVENT_CMD_COMPLETE = 0,
36 EVENT_XFER_COMPLETE,
37 EVENT_DATA_COMPLETE,
38 EVENT_DATA_ERROR,
39};
40
41enum dw_mci_cookie {
42 COOKIE_UNMAPPED,
43 COOKIE_PRE_MAPPED,
44 COOKIE_MAPPED,
45};
46
47struct mmc_data;
48
49enum {
50 TRANS_MODE_PIO = 0,
51 TRANS_MODE_IDMAC,
52 TRANS_MODE_EDMAC
53};
54
55struct dw_mci_dma_slave {
56 struct dma_chan *ch;
57 enum dma_transfer_direction direction;
58};
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159struct dw_mci {
160 spinlock_t lock;
161 spinlock_t irq_lock;
162 void __iomem *regs;
163 void __iomem *fifo_reg;
164 u32 data_addr_override;
165 bool wm_aligned;
166
167 struct scatterlist *sg;
168 struct sg_mapping_iter sg_miter;
169
170 struct mmc_request *mrq;
171 struct mmc_command *cmd;
172 struct mmc_data *data;
173 struct mmc_command stop_abort;
174 unsigned int prev_blksz;
175 unsigned char timing;
176
177
178 int use_dma;
179 int using_dma;
180 int dma_64bit_address;
181
182 dma_addr_t sg_dma;
183 void *sg_cpu;
184 const struct dw_mci_dma_ops *dma_ops;
185
186 unsigned int ring_size;
187
188
189 struct dw_mci_dma_slave *dms;
190
191 resource_size_t phy_regs;
192
193 u32 cmd_status;
194 u32 data_status;
195 u32 stop_cmdr;
196 u32 dir_status;
197 struct tasklet_struct tasklet;
198 unsigned long pending_events;
199 unsigned long completed_events;
200 enum dw_mci_state state;
201 struct list_head queue;
202
203 u32 bus_hz;
204 u32 current_speed;
205 u32 fifoth_val;
206 u16 verid;
207 struct device *dev;
208 struct dw_mci_board *pdata;
209 const struct dw_mci_drv_data *drv_data;
210 void *priv;
211 struct clk *biu_clk;
212 struct clk *ciu_clk;
213 struct dw_mci_slot *slot;
214
215
216 int fifo_depth;
217 int data_shift;
218 u8 part_buf_start;
219 u8 part_buf_count;
220 union {
221 u16 part_buf16;
222 u32 part_buf32;
223 u64 part_buf;
224 };
225 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
226 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
227
228 bool vqmmc_enabled;
229 unsigned long irq_flags;
230 int irq;
231
232 int sdio_id0;
233
234 struct timer_list cmd11_timer;
235 struct timer_list cto_timer;
236 struct timer_list dto_timer;
237};
238
239
240struct dw_mci_dma_ops {
241
242 int (*init)(struct dw_mci *host);
243 int (*start)(struct dw_mci *host, unsigned int sg_len);
244 void (*complete)(void *host);
245 void (*stop)(struct dw_mci *host);
246 void (*cleanup)(struct dw_mci *host);
247 void (*exit)(struct dw_mci *host);
248};
249
250struct dma_pdata;
251
252
253struct dw_mci_board {
254 unsigned int bus_hz;
255
256 u32 caps;
257 u32 caps2;
258 u32 pm_caps;
259
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263
264 unsigned int fifo_depth;
265
266
267 u32 detect_delay_ms;
268
269 struct reset_control *rstc;
270 struct dw_mci_dma_ops *dma_ops;
271 struct dma_pdata *data;
272};
273
274#define DW_MMC_240A 0x240a
275#define DW_MMC_280A 0x280a
276
277#define SDMMC_CTRL 0x000
278#define SDMMC_PWREN 0x004
279#define SDMMC_CLKDIV 0x008
280#define SDMMC_CLKSRC 0x00c
281#define SDMMC_CLKENA 0x010
282#define SDMMC_TMOUT 0x014
283#define SDMMC_CTYPE 0x018
284#define SDMMC_BLKSIZ 0x01c
285#define SDMMC_BYTCNT 0x020
286#define SDMMC_INTMASK 0x024
287#define SDMMC_CMDARG 0x028
288#define SDMMC_CMD 0x02c
289#define SDMMC_RESP0 0x030
290#define SDMMC_RESP1 0x034
291#define SDMMC_RESP2 0x038
292#define SDMMC_RESP3 0x03c
293#define SDMMC_MINTSTS 0x040
294#define SDMMC_RINTSTS 0x044
295#define SDMMC_STATUS 0x048
296#define SDMMC_FIFOTH 0x04c
297#define SDMMC_CDETECT 0x050
298#define SDMMC_WRTPRT 0x054
299#define SDMMC_GPIO 0x058
300#define SDMMC_TCBCNT 0x05c
301#define SDMMC_TBBCNT 0x060
302#define SDMMC_DEBNCE 0x064
303#define SDMMC_USRID 0x068
304#define SDMMC_VERID 0x06c
305#define SDMMC_HCON 0x070
306#define SDMMC_UHS_REG 0x074
307#define SDMMC_RST_N 0x078
308#define SDMMC_BMOD 0x080
309#define SDMMC_PLDMND 0x084
310#define SDMMC_DBADDR 0x088
311#define SDMMC_IDSTS 0x08c
312#define SDMMC_IDINTEN 0x090
313#define SDMMC_DSCADDR 0x094
314#define SDMMC_BUFADDR 0x098
315#define SDMMC_CDTHRCTL 0x100
316#define SDMMC_UHS_REG_EXT 0x108
317#define SDMMC_DDR_REG 0x10c
318#define SDMMC_ENABLE_SHIFT 0x110
319#define SDMMC_DATA(x) (x)
320
321
322
323#define SDMMC_DBADDRL 0x088
324#define SDMMC_DBADDRU 0x08c
325#define SDMMC_IDSTS64 0x090
326#define SDMMC_IDINTEN64 0x094
327#define SDMMC_DSCADDRL 0x098
328#define SDMMC_DSCADDRU 0x09c
329#define SDMMC_BUFADDRL 0x0A0
330#define SDMMC_BUFADDRU 0x0A4
331
332
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334
335
336#define DATA_OFFSET 0x100
337#define DATA_240A_OFFSET 0x200
338
339
340#define _SBF(f, v) ((v) << (f))
341
342
343#define SDMMC_CTRL_USE_IDMAC BIT(25)
344#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
345#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
346#define SDMMC_CTRL_SEND_CCSD BIT(9)
347#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
348#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
349#define SDMMC_CTRL_READ_WAIT BIT(6)
350#define SDMMC_CTRL_DMA_ENABLE BIT(5)
351#define SDMMC_CTRL_INT_ENABLE BIT(4)
352#define SDMMC_CTRL_DMA_RESET BIT(2)
353#define SDMMC_CTRL_FIFO_RESET BIT(1)
354#define SDMMC_CTRL_RESET BIT(0)
355
356#define SDMMC_CLKEN_LOW_PWR BIT(16)
357#define SDMMC_CLKEN_ENABLE BIT(0)
358
359#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
360#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
361#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
362#define SDMMC_TMOUT_RESP_MSK 0xFF
363
364#define SDMMC_CTYPE_8BIT BIT(16)
365#define SDMMC_CTYPE_4BIT BIT(0)
366#define SDMMC_CTYPE_1BIT 0
367
368#define SDMMC_INT_SDIO(n) BIT(16 + (n))
369#define SDMMC_INT_EBE BIT(15)
370#define SDMMC_INT_ACD BIT(14)
371#define SDMMC_INT_SBE BIT(13)
372#define SDMMC_INT_HLE BIT(12)
373#define SDMMC_INT_FRUN BIT(11)
374#define SDMMC_INT_HTO BIT(10)
375#define SDMMC_INT_VOLT_SWITCH BIT(10)
376#define SDMMC_INT_DRTO BIT(9)
377#define SDMMC_INT_RTO BIT(8)
378#define SDMMC_INT_DCRC BIT(7)
379#define SDMMC_INT_RCRC BIT(6)
380#define SDMMC_INT_RXDR BIT(5)
381#define SDMMC_INT_TXDR BIT(4)
382#define SDMMC_INT_DATA_OVER BIT(3)
383#define SDMMC_INT_CMD_DONE BIT(2)
384#define SDMMC_INT_RESP_ERR BIT(1)
385#define SDMMC_INT_CD BIT(0)
386#define SDMMC_INT_ERROR 0xbfc2
387
388#define SDMMC_CMD_START BIT(31)
389#define SDMMC_CMD_USE_HOLD_REG BIT(29)
390#define SDMMC_CMD_VOLT_SWITCH BIT(28)
391#define SDMMC_CMD_CCS_EXP BIT(23)
392#define SDMMC_CMD_CEATA_RD BIT(22)
393#define SDMMC_CMD_UPD_CLK BIT(21)
394#define SDMMC_CMD_INIT BIT(15)
395#define SDMMC_CMD_STOP BIT(14)
396#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
397#define SDMMC_CMD_SEND_STOP BIT(12)
398#define SDMMC_CMD_STRM_MODE BIT(11)
399#define SDMMC_CMD_DAT_WR BIT(10)
400#define SDMMC_CMD_DAT_EXP BIT(9)
401#define SDMMC_CMD_RESP_CRC BIT(8)
402#define SDMMC_CMD_RESP_LONG BIT(7)
403#define SDMMC_CMD_RESP_EXP BIT(6)
404#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
405
406#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
407#define SDMMC_STATUS_DMA_REQ BIT(31)
408#define SDMMC_STATUS_BUSY BIT(9)
409
410#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
411 ((r) & 0xFFF) << 16 | \
412 ((t) & 0xFFF))
413
414#define DMA_INTERFACE_IDMA (0x0)
415#define DMA_INTERFACE_DWDMA (0x1)
416#define DMA_INTERFACE_GDMA (0x2)
417#define DMA_INTERFACE_NODMA (0x3)
418#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
419#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
420#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
421#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
422
423#define SDMMC_IDMAC_INT_AI BIT(9)
424#define SDMMC_IDMAC_INT_NI BIT(8)
425#define SDMMC_IDMAC_INT_CES BIT(5)
426#define SDMMC_IDMAC_INT_DU BIT(4)
427#define SDMMC_IDMAC_INT_FBE BIT(2)
428#define SDMMC_IDMAC_INT_RI BIT(1)
429#define SDMMC_IDMAC_INT_TI BIT(0)
430
431#define SDMMC_IDMAC_ENABLE BIT(7)
432#define SDMMC_IDMAC_FB BIT(1)
433#define SDMMC_IDMAC_SWRESET BIT(0)
434
435#define SDMMC_RST_HWACTIVE 0x1
436
437#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
438
439#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
440#define SDMMC_CARD_WR_THR_EN BIT(2)
441#define SDMMC_CARD_RD_THR_EN BIT(0)
442
443#define SDMMC_UHS_DDR BIT(16)
444#define SDMMC_UHS_18V BIT(0)
445
446#define SDMMC_DDR_HS400 BIT(31)
447
448#define SDMMC_ENABLE_PHASE BIT(0)
449
450#define SDMMC_CTRL_ALL_RESET_FLAGS \
451 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
452
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455
456#define mci_fifo_readw(__reg) __raw_readw(__reg)
457#define mci_fifo_readl(__reg) __raw_readl(__reg)
458#define mci_fifo_readq(__reg) __raw_readq(__reg)
459
460#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
461#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
462#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
463
464
465#define mci_readl(dev, reg) \
466 readl_relaxed((dev)->regs + SDMMC_##reg)
467#define mci_writel(dev, reg, value) \
468 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
469
470
471#define mci_readw(dev, reg) \
472 readw_relaxed((dev)->regs + SDMMC_##reg)
473#define mci_writew(dev, reg, value) \
474 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
475
476
477#ifdef readq
478#define mci_readq(dev, reg) \
479 readq_relaxed((dev)->regs + SDMMC_##reg)
480#define mci_writeq(dev, reg, value) \
481 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
482#else
483
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491#define mci_readq(dev, reg) \
492 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
493#define mci_writeq(dev, reg, value) \
494 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
495
496#define __raw_writeq(__value, __reg) \
497 (*(volatile u64 __force *)(__reg) = (__value))
498#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
499#endif
500
501extern int dw_mci_probe(struct dw_mci *host);
502extern void dw_mci_remove(struct dw_mci *host);
503#ifdef CONFIG_PM
504extern int dw_mci_runtime_suspend(struct device *device);
505extern int dw_mci_runtime_resume(struct device *device);
506#endif
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524struct dw_mci_slot {
525 struct mmc_host *mmc;
526 struct dw_mci *host;
527
528 u32 ctype;
529
530 struct mmc_request *mrq;
531 struct list_head queue_node;
532
533 unsigned int clock;
534 unsigned int __clk_old;
535
536 unsigned long flags;
537#define DW_MMC_CARD_PRESENT 0
538#define DW_MMC_CARD_NEED_INIT 1
539#define DW_MMC_CARD_NO_LOW_PWR 2
540#define DW_MMC_CARD_NO_USE_HOLD 3
541#define DW_MMC_CARD_NEEDS_POLL 4
542 int id;
543 int sdio_id;
544};
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559struct dw_mci_drv_data {
560 unsigned long *caps;
561 u32 num_caps;
562 int (*init)(struct dw_mci *host);
563 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
564 int (*parse_dt)(struct dw_mci *host);
565 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
566 int (*prepare_hs400_tuning)(struct dw_mci *host,
567 struct mmc_ios *ios);
568 int (*switch_voltage)(struct mmc_host *mmc,
569 struct mmc_ios *ios);
570};
571#endif
572