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20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/mmc/card.h>
28#include <linux/mmc/host.h>
29#include <linux/platform_data/pxa_sdhci.h>
30#include <linux/slab.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33
34#include "sdhci.h"
35#include "sdhci-pltfm.h"
36
37#define SD_FIFO_PARAM 0xe0
38#define DIS_PAD_SD_CLK_GATE 0x0400
39#define CLK_GATE_ON 0x0200
40#define CLK_GATE_CTL 0x0100
41#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
42 CLK_GATE_ON | CLK_GATE_CTL)
43
44#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
45#define SDCLK_SEL_SHIFT 8
46#define SDCLK_SEL_MASK 0x3
47#define SDCLK_DELAY_SHIFT 10
48#define SDCLK_DELAY_MASK 0x3c
49
50#define SD_CE_ATA_2 0xea
51#define MMC_CARD 0x1000
52#define MMC_WIDTH 0x0100
53
54static void pxav2_reset(struct sdhci_host *host, u8 mask)
55{
56 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
57 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
58
59 sdhci_reset(host, mask);
60
61 if (mask == SDHCI_RESET_ALL) {
62 u16 tmp = 0;
63
64
65
66
67
68 if (pdata && pdata->clk_delay_sel == 1) {
69 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
70
71 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
72 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
73 << SDCLK_DELAY_SHIFT;
74 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
75 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
76
77 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
78 }
79
80 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
81 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
82 tmp &= ~CLK_GATE_SETTING_BITS;
83 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
84 } else {
85 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
86 tmp &= ~CLK_GATE_SETTING_BITS;
87 tmp |= CLK_GATE_SETTING_BITS;
88 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
89 }
90 }
91}
92
93static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
94{
95 u8 ctrl;
96 u16 tmp;
97
98 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
99 tmp = readw(host->ioaddr + SD_CE_ATA_2);
100 if (width == MMC_BUS_WIDTH_8) {
101 ctrl &= ~SDHCI_CTRL_4BITBUS;
102 tmp |= MMC_CARD | MMC_WIDTH;
103 } else {
104 tmp &= ~(MMC_CARD | MMC_WIDTH);
105 if (width == MMC_BUS_WIDTH_4)
106 ctrl |= SDHCI_CTRL_4BITBUS;
107 else
108 ctrl &= ~SDHCI_CTRL_4BITBUS;
109 }
110 writew(tmp, host->ioaddr + SD_CE_ATA_2);
111 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
112}
113
114static const struct sdhci_ops pxav2_sdhci_ops = {
115 .set_clock = sdhci_set_clock,
116 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
117 .set_bus_width = pxav2_mmc_set_bus_width,
118 .reset = pxav2_reset,
119 .set_uhs_signaling = sdhci_set_uhs_signaling,
120};
121
122#ifdef CONFIG_OF
123static const struct of_device_id sdhci_pxav2_of_match[] = {
124 {
125 .compatible = "mrvl,pxav2-mmc",
126 },
127 {},
128};
129MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
130
131static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
132{
133 struct sdhci_pxa_platdata *pdata;
134 struct device_node *np = dev->of_node;
135 u32 bus_width;
136 u32 clk_delay_cycles;
137
138 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
139 if (!pdata)
140 return NULL;
141
142 if (of_find_property(np, "non-removable", NULL))
143 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
144
145 of_property_read_u32(np, "bus-width", &bus_width);
146 if (bus_width == 8)
147 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
148
149 of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
150 if (clk_delay_cycles > 0) {
151 pdata->clk_delay_sel = 1;
152 pdata->clk_delay_cycles = clk_delay_cycles;
153 }
154
155 return pdata;
156}
157#else
158static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
159{
160 return NULL;
161}
162#endif
163
164static int sdhci_pxav2_probe(struct platform_device *pdev)
165{
166 struct sdhci_pltfm_host *pltfm_host;
167 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
168 struct device *dev = &pdev->dev;
169 struct sdhci_host *host = NULL;
170 const struct of_device_id *match;
171
172 int ret;
173 struct clk *clk;
174
175 host = sdhci_pltfm_init(pdev, NULL, 0);
176 if (IS_ERR(host))
177 return PTR_ERR(host);
178
179 pltfm_host = sdhci_priv(host);
180
181 clk = devm_clk_get(dev, "PXA-SDHCLK");
182 if (IS_ERR(clk)) {
183 dev_err(dev, "failed to get io clock\n");
184 ret = PTR_ERR(clk);
185 goto free;
186 }
187 pltfm_host->clk = clk;
188 ret = clk_prepare_enable(clk);
189 if (ret) {
190 dev_err(&pdev->dev, "failed to enable io clock\n");
191 goto free;
192 }
193
194 host->quirks = SDHCI_QUIRK_BROKEN_ADMA
195 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
196 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
197
198 match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
199 if (match) {
200 pdata = pxav2_get_mmc_pdata(dev);
201 }
202 if (pdata) {
203 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
204
205 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
206 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
207 }
208
209
210 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
211 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
212
213 if (pdata->quirks)
214 host->quirks |= pdata->quirks;
215 if (pdata->host_caps)
216 host->mmc->caps |= pdata->host_caps;
217 if (pdata->pm_caps)
218 host->mmc->pm_caps |= pdata->pm_caps;
219 }
220
221 host->ops = &pxav2_sdhci_ops;
222
223 ret = sdhci_add_host(host);
224 if (ret)
225 goto disable_clk;
226
227 return 0;
228
229disable_clk:
230 clk_disable_unprepare(clk);
231free:
232 sdhci_pltfm_free(pdev);
233 return ret;
234}
235
236static struct platform_driver sdhci_pxav2_driver = {
237 .driver = {
238 .name = "sdhci-pxav2",
239 .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
240 .pm = &sdhci_pltfm_pmops,
241 },
242 .probe = sdhci_pxav2_probe,
243 .remove = sdhci_pltfm_unregister,
244};
245
246module_platform_driver(sdhci_pxav2_driver);
247
248MODULE_DESCRIPTION("SDHCI driver for pxav2");
249MODULE_AUTHOR("Marvell International Ltd.");
250MODULE_LICENSE("GPL v2");
251
252
