LXR linux/drivers/mtd/nand/raw/lpc32xx

   1/*
   2 * NXP LPC32XX NAND SLC driver
   3 *
   4 * Authors:
   5 *    Kevin Wells <kevin.wells@nxp.com>
   6 *    Roland Stigge <stigge@antcom.de>
   7 *
   8 * Copyright © 2011 NXP Semiconductors
   9 * Copyright © 2012 Roland Stigge
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 */
  21
  22#include <linux/slab.h>
  23#include <linux/module.h>
  24#include <linux/platform_device.h>
  25#include <linux/mtd/mtd.h>
  26#include <linux/mtd/rawnand.h>
  27#include <linux/mtd/partitions.h>
  28#include <linux/clk.h>
  29#include <linux/err.h>
  30#include <linux/delay.h>
  31#include <linux/io.h>
  32#include <linux/mm.h>
  33#include <linux/dma-mapping.h>
  34#include <linux/dmaengine.h>
  35#include <linux/mtd/nand_ecc.h>
  36#include <linux/gpio.h>
  37#include <linux/of.h>
  38#include <linux/of_gpio.h>
  39#include <linux/mtd/lpc32xx_slc.h>
  40
  41#define LPC32XX_MODNAME         "lpc32xx-nand"
  42
  43/**********************************************************************
  44* SLC NAND controller register offsets
  45**********************************************************************/
  46
  47#define SLC_DATA(x)             (x + 0x000)
  48#define SLC_ADDR(x)             (x + 0x004)
  49#define SLC_CMD(x)              (x + 0x008)
  50#define SLC_STOP(x)             (x + 0x00C)
  51#define SLC_CTRL(x)             (x + 0x010)
  52#define SLC_CFG(x)              (x + 0x014)
  53#define SLC_STAT(x)             (x + 0x018)
  54#define SLC_INT_STAT(x)         (x + 0x01C)
  55#define SLC_IEN(x)              (x + 0x020)
  56#define SLC_ISR(x)              (x + 0x024)
  57#define SLC_ICR(x)              (x + 0x028)
  58#define SLC_TAC(x)              (x + 0x02C)
  59#define SLC_TC(x)               (x + 0x030)
  60#define SLC_ECC(x)              (x + 0x034)
  61#define SLC_DMA_DATA(x)         (x + 0x038)
  62
  63/**********************************************************************
  64* slc_ctrl register definitions
  65**********************************************************************/
  66#define SLCCTRL_SW_RESET        (1 << 2) /* Reset the NAND controller bit */
  67#define SLCCTRL_ECC_CLEAR       (1 << 1) /* Reset ECC bit */
  68#define SLCCTRL_DMA_START       (1 << 0) /* Start DMA channel bit */
  69
  70/**********************************************************************
  71* slc_cfg register definitions
  72**********************************************************************/
  73#define SLCCFG_CE_LOW           (1 << 5) /* Force CE low bit */
  74#define SLCCFG_DMA_ECC          (1 << 4) /* Enable DMA ECC bit */
  75#define SLCCFG_ECC_EN           (1 << 3) /* ECC enable bit */
  76#define SLCCFG_DMA_BURST        (1 << 2) /* DMA burst bit */
  77#define SLCCFG_DMA_DIR          (1 << 1) /* DMA write(0)/read(1) bit */
  78#define SLCCFG_WIDTH            (1 << 0) /* External device width, 0=8bit */
  79
  80/**********************************************************************
  81* slc_stat register definitions
  82**********************************************************************/
  83#define SLCSTAT_DMA_FIFO        (1 << 2) /* DMA FIFO has data bit */
  84#define SLCSTAT_SLC_FIFO        (1 << 1) /* SLC FIFO has data bit */
  85#define SLCSTAT_NAND_READY      (1 << 0) /* NAND device is ready bit */
  86
  87/**********************************************************************
  88* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
  89**********************************************************************/
  90#define SLCSTAT_INT_TC          (1 << 1) /* Transfer count bit */
  91#define SLCSTAT_INT_RDY_EN      (1 << 0) /* Ready interrupt bit */
  92
  93/**********************************************************************
  94* slc_tac register definitions
  95**********************************************************************/
  96/* Computation of clock cycles on basis of controller and device clock rates */
  97#define SLCTAC_CLOCKS(c, n, s)  (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
  98
  99/* Clock setting for RDY write sample wait time in 2*n clocks */
 100#define SLCTAC_WDR(n)           (((n) & 0xF) << 28)
 101/* Write pulse width in clock cycles, 1 to 16 clocks */
 102#define SLCTAC_WWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 24))
 103/* Write hold time of control and data signals, 1 to 16 clocks */
 104#define SLCTAC_WHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 20))
 105/* Write setup time of control and data signals, 1 to 16 clocks */
 106#define SLCTAC_WSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 16))
 107/* Clock setting for RDY read sample wait time in 2*n clocks */
 108#define SLCTAC_RDR(n)           (((n) & 0xF) << 12)
 109/* Read pulse width in clock cycles, 1 to 16 clocks */
 110#define SLCTAC_RWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 8))
 111/* Read hold time of control and data signals, 1 to 16 clocks */
 112#define SLCTAC_RHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 4))
 113/* Read setup time of control and data signals, 1 to 16 clocks */
 114#define SLCTAC_RSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 0))
 115
 116/**********************************************************************
 117* slc_ecc register definitions
 118**********************************************************************/
 119/* ECC line party fetch macro */
 120#define SLCECC_TO_LINEPAR(n)    (((n) >> 6) & 0x7FFF)
 121#define SLCECC_TO_COLPAR(n)     ((n) & 0x3F)
 122
 123/*
 124 * DMA requires storage space for the DMA local buffer and the hardware ECC
 125 * storage area. The DMA local buffer is only used if DMA mapping fails
 126 * during runtime.
 127 */
 128#define LPC32XX_DMA_DATA_SIZE           4096
 129#define LPC32XX_ECC_SAVE_SIZE           ((4096 / 256) * 4)
 130
 131/* Number of bytes used for ECC stored in NAND per 256 bytes */
 132#define LPC32XX_SLC_DEV_ECC_BYTES       3
 133
 134/*
 135 * If the NAND base clock frequency can't be fetched, this frequency will be
 136 * used instead as the base. This rate is used to setup the timing registers
 137 * used for NAND accesses.
 138 */
 139#define LPC32XX_DEF_BUS_RATE            133250000
 140
 141/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
 142#define LPC32XX_DMA_TIMEOUT             100
 143
 144/*
 145 * NAND ECC Layout for small page NAND devices
 146 * Note: For large and huge page devices, the default layouts are used
 147 */
 148static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
 149                                 struct mtd_oob_region *oobregion)
 150{
 151        if (section)
 152                return -ERANGE;
 153
 154        oobregion->length = 6;
 155        oobregion->offset = 10;
 156
 157        return 0;
 158}
 159
 160static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
 161                                  struct mtd_oob_region *oobregion)
 162{
 163        if (section > 1)
 164                return -ERANGE;
 165
 166        if (!section) {
 167                oobregion->offset = 0;
 168                oobregion->length = 4;
 169        } else {
 170                oobregion->offset = 6;
 171                oobregion->length = 4;
 172        }
 173
 174        return 0;
 175}
 176
 177static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
 178        .ecc = lpc32xx_ooblayout_ecc,
 179        .free = lpc32xx_ooblayout_free,
 180};
 181
 182static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 183static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 184
 185/*
 186 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
 187 * Note: Large page devices used the default layout
 188 */
 189static struct nand_bbt_descr bbt_smallpage_main_descr = {
 190        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 191                | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 192        .offs = 0,
 193        .len = 4,
 194        .veroffs = 6,
 195        .maxblocks = 4,
 196        .pattern = bbt_pattern
 197};
 198
 199static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
 200        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 201                | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 202        .offs = 0,
 203        .len = 4,
 204        .veroffs = 6,
 205        .maxblocks = 4,
 206        .pattern = mirror_pattern
 207};
 208
 209/*
 210 * NAND platform configuration structure
 211 */
 212struct lpc32xx_nand_cfg_slc {
 213        uint32_t wdr_clks;
 214        uint32_t wwidth;
 215        uint32_t whold;
 216        uint32_t wsetup;
 217        uint32_t rdr_clks;
 218        uint32_t rwidth;
 219        uint32_t rhold;
 220        uint32_t rsetup;
 221        int wp_gpio;
 222        struct mtd_partition *parts;
 223        unsigned num_parts;
 224};
 225
 226struct lpc32xx_nand_host {
 227        struct nand_chip        nand_chip;
 228        struct lpc32xx_slc_platform_data *pdata;
 229        struct clk              *clk;
 230        void __iomem            *io_base;
 231        struct lpc32xx_nand_cfg_slc *ncfg;
 232
 233        struct completion       comp;
 234        struct dma_chan         *dma_chan;
 235        uint32_t                dma_buf_len;
 236        struct dma_slave_config dma_slave_config;
 237        struct scatterlist      sgl;
 238
 239        /*
 240         * DMA and CPU addresses of ECC work area and data buffer
 241         */
 242        uint32_t                *ecc_buf;
 243        uint8_t                 *data_buf;
 244        dma_addr_t              io_base_dma;
 245};
 246
 247static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
 248{
 249        uint32_t clkrate, tmp;
 250
 251        /* Reset SLC controller */
 252        writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
 253        udelay(1000);
 254
 255        /* Basic setup */
 256        writel(0, SLC_CFG(host->io_base));
 257        writel(0, SLC_IEN(host->io_base));
 258        writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
 259                SLC_ICR(host->io_base));
 260
 261        /* Get base clock for SLC block */
 262        clkrate = clk_get_rate(host->clk);
 263        if (clkrate == 0)
 264                clkrate = LPC32XX_DEF_BUS_RATE;
 265
 266        /* Compute clock setup values */
 267        tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
 268                SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
 269                SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
 270                SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
 271                SLCTAC_RDR(host->ncfg->rdr_clks) |
 272                SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
 273                SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
 274                SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
 275        writel(tmp, SLC_TAC(host->io_base));
 276}
 277
 278/*
 279 * Hardware specific access to control lines
 280 */
 281static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 282        unsigned int ctrl)
 283{
 284        uint32_t tmp;
 285        struct nand_chip *chip = mtd_to_nand(mtd);
 286        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 287
 288        /* Does CE state need to be changed? */
 289        tmp = readl(SLC_CFG(host->io_base));
 290        if (ctrl & NAND_NCE)
 291                tmp |= SLCCFG_CE_LOW;
 292        else
 293                tmp &= ~SLCCFG_CE_LOW;
 294        writel(tmp, SLC_CFG(host->io_base));
 295
 296        if (cmd != NAND_CMD_NONE) {
 297                if (ctrl & NAND_CLE)
 298                        writel(cmd, SLC_CMD(host->io_base));
 299                else
 300                        writel(cmd, SLC_ADDR(host->io_base));
 301        }
 302}
 303
 304/*
 305 * Read the Device Ready pin
 306 */
 307static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
 308{
 309        struct nand_chip *chip = mtd_to_nand(mtd);
 310        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 311        int rdy = 0;
 312
 313        if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
 314                rdy = 1;
 315
 316        return rdy;
 317}
 318
 319/*
 320 * Enable NAND write protect
 321 */
 322static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
 323{
 324        if (gpio_is_valid(host->ncfg->wp_gpio))
 325                gpio_set_value(host->ncfg->wp_gpio, 0);
 326}
 327
 328/*
 329 * Disable NAND write protect
 330 */
 331static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
 332{
 333        if (gpio_is_valid(host->ncfg->wp_gpio))
 334                gpio_set_value(host->ncfg->wp_gpio, 1);
 335}
 336
 337/*
 338 * Prepares SLC for transfers with H/W ECC enabled
 339 */
 340static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
 341{
 342        /* Hardware ECC is enabled automatically in hardware as needed */
 343}
 344
 345/*
 346 * Calculates the ECC for the data
 347 */
 348static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
 349                                      const unsigned char *buf,
 350                                      unsigned char *code)
 351{
 352        /*
 353         * ECC is calculated automatically in hardware during syndrome read
 354         * and write operations, so it doesn't need to be calculated here.
 355         */
 356        return 0;
 357}
 358
 359/*
 360 * Read a single byte from NAND device
 361 */
 362static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
 363{
 364        struct nand_chip *chip = mtd_to_nand(mtd);
 365        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 366
 367        return (uint8_t)readl(SLC_DATA(host->io_base));
 368}
 369
 370/*
 371 * Simple device read without ECC
 372 */
 373static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 374{
 375        struct nand_chip *chip = mtd_to_nand(mtd);
 376        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 377
 378        /* Direct device read with no ECC */
 379        while (len-- > 0)
 380                *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
 381}
 382
 383/*
 384 * Simple device write without ECC
 385 */
 386static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 387{
 388        struct nand_chip *chip = mtd_to_nand(mtd);
 389        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 390
 391        /* Direct device write with no ECC */
 392        while (len-- > 0)
 393                writel((uint32_t)*buf++, SLC_DATA(host->io_base));
 394}
 395
 396/*
 397 * Read the OOB data from the device without ECC using FIFO method
 398 */
 399static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
 400                                          struct nand_chip *chip, int page)
 401{
 402        return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
 403}
 404
 405/*
 406 * Write the OOB data to the device without ECC using FIFO method
 407 */
 408static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
 409        struct nand_chip *chip, int page)
 410{
 411        return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
 412                                 mtd->oobsize);
 413}
 414
 415/*
 416 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
 417 */
 418static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
 419{
 420        int i;
 421
 422        for (i = 0; i < (count * 3); i += 3) {
 423                uint32_t ce = ecc[i / 3];
 424                ce = ~(ce << 2) & 0xFFFFFF;
 425                spare[i + 2] = (uint8_t)(ce & 0xFF);
 426                ce >>= 8;
 427                spare[i + 1] = (uint8_t)(ce & 0xFF);
 428                ce >>= 8;
 429                spare[i] = (uint8_t)(ce & 0xFF);
 430        }
 431}
 432
 433static void lpc32xx_dma_complete_func(void *completion)
 434{
 435        complete(completion);
 436}
 437
 438static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
 439                            void *mem, int len, enum dma_transfer_direction dir)
 440{
 441        struct nand_chip *chip = mtd_to_nand(mtd);
 442        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 443        struct dma_async_tx_descriptor *desc;
 444        int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 445        int res;
 446
 447        host->dma_slave_config.direction = dir;
 448        host->dma_slave_config.src_addr = dma;
 449        host->dma_slave_config.dst_addr = dma;
 450        host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 451        host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 452        host->dma_slave_config.src_maxburst = 4;
 453        host->dma_slave_config.dst_maxburst = 4;
 454        /* DMA controller does flow control: */
 455        host->dma_slave_config.device_fc = false;
 456        if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
 457                dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
 458                return -ENXIO;
 459        }
 460
 461        sg_init_one(&host->sgl, mem, len);
 462
 463        res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
 464                         DMA_BIDIRECTIONAL);
 465        if (res != 1) {
 466                dev_err(mtd->dev.parent, "Failed to map sg list\n");
 467                return -ENXIO;
 468        }
 469        desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
 470                                       flags);
 471        if (!desc) {
 472                dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
 473                goto out1;
 474        }
 475
 476        init_completion(&host->comp);
 477        desc->callback = lpc32xx_dma_complete_func;
 478        desc->callback_param = &host->comp;
 479
 480        dmaengine_submit(desc);
 481        dma_async_issue_pending(host->dma_chan);
 482
 483        wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
 484
 485        dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 486                     DMA_BIDIRECTIONAL);
 487
 488        return 0;
 489out1:
 490        dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 491                     DMA_BIDIRECTIONAL);
 492        return -ENXIO;
 493}
 494
 495/*
 496 * DMA read/write transfers with ECC support
 497 */
 498static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
 499                        int read)
 500{
 501        struct nand_chip *chip = mtd_to_nand(mtd);
 502        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 503        int i, status = 0;
 504        unsigned long timeout;
 505        int res;
 506        enum dma_transfer_direction dir =
 507                read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 508        uint8_t *dma_buf;
 509        bool dma_mapped;
 510
 511        if ((void *)buf <= high_memory) {
 512                dma_buf = buf;
 513                dma_mapped = true;
 514        } else {
 515                dma_buf = host->data_buf;
 516                dma_mapped = false;
 517                if (!read)
 518                        memcpy(host->data_buf, buf, mtd->writesize);
 519        }
 520
 521        if (read) {
 522                writel(readl(SLC_CFG(host->io_base)) |
 523                       SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
 524                       SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
 525        } else {
 526                writel((readl(SLC_CFG(host->io_base)) |
 527                        SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
 528                       ~SLCCFG_DMA_DIR,
 529                        SLC_CFG(host->io_base));
 530        }
 531
 532        /* Clear initial ECC */
 533        writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
 534
 535        /* Transfer size is data area only */
 536        writel(mtd->writesize, SLC_TC(host->io_base));
 537
 538        /* Start transfer in the NAND controller */
 539        writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
 540               SLC_CTRL(host->io_base));
 541
 542        for (i = 0; i < chip->ecc.steps; i++) {
 543                /* Data */
 544                res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
 545                                       dma_buf + i * chip->ecc.size,
 546                                       mtd->writesize / chip->ecc.steps, dir);
 547                if (res)
 548                        return res;
 549
 550                /* Always _read_ ECC */
 551                if (i == chip->ecc.steps - 1)
 552                        break;
 553                if (!read) /* ECC availability delayed on write */
 554                        udelay(10);
 555                res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
 556                                       &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
 557                if (res)
 558                        return res;
 559        }
 560
 561        /*
 562         * According to NXP, the DMA can be finished here, but the NAND
 563         * controller may still have buffered data. After porting to using the
 564         * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
 565         * appears to be always true, according to tests. Keeping the check for
 566         * safety reasons for now.
 567         */
 568        if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
 569                dev_warn(mtd->dev.parent, "FIFO not empty!\n");
 570                timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
 571                while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
 572                       time_before(jiffies, timeout))
 573                        cpu_relax();
 574                if (!time_before(jiffies, timeout)) {
 575                        dev_err(mtd->dev.parent, "FIFO held data too long\n");
 576                        status = -EIO;
 577                }
 578        }
 579
 580        /* Read last calculated ECC value */
 581        if (!read)
 582                udelay(10);
 583        host->ecc_buf[chip->ecc.steps - 1] =
 584                readl(SLC_ECC(host->io_base));
 585
 586        /* Flush DMA */
 587        dmaengine_terminate_all(host->dma_chan);
 588
 589        if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
 590            readl(SLC_TC(host->io_base))) {
 591                /* Something is left in the FIFO, something is wrong */
 592                dev_err(mtd->dev.parent, "DMA FIFO failure\n");
 593                status = -EIO;
 594        }
 595
 596        /* Stop DMA & HW ECC */
 597        writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
 598               SLC_CTRL(host->io_base));
 599        writel(readl(SLC_CFG(host->io_base)) &
 600               ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
 601                 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
 602
 603        if (!dma_mapped && read)
 604                memcpy(buf, host->data_buf, mtd->writesize);
 605
 606        return status;
 607}
 608
 609/*
 610 * Read the data and OOB data from the device, use ECC correction with the
 611 * data, disable ECC for the OOB data
 612 */
 613static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
 614                                           struct nand_chip *chip, uint8_t *buf,
 615                                           int oob_required, int page)
 616{
 617        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 618        struct mtd_oob_region oobregion = { };
 619        int stat, i, status, error;
 620        uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
 621
 622        /* Issue read command */
 623        nand_read_page_op(chip, page, 0, NULL, 0);
 624
 625        /* Read data and oob, calculate ECC */
 626        status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
 627
 628        /* Get OOB data */
 629        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 630
 631        /* Convert to stored ECC format */
 632        lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
 633
 634        /* Pointer to ECC data retrieved from NAND spare area */
 635        error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
 636        if (error)
 637                return error;
 638
 639        oobecc = chip->oob_poi + oobregion.offset;
 640
 641        for (i = 0; i < chip->ecc.steps; i++) {
 642                stat = chip->ecc.correct(mtd, buf, oobecc,
 643                                         &tmpecc[i * chip->ecc.bytes]);
 644                if (stat < 0)
 645                        mtd->ecc_stats.failed++;
 646                else
 647                        mtd->ecc_stats.corrected += stat;
 648
 649                buf += chip->ecc.size;
 650                oobecc += chip->ecc.bytes;
 651        }
 652
 653        return status;
 654}
 655
 656/*
 657 * Read the data and OOB data from the device, no ECC correction with the
 658 * data or OOB data
 659 */
 660static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 661                                               struct nand_chip *chip,
 662                                               uint8_t *buf, int oob_required,
 663                                               int page)
 664{
 665        /* Issue read command */
 666        nand_read_page_op(chip, page, 0, NULL, 0);
 667
 668        /* Raw reads can just use the FIFO interface */
 669        chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
 670        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 671
 672        return 0;
 673}
 674
 675/*
 676 * Write the data and OOB data to the device, use ECC with the data,
 677 * disable ECC for the OOB data
 678 */
 679static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
 680                                            struct nand_chip *chip,
 681                                            const uint8_t *buf,
 682                                            int oob_required, int page)
 683{
 684        struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 685        struct mtd_oob_region oobregion = { };
 686        uint8_t *pb;
 687        int error;
 688
 689        nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 690
 691        /* Write data, calculate ECC on outbound data */
 692        error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
 693        if (error)
 694                return error;
 695
 696        /*
 697         * The calculated ECC needs some manual work done to it before
 698         * committing it to NAND. Process the calculated ECC and place
 699         * the resultant values directly into the OOB buffer. */
 700        error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
 701        if (error)
 702                return error;
 703
 704        pb = chip->oob_poi + oobregion.offset;
 705        lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
 706
 707        /* Write ECC data to device */
 708        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 709
 710        return nand_prog_page_end_op(chip);
 711}
 712
 713/*
 714 * Write the data and OOB data to the device, no ECC correction with the
 715 * data or OOB data
 716 */
 717static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 718                                                struct nand_chip *chip,
 719                                                const uint8_t *buf,
 720                                                int oob_required, int page)
 721{
 722        /* Raw writes can just use the FIFO interface */
 723        nand_prog_page_begin_op(chip, page, 0, buf,
 724                                chip->ecc.size * chip->ecc.steps);
 725        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 726
 727        return nand_prog_page_end_op(chip);
 728}
 729
 730static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
 731{
 732        struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 733        dma_cap_mask_t mask;
 734
 735        if (!host->pdata || !host->pdata->dma_filter) {
 736                dev_err(mtd->dev.parent, "no DMA platform data\n");
 737                return -ENOENT;
 738        }
 739
 740        dma_cap_zero(mask);
 741        dma_cap_set(DMA_SLAVE, mask);
 742        host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
 743                                             "nand-slc");
 744        if (!host->dma_chan) {
 745                dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 746                return -EBUSY;
 747        }
 748
 749        return 0;
 750}
 751
 752static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
 753{
 754        struct lpc32xx_nand_cfg_slc *ncfg;
 755        struct device_node *np = dev->of_node;
 756
 757        ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
 758        if (!ncfg)
 759                return NULL;
 760
 761        of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
 762        of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
 763        of_property_read_u32(np, "nxp,whold", &ncfg->whold);
 764        of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
 765        of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
 766        of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
 767        of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
 768        of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
 769
 770        if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
 771            !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
 772            !ncfg->rhold || !ncfg->rsetup) {
 773                dev_err(dev, "chip parameters not specified correctly\n");
 774                return NULL;
 775        }
 776
 777        ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
 778
 779        return ncfg;
 780}
 781
 782/*
 783 * Probe for NAND controller
 784 */
 785static int lpc32xx_nand_probe(struct platform_device *pdev)
 786{
 787        struct lpc32xx_nand_host *host;
 788        struct mtd_info *mtd;
 789        struct nand_chip *chip;
 790        struct resource *rc;
 791        int res;
 792
 793        /* Allocate memory for the device structure (and zero it) */
 794        host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 795        if (!host)
 796                return -ENOMEM;
 797
 798        rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 799        host->io_base = devm_ioremap_resource(&pdev->dev, rc);
 800        if (IS_ERR(host->io_base))
 801                return PTR_ERR(host->io_base);
 802
 803        host->io_base_dma = rc->start;
 804        if (pdev->dev.of_node)
 805                host->ncfg = lpc32xx_parse_dt(&pdev->dev);
 806        if (!host->ncfg) {
 807                dev_err(&pdev->dev,
 808                        "Missing or bad NAND config from device tree\n");
 809                return -ENOENT;
 810        }
 811        if (host->ncfg->wp_gpio == -EPROBE_DEFER)
 812                return -EPROBE_DEFER;
 813        if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
 814                        host->ncfg->wp_gpio, "NAND WP")) {
 815                dev_err(&pdev->dev, "GPIO not available\n");
 816                return -EBUSY;
 817        }
 818        lpc32xx_wp_disable(host);
 819
 820        host->pdata = dev_get_platdata(&pdev->dev);
 821
 822        chip = &host->nand_chip;
 823        mtd = nand_to_mtd(chip);
 824        nand_set_controller_data(chip, host);
 825        nand_set_flash_node(chip, pdev->dev.of_node);
 826        mtd->owner = THIS_MODULE;
 827        mtd->dev.parent = &pdev->dev;
 828
 829        /* Get NAND clock */
 830        host->clk = devm_clk_get(&pdev->dev, NULL);
 831        if (IS_ERR(host->clk)) {
 832                dev_err(&pdev->dev, "Clock failure\n");
 833                res = -ENOENT;
 834                goto enable_wp;
 835        }
 836        res = clk_prepare_enable(host->clk);
 837        if (res)
 838                goto enable_wp;
 839
 840        /* Set NAND IO addresses and command/ready functions */
 841        chip->IO_ADDR_R = SLC_DATA(host->io_base);
 842        chip->IO_ADDR_W = SLC_DATA(host->io_base);
 843        chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
 844        chip->dev_ready = lpc32xx_nand_device_ready;
 845        chip->chip_delay = 20; /* 20us command delay time */
 846
 847        /* Init NAND controller */
 848        lpc32xx_nand_setup(host);
 849
 850        platform_set_drvdata(pdev, host);
 851
 852        /* NAND callbacks for LPC32xx SLC hardware */
 853        chip->ecc.mode = NAND_ECC_HW_SYNDROME;
 854        chip->read_byte = lpc32xx_nand_read_byte;
 855        chip->read_buf = lpc32xx_nand_read_buf;
 856        chip->write_buf = lpc32xx_nand_write_buf;
 857        chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
 858        chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
 859        chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
 860        chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
 861        chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
 862        chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
 863        chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
 864        chip->ecc.correct = nand_correct_data;
 865        chip->ecc.strength = 1;
 866        chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
 867
 868        /*
 869         * Allocate a large enough buffer for a single huge page plus
 870         * extra space for the spare area and ECC storage area
 871         */
 872        host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
 873        host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
 874                                      GFP_KERNEL);
 875        if (host->data_buf == NULL) {
 876                res = -ENOMEM;
 877                goto unprepare_clk;
 878        }
 879
 880        res = lpc32xx_nand_dma_setup(host);
 881        if (res) {
 882                res = -EIO;
 883                goto unprepare_clk;
 884        }
 885
 886        /* Find NAND device */
 887        res = nand_scan_ident(mtd, 1, NULL);
 888        if (res)
 889                goto release_dma;
 890
 891        /* OOB and ECC CPU and DMA work areas */
 892        host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
 893
 894        /*
 895         * Small page FLASH has a unique OOB layout, but large and huge
 896         * page FLASH use the standard layout. Small page FLASH uses a
 897         * custom BBT marker layout.
 898         */
 899        if (mtd->writesize <= 512)
 900                mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
 901
 902        /* These sizes remain the same regardless of page size */
 903        chip->ecc.size = 256;
 904        chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
 905        chip->ecc.prepad = chip->ecc.postpad = 0;
 906
 907        /*
 908         * Use a custom BBT marker setup for small page FLASH that
 909         * won't interfere with the ECC layout. Large and huge page
 910         * FLASH use the standard layout.
 911         */
 912        if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
 913            mtd->writesize <= 512) {
 914                chip->bbt_td = &bbt_smallpage_main_descr;
 915                chip->bbt_md = &bbt_smallpage_mirror_descr;
 916        }
 917
 918        /*
 919         * Fills out all the uninitialized function pointers with the defaults
 920         */
 921        res = nand_scan_tail(mtd);
 922        if (res)
 923                goto release_dma;
 924
 925        mtd->name = "nxp_lpc3220_slc";
 926        res = mtd_device_register(mtd, host->ncfg->parts,
 927                                  host->ncfg->num_parts);
 928        if (res)
 929                goto cleanup_nand;
 930
 931        return 0;
 932
 933cleanup_nand:
 934        nand_cleanup(chip);
 935release_dma:
 936        dma_release_channel(host->dma_chan);
 937unprepare_clk:
 938        clk_disable_unprepare(host->clk);
 939enable_wp:
 940        lpc32xx_wp_enable(host);
 941
 942        return res;
 943}
 944
 945/*
 946 * Remove NAND device.
 947 */
 948static int lpc32xx_nand_remove(struct platform_device *pdev)
 949{
 950        uint32_t tmp;
 951        struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 952        struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 953
 954        nand_release(mtd);
 955        dma_release_channel(host->dma_chan);
 956
 957        /* Force CE high */
 958        tmp = readl(SLC_CTRL(host->io_base));
 959        tmp &= ~SLCCFG_CE_LOW;
 960        writel(tmp, SLC_CTRL(host->io_base));
 961
 962        clk_disable_unprepare(host->clk);
 963        lpc32xx_wp_enable(host);
 964
 965        return 0;
 966}
 967
 968#ifdef CONFIG_PM
 969static int lpc32xx_nand_resume(struct platform_device *pdev)
 970{
 971        struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 972        int ret;
 973
 974        /* Re-enable NAND clock */
 975        ret = clk_prepare_enable(host->clk);
 976        if (ret)
 977                return ret;
 978
 979        /* Fresh init of NAND controller */
 980        lpc32xx_nand_setup(host);
 981
 982        /* Disable write protect */
 983        lpc32xx_wp_disable(host);
 984
 985        return 0;
 986}
 987
 988static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
 989{
 990        uint32_t tmp;
 991        struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 992
 993        /* Force CE high */
 994        tmp = readl(SLC_CTRL(host->io_base));
 995        tmp &= ~SLCCFG_CE_LOW;
 996        writel(tmp, SLC_CTRL(host->io_base));
 997
 998        /* Enable write protect for safety */
 999        lpc32xx_wp_enable(host);
1000

1001        /* Disable clock */
1002        clk_disable_unprepare(host->clk);
1003
1004        return 0;
1005}
1006
1007#else
1008#define lpc32xx_nand_resume NULL
1009#define lpc32xx_nand_suspend NULL
1010#endif
1011
1012static const struct of_device_id lpc32xx_nand_match[] = {
1013        { .compatible = "nxp,lpc3220-slc" },
1014        { /* sentinel */ },
1015};
1016MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1017
1018static struct platform_driver lpc32xx_nand_driver = {
1019        .probe          = lpc32xx_nand_probe,
1020        .remove         = lpc32xx_nand_remove,
1021        .resume         = lpc32xx_nand_resume,
1022        .suspend        = lpc32xx_nand_suspend,
1023        .driver         = {
1024                .name   = LPC32XX_MODNAME,
1025                .of_match_table = lpc32xx_nand_match,
1026        },
1027};
1028
1029module_platform_driver(lpc32xx_nand_driver);
1030
1031MODULE_LICENSE("GPL");
1032MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1033MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1034MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
1035