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32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/if_vlan.h>
43#include <linux/mdio.h>
44#include <linux/sockios.h>
45#include <linux/workqueue.h>
46#include <linux/proc_fs.h>
47#include <linux/rtnetlink.h>
48#include <linux/firmware.h>
49#include <linux/log2.h>
50#include <linux/stringify.h>
51#include <linux/sched.h>
52#include <linux/slab.h>
53#include <linux/uaccess.h>
54#include <linux/nospec.h>
55
56#include "common.h"
57#include "cxgb3_ioctl.h"
58#include "regs.h"
59#include "cxgb3_offload.h"
60#include "version.h"
61
62#include "cxgb3_ctl_defs.h"
63#include "t3_cpl.h"
64#include "firmware_exports.h"
65
66enum {
67 MAX_TXQ_ENTRIES = 16384,
68 MAX_CTRL_TXQ_ENTRIES = 1024,
69 MAX_RSPQ_ENTRIES = 16384,
70 MAX_RX_BUFFERS = 16384,
71 MAX_RX_JUMBO_BUFFERS = 16384,
72 MIN_TXQ_ENTRIES = 4,
73 MIN_CTRL_TXQ_ENTRIES = 4,
74 MIN_RSPQ_ENTRIES = 32,
75 MIN_FL_ENTRIES = 32
76};
77
78#define PORT_MASK ((1 << MAX_NPORTS) - 1)
79
80#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
82 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
83
84#define EEPROM_MAGIC 0x38E2F10C
85
86#define CH_DEVICE(devid, idx) \
87 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
88
89static const struct pci_device_id cxgb3_pci_tbl[] = {
90 CH_DEVICE(0x20, 0),
91 CH_DEVICE(0x21, 1),
92 CH_DEVICE(0x22, 2),
93 CH_DEVICE(0x23, 3),
94 CH_DEVICE(0x24, 1),
95 CH_DEVICE(0x25, 3),
96 CH_DEVICE(0x26, 2),
97 CH_DEVICE(0x30, 2),
98 CH_DEVICE(0x31, 3),
99 CH_DEVICE(0x32, 1),
100 CH_DEVICE(0x35, 6),
101 CH_DEVICE(0x36, 3),
102 CH_DEVICE(0x37, 7),
103 {0,}
104};
105
106MODULE_DESCRIPTION(DRV_DESC);
107MODULE_AUTHOR("Chelsio Communications");
108MODULE_LICENSE("Dual BSD/GPL");
109MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
110
111static int dflt_msg_enable = DFLT_MSG_ENABLE;
112
113module_param(dflt_msg_enable, int, 0644);
114MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
115
116
117
118
119
120
121
122
123
124
125static int msi = 2;
126
127module_param(msi, int, 0644);
128MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
129
130
131
132
133
134
135static int ofld_disable = 0;
136
137module_param(ofld_disable, int, 0644);
138MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
139
140
141
142
143
144
145
146
147
148struct workqueue_struct *cxgb3_wq;
149
150
151
152
153
154
155
156static void link_report(struct net_device *dev)
157{
158 if (!netif_carrier_ok(dev))
159 netdev_info(dev, "link down\n");
160 else {
161 const char *s = "10Mbps";
162 const struct port_info *p = netdev_priv(dev);
163
164 switch (p->link_config.speed) {
165 case SPEED_10000:
166 s = "10Gbps";
167 break;
168 case SPEED_1000:
169 s = "1000Mbps";
170 break;
171 case SPEED_100:
172 s = "100Mbps";
173 break;
174 }
175
176 netdev_info(dev, "link up, %s, %s-duplex\n",
177 s, p->link_config.duplex == DUPLEX_FULL
178 ? "full" : "half");
179 }
180}
181
182static void enable_tx_fifo_drain(struct adapter *adapter,
183 struct port_info *pi)
184{
185 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
186 F_ENDROPPKT);
187 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
188 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
189 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
190}
191
192static void disable_tx_fifo_drain(struct adapter *adapter,
193 struct port_info *pi)
194{
195 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
196 F_ENDROPPKT, 0);
197}
198
199void t3_os_link_fault(struct adapter *adap, int port_id, int state)
200{
201 struct net_device *dev = adap->port[port_id];
202 struct port_info *pi = netdev_priv(dev);
203
204 if (state == netif_carrier_ok(dev))
205 return;
206
207 if (state) {
208 struct cmac *mac = &pi->mac;
209
210 netif_carrier_on(dev);
211
212 disable_tx_fifo_drain(adap, pi);
213
214
215 t3_xgm_intr_disable(adap, pi->port_id);
216 t3_read_reg(adap, A_XGM_INT_STATUS +
217 pi->mac.offset);
218 t3_write_reg(adap,
219 A_XGM_INT_CAUSE + pi->mac.offset,
220 F_XGM_INT);
221
222 t3_set_reg_field(adap,
223 A_XGM_INT_ENABLE +
224 pi->mac.offset,
225 F_XGM_INT, F_XGM_INT);
226 t3_xgm_intr_enable(adap, pi->port_id);
227
228 t3_mac_enable(mac, MAC_DIRECTION_TX);
229 } else {
230 netif_carrier_off(dev);
231
232
233 enable_tx_fifo_drain(adap, pi);
234 }
235 link_report(dev);
236}
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
252 int speed, int duplex, int pause)
253{
254 struct net_device *dev = adapter->port[port_id];
255 struct port_info *pi = netdev_priv(dev);
256 struct cmac *mac = &pi->mac;
257
258
259 if (!netif_running(dev))
260 return;
261
262 if (link_stat != netif_carrier_ok(dev)) {
263 if (link_stat) {
264 disable_tx_fifo_drain(adapter, pi);
265
266 t3_mac_enable(mac, MAC_DIRECTION_RX);
267
268
269 t3_xgm_intr_disable(adapter, pi->port_id);
270 t3_read_reg(adapter, A_XGM_INT_STATUS +
271 pi->mac.offset);
272 t3_write_reg(adapter,
273 A_XGM_INT_CAUSE + pi->mac.offset,
274 F_XGM_INT);
275
276 t3_set_reg_field(adapter,
277 A_XGM_INT_ENABLE + pi->mac.offset,
278 F_XGM_INT, F_XGM_INT);
279 t3_xgm_intr_enable(adapter, pi->port_id);
280
281 netif_carrier_on(dev);
282 } else {
283 netif_carrier_off(dev);
284
285 t3_xgm_intr_disable(adapter, pi->port_id);
286 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
287 t3_set_reg_field(adapter,
288 A_XGM_INT_ENABLE + pi->mac.offset,
289 F_XGM_INT, 0);
290
291 if (is_10G(adapter))
292 pi->phy.ops->power_down(&pi->phy, 1);
293
294 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
295 t3_mac_disable(mac, MAC_DIRECTION_RX);
296 t3_link_start(&pi->phy, mac, &pi->link_config);
297
298
299 enable_tx_fifo_drain(adapter, pi);
300 }
301
302 link_report(dev);
303 }
304}
305
306
307
308
309
310
311
312
313
314
315void t3_os_phymod_changed(struct adapter *adap, int port_id)
316{
317 static const char *mod_str[] = {
318 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
319 };
320
321 const struct net_device *dev = adap->port[port_id];
322 const struct port_info *pi = netdev_priv(dev);
323
324 if (pi->phy.modtype == phy_modtype_none)
325 netdev_info(dev, "PHY module unplugged\n");
326 else
327 netdev_info(dev, "%s PHY module inserted\n",
328 mod_str[pi->phy.modtype]);
329}
330
331static void cxgb_set_rxmode(struct net_device *dev)
332{
333 struct port_info *pi = netdev_priv(dev);
334
335 t3_mac_set_rx_mode(&pi->mac, dev);
336}
337
338
339
340
341
342
343
344static void link_start(struct net_device *dev)
345{
346 struct port_info *pi = netdev_priv(dev);
347 struct cmac *mac = &pi->mac;
348
349 t3_mac_reset(mac);
350 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
351 t3_mac_set_mtu(mac, dev->mtu);
352 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
353 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
354 t3_mac_set_rx_mode(mac, dev);
355 t3_link_start(&pi->phy, mac, &pi->link_config);
356 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
357}
358
359static inline void cxgb_disable_msi(struct adapter *adapter)
360{
361 if (adapter->flags & USING_MSIX) {
362 pci_disable_msix(adapter->pdev);
363 adapter->flags &= ~USING_MSIX;
364 } else if (adapter->flags & USING_MSI) {
365 pci_disable_msi(adapter->pdev);
366 adapter->flags &= ~USING_MSI;
367 }
368}
369
370
371
372
373static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
374{
375 t3_slow_intr_handler(cookie);
376 return IRQ_HANDLED;
377}
378
379
380
381
382static void name_msix_vecs(struct adapter *adap)
383{
384 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
385
386 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
387 adap->msix_info[0].desc[n] = 0;
388
389 for_each_port(adap, j) {
390 struct net_device *d = adap->port[j];
391 const struct port_info *pi = netdev_priv(d);
392
393 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
394 snprintf(adap->msix_info[msi_idx].desc, n,
395 "%s-%d", d->name, pi->first_qset + i);
396 adap->msix_info[msi_idx].desc[n] = 0;
397 }
398 }
399}
400
401static int request_msix_data_irqs(struct adapter *adap)
402{
403 int i, j, err, qidx = 0;
404
405 for_each_port(adap, i) {
406 int nqsets = adap2pinfo(adap, i)->nqsets;
407
408 for (j = 0; j < nqsets; ++j) {
409 err = request_irq(adap->msix_info[qidx + 1].vec,
410 t3_intr_handler(adap,
411 adap->sge.qs[qidx].
412 rspq.polling), 0,
413 adap->msix_info[qidx + 1].desc,
414 &adap->sge.qs[qidx]);
415 if (err) {
416 while (--qidx >= 0)
417 free_irq(adap->msix_info[qidx + 1].vec,
418 &adap->sge.qs[qidx]);
419 return err;
420 }
421 qidx++;
422 }
423 }
424 return 0;
425}
426
427static void free_irq_resources(struct adapter *adapter)
428{
429 if (adapter->flags & USING_MSIX) {
430 int i, n = 0;
431
432 free_irq(adapter->msix_info[0].vec, adapter);
433 for_each_port(adapter, i)
434 n += adap2pinfo(adapter, i)->nqsets;
435
436 for (i = 0; i < n; ++i)
437 free_irq(adapter->msix_info[i + 1].vec,
438 &adapter->sge.qs[i]);
439 } else
440 free_irq(adapter->pdev->irq, adapter);
441}
442
443static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
444 unsigned long n)
445{
446 int attempts = 10;
447
448 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
449 if (!--attempts)
450 return -ETIMEDOUT;
451 msleep(10);
452 }
453 return 0;
454}
455
456static int init_tp_parity(struct adapter *adap)
457{
458 int i;
459 struct sk_buff *skb;
460 struct cpl_set_tcb_field *greq;
461 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
462
463 t3_tp_set_offload_mode(adap, 1);
464
465 for (i = 0; i < 16; i++) {
466 struct cpl_smt_write_req *req;
467
468 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
469 if (!skb)
470 skb = adap->nofail_skb;
471 if (!skb)
472 goto alloc_skb_fail;
473
474 req = __skb_put_zero(skb, sizeof(*req));
475 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
476 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
477 req->mtu_idx = NMTUS - 1;
478 req->iff = i;
479 t3_mgmt_tx(adap, skb);
480 if (skb == adap->nofail_skb) {
481 await_mgmt_replies(adap, cnt, i + 1);
482 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
483 if (!adap->nofail_skb)
484 goto alloc_skb_fail;
485 }
486 }
487
488 for (i = 0; i < 2048; i++) {
489 struct cpl_l2t_write_req *req;
490
491 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
492 if (!skb)
493 skb = adap->nofail_skb;
494 if (!skb)
495 goto alloc_skb_fail;
496
497 req = __skb_put_zero(skb, sizeof(*req));
498 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
499 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
500 req->params = htonl(V_L2T_W_IDX(i));
501 t3_mgmt_tx(adap, skb);
502 if (skb == adap->nofail_skb) {
503 await_mgmt_replies(adap, cnt, 16 + i + 1);
504 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
505 if (!adap->nofail_skb)
506 goto alloc_skb_fail;
507 }
508 }
509
510 for (i = 0; i < 2048; i++) {
511 struct cpl_rte_write_req *req;
512
513 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
514 if (!skb)
515 skb = adap->nofail_skb;
516 if (!skb)
517 goto alloc_skb_fail;
518
519 req = __skb_put_zero(skb, sizeof(*req));
520 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
521 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
522 req->l2t_idx = htonl(V_L2T_W_IDX(i));
523 t3_mgmt_tx(adap, skb);
524 if (skb == adap->nofail_skb) {
525 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
526 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
527 if (!adap->nofail_skb)
528 goto alloc_skb_fail;
529 }
530 }
531
532 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
533 if (!skb)
534 skb = adap->nofail_skb;
535 if (!skb)
536 goto alloc_skb_fail;
537
538 greq = __skb_put_zero(skb, sizeof(*greq));
539 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
540 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
541 greq->mask = cpu_to_be64(1);
542 t3_mgmt_tx(adap, skb);
543
544 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
545 if (skb == adap->nofail_skb) {
546 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
547 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
548 }
549
550 t3_tp_set_offload_mode(adap, 0);
551 return i;
552
553alloc_skb_fail:
554 t3_tp_set_offload_mode(adap, 0);
555 return -ENOMEM;
556}
557
558
559
560
561
562
563
564
565
566
567
568
569static void setup_rss(struct adapter *adap)
570{
571 int i;
572 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
573 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
574 u8 cpus[SGE_QSETS + 1];
575 u16 rspq_map[RSS_TABLE_SIZE + 1];
576
577 for (i = 0; i < SGE_QSETS; ++i)
578 cpus[i] = i;
579 cpus[SGE_QSETS] = 0xff;
580
581 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
582 rspq_map[i] = i % nq0;
583 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
584 }
585 rspq_map[RSS_TABLE_SIZE] = 0xffff;
586
587 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
588 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
589 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
590}
591
592static void ring_dbs(struct adapter *adap)
593{
594 int i, j;
595
596 for (i = 0; i < SGE_QSETS; i++) {
597 struct sge_qset *qs = &adap->sge.qs[i];
598
599 if (qs->adap)
600 for (j = 0; j < SGE_TXQ_PER_SET; j++)
601 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
602 }
603}
604
605static void init_napi(struct adapter *adap)
606{
607 int i;
608
609 for (i = 0; i < SGE_QSETS; i++) {
610 struct sge_qset *qs = &adap->sge.qs[i];
611
612 if (qs->adap)
613 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
614 64);
615 }
616
617
618
619
620
621
622 adap->flags |= NAPI_INIT;
623}
624
625
626
627
628
629
630static void quiesce_rx(struct adapter *adap)
631{
632 int i;
633
634 for (i = 0; i < SGE_QSETS; i++)
635 if (adap->sge.qs[i].adap)
636 napi_disable(&adap->sge.qs[i].napi);
637}
638
639static void enable_all_napi(struct adapter *adap)
640{
641 int i;
642 for (i = 0; i < SGE_QSETS; i++)
643 if (adap->sge.qs[i].adap)
644 napi_enable(&adap->sge.qs[i].napi);
645}
646
647
648
649
650
651
652
653
654
655static int setup_sge_qsets(struct adapter *adap)
656{
657 int i, j, err, irq_idx = 0, qset_idx = 0;
658 unsigned int ntxq = SGE_TXQ_PER_SET;
659
660 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
661 irq_idx = -1;
662
663 for_each_port(adap, i) {
664 struct net_device *dev = adap->port[i];
665 struct port_info *pi = netdev_priv(dev);
666
667 pi->qs = &adap->sge.qs[pi->first_qset];
668 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
669 err = t3_sge_alloc_qset(adap, qset_idx, 1,
670 (adap->flags & USING_MSIX) ? qset_idx + 1 :
671 irq_idx,
672 &adap->params.sge.qset[qset_idx], ntxq, dev,
673 netdev_get_tx_queue(dev, j));
674 if (err) {
675 t3_free_sge_resources(adap);
676 return err;
677 }
678 }
679 }
680
681 return 0;
682}
683
684static ssize_t attr_show(struct device *d, char *buf,
685 ssize_t(*format) (struct net_device *, char *))
686{
687 ssize_t len;
688
689
690 rtnl_lock();
691 len = (*format) (to_net_dev(d), buf);
692 rtnl_unlock();
693 return len;
694}
695
696static ssize_t attr_store(struct device *d,
697 const char *buf, size_t len,
698 ssize_t(*set) (struct net_device *, unsigned int),
699 unsigned int min_val, unsigned int max_val)
700{
701 ssize_t ret;
702 unsigned int val;
703
704 if (!capable(CAP_NET_ADMIN))
705 return -EPERM;
706
707 ret = kstrtouint(buf, 0, &val);
708 if (ret)
709 return ret;
710 if (val < min_val || val > max_val)
711 return -EINVAL;
712
713 rtnl_lock();
714 ret = (*set) (to_net_dev(d), val);
715 if (!ret)
716 ret = len;
717 rtnl_unlock();
718 return ret;
719}
720
721#define CXGB3_SHOW(name, val_expr) \
722static ssize_t format_##name(struct net_device *dev, char *buf) \
723{ \
724 struct port_info *pi = netdev_priv(dev); \
725 struct adapter *adap = pi->adapter; \
726 return sprintf(buf, "%u\n", val_expr); \
727} \
728static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
729 char *buf) \
730{ \
731 return attr_show(d, buf, format_##name); \
732}
733
734static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
735{
736 struct port_info *pi = netdev_priv(dev);
737 struct adapter *adap = pi->adapter;
738 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
739
740 if (adap->flags & FULL_INIT_DONE)
741 return -EBUSY;
742 if (val && adap->params.rev == 0)
743 return -EINVAL;
744 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
745 min_tids)
746 return -EINVAL;
747 adap->params.mc5.nfilters = val;
748 return 0;
749}
750
751static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
752 const char *buf, size_t len)
753{
754 return attr_store(d, buf, len, set_nfilters, 0, ~0);
755}
756
757static ssize_t set_nservers(struct net_device *dev, unsigned int val)
758{
759 struct port_info *pi = netdev_priv(dev);
760 struct adapter *adap = pi->adapter;
761
762 if (adap->flags & FULL_INIT_DONE)
763 return -EBUSY;
764 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
765 MC5_MIN_TIDS)
766 return -EINVAL;
767 adap->params.mc5.nservers = val;
768 return 0;
769}
770
771static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
772 const char *buf, size_t len)
773{
774 return attr_store(d, buf, len, set_nservers, 0, ~0);
775}
776
777#define CXGB3_ATTR_R(name, val_expr) \
778CXGB3_SHOW(name, val_expr) \
779static DEVICE_ATTR(name, 0444, show_##name, NULL)
780
781#define CXGB3_ATTR_RW(name, val_expr, store_method) \
782CXGB3_SHOW(name, val_expr) \
783static DEVICE_ATTR(name, 0644, show_##name, store_method)
784
785CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
786CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
787CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
788
789static struct attribute *cxgb3_attrs[] = {
790 &dev_attr_cam_size.attr,
791 &dev_attr_nfilters.attr,
792 &dev_attr_nservers.attr,
793 NULL
794};
795
796static const struct attribute_group cxgb3_attr_group = {
797 .attrs = cxgb3_attrs,
798};
799
800static ssize_t tm_attr_show(struct device *d,
801 char *buf, int sched)
802{
803 struct port_info *pi = netdev_priv(to_net_dev(d));
804 struct adapter *adap = pi->adapter;
805 unsigned int v, addr, bpt, cpt;
806 ssize_t len;
807
808 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
809 rtnl_lock();
810 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
811 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
812 if (sched & 1)
813 v >>= 16;
814 bpt = (v >> 8) & 0xff;
815 cpt = v & 0xff;
816 if (!cpt)
817 len = sprintf(buf, "disabled\n");
818 else {
819 v = (adap->params.vpd.cclk * 1000) / cpt;
820 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
821 }
822 rtnl_unlock();
823 return len;
824}
825
826static ssize_t tm_attr_store(struct device *d,
827 const char *buf, size_t len, int sched)
828{
829 struct port_info *pi = netdev_priv(to_net_dev(d));
830 struct adapter *adap = pi->adapter;
831 unsigned int val;
832 ssize_t ret;
833
834 if (!capable(CAP_NET_ADMIN))
835 return -EPERM;
836
837 ret = kstrtouint(buf, 0, &val);
838 if (ret)
839 return ret;
840 if (val > 10000000)
841 return -EINVAL;
842
843 rtnl_lock();
844 ret = t3_config_sched(adap, val, sched);
845 if (!ret)
846 ret = len;
847 rtnl_unlock();
848 return ret;
849}
850
851#define TM_ATTR(name, sched) \
852static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
853 char *buf) \
854{ \
855 return tm_attr_show(d, buf, sched); \
856} \
857static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
858 const char *buf, size_t len) \
859{ \
860 return tm_attr_store(d, buf, len, sched); \
861} \
862static DEVICE_ATTR(name, 0644, show_##name, store_##name)
863
864TM_ATTR(sched0, 0);
865TM_ATTR(sched1, 1);
866TM_ATTR(sched2, 2);
867TM_ATTR(sched3, 3);
868TM_ATTR(sched4, 4);
869TM_ATTR(sched5, 5);
870TM_ATTR(sched6, 6);
871TM_ATTR(sched7, 7);
872
873static struct attribute *offload_attrs[] = {
874 &dev_attr_sched0.attr,
875 &dev_attr_sched1.attr,
876 &dev_attr_sched2.attr,
877 &dev_attr_sched3.attr,
878 &dev_attr_sched4.attr,
879 &dev_attr_sched5.attr,
880 &dev_attr_sched6.attr,
881 &dev_attr_sched7.attr,
882 NULL
883};
884
885static const struct attribute_group offload_attr_group = {
886 .attrs = offload_attrs,
887};
888
889
890
891
892
893static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
894{
895 int ret;
896
897 local_bh_disable();
898 ret = t3_offload_tx(tdev, skb);
899 local_bh_enable();
900 return ret;
901}
902
903static int write_smt_entry(struct adapter *adapter, int idx)
904{
905 struct cpl_smt_write_req *req;
906 struct port_info *pi = netdev_priv(adapter->port[idx]);
907 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
908
909 if (!skb)
910 return -ENOMEM;
911
912 req = __skb_put(skb, sizeof(*req));
913 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
914 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
915 req->mtu_idx = NMTUS - 1;
916 req->iff = idx;
917 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
918 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
919 skb->priority = 1;
920 offload_tx(&adapter->tdev, skb);
921 return 0;
922}
923
924static int init_smt(struct adapter *adapter)
925{
926 int i;
927
928 for_each_port(adapter, i)
929 write_smt_entry(adapter, i);
930 return 0;
931}
932
933static void init_port_mtus(struct adapter *adapter)
934{
935 unsigned int mtus = adapter->port[0]->mtu;
936
937 if (adapter->port[1])
938 mtus |= adapter->port[1]->mtu << 16;
939 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
940}
941
942static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
943 int hi, int port)
944{
945 struct sk_buff *skb;
946 struct mngt_pktsched_wr *req;
947 int ret;
948
949 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
950 if (!skb)
951 skb = adap->nofail_skb;
952 if (!skb)
953 return -ENOMEM;
954
955 req = skb_put(skb, sizeof(*req));
956 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
957 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
958 req->sched = sched;
959 req->idx = qidx;
960 req->min = lo;
961 req->max = hi;
962 req->binding = port;
963 ret = t3_mgmt_tx(adap, skb);
964 if (skb == adap->nofail_skb) {
965 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
966 GFP_KERNEL);
967 if (!adap->nofail_skb)
968 ret = -ENOMEM;
969 }
970
971 return ret;
972}
973
974static int bind_qsets(struct adapter *adap)
975{
976 int i, j, err = 0;
977
978 for_each_port(adap, i) {
979 const struct port_info *pi = adap2pinfo(adap, i);
980
981 for (j = 0; j < pi->nqsets; ++j) {
982 int ret = send_pktsched_cmd(adap, 1,
983 pi->first_qset + j, -1,
984 -1, i);
985 if (ret)
986 err = ret;
987 }
988 }
989
990 return err;
991}
992
993#define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
994 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
995#define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
996#define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
997 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
998#define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
999#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1000#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
1001#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
1002MODULE_FIRMWARE(FW_FNAME);
1003MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1004MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1005MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1006MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1007MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
1008
1009static inline const char *get_edc_fw_name(int edc_idx)
1010{
1011 const char *fw_name = NULL;
1012
1013 switch (edc_idx) {
1014 case EDC_OPT_AEL2005:
1015 fw_name = AEL2005_OPT_EDC_NAME;
1016 break;
1017 case EDC_TWX_AEL2005:
1018 fw_name = AEL2005_TWX_EDC_NAME;
1019 break;
1020 case EDC_TWX_AEL2020:
1021 fw_name = AEL2020_TWX_EDC_NAME;
1022 break;
1023 }
1024 return fw_name;
1025}
1026
1027int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1028{
1029 struct adapter *adapter = phy->adapter;
1030 const struct firmware *fw;
1031 const char *fw_name;
1032 u32 csum;
1033 const __be32 *p;
1034 u16 *cache = phy->phy_cache;
1035 int i, ret = -EINVAL;
1036
1037 fw_name = get_edc_fw_name(edc_idx);
1038 if (fw_name)
1039 ret = request_firmware(&fw, fw_name, &adapter->pdev->dev);
1040 if (ret < 0) {
1041 dev_err(&adapter->pdev->dev,
1042 "could not upgrade firmware: unable to load %s\n",
1043 fw_name);
1044 return ret;
1045 }
1046
1047
1048 if (fw->size > size + 4) {
1049 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1050 (unsigned int)fw->size, size + 4);
1051 ret = -EINVAL;
1052 }
1053
1054
1055 p = (const __be32 *)fw->data;
1056 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1057 csum += ntohl(p[i]);
1058
1059 if (csum != 0xffffffff) {
1060 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1061 csum);
1062 ret = -EINVAL;
1063 }
1064
1065 for (i = 0; i < size / 4 ; i++) {
1066 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1067 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1068 }
1069
1070 release_firmware(fw);
1071
1072 return ret;
1073}
1074
1075static int upgrade_fw(struct adapter *adap)
1076{
1077 int ret;
1078 const struct firmware *fw;
1079 struct device *dev = &adap->pdev->dev;
1080
1081 ret = request_firmware(&fw, FW_FNAME, dev);
1082 if (ret < 0) {
1083 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
1084 FW_FNAME);
1085 return ret;
1086 }
1087 ret = t3_load_fw(adap, fw->data, fw->size);
1088 release_firmware(fw);
1089
1090 if (ret == 0)
1091 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1092 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1093 else
1094 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1095 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1096
1097 return ret;
1098}
1099
1100static inline char t3rev2char(struct adapter *adapter)
1101{
1102 char rev = 0;
1103
1104 switch(adapter->params.rev) {
1105 case T3_REV_B:
1106 case T3_REV_B2:
1107 rev = 'b';
1108 break;
1109 case T3_REV_C:
1110 rev = 'c';
1111 break;
1112 }
1113 return rev;
1114}
1115
1116static int update_tpsram(struct adapter *adap)
1117{
1118 const struct firmware *tpsram;
1119 char buf[64];
1120 struct device *dev = &adap->pdev->dev;
1121 int ret;
1122 char rev;
1123
1124 rev = t3rev2char(adap);
1125 if (!rev)
1126 return 0;
1127
1128 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
1129
1130 ret = request_firmware(&tpsram, buf, dev);
1131 if (ret < 0) {
1132 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1133 buf);
1134 return ret;
1135 }
1136
1137 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1138 if (ret)
1139 goto release_tpsram;
1140
1141 ret = t3_set_proto_sram(adap, tpsram->data);
1142 if (ret == 0)
1143 dev_info(dev,
1144 "successful update of protocol engine "
1145 "to %d.%d.%d\n",
1146 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1147 else
1148 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1149 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1150 if (ret)
1151 dev_err(dev, "loading protocol SRAM failed\n");
1152
1153release_tpsram:
1154 release_firmware(tpsram);
1155
1156 return ret;
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
1169{
1170 int i;
1171
1172 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1173 struct sge_rspq *q = &adap->sge.qs[i].rspq;
1174
1175 spin_lock_irq(&q->lock);
1176 spin_unlock_irq(&q->lock);
1177 }
1178}
1179
1180static void cxgb_vlan_mode(struct net_device *dev, netdev_features_t features)
1181{
1182 struct port_info *pi = netdev_priv(dev);
1183 struct adapter *adapter = pi->adapter;
1184
1185 if (adapter->params.rev > 0) {
1186 t3_set_vlan_accel(adapter, 1 << pi->port_id,
1187 features & NETIF_F_HW_VLAN_CTAG_RX);
1188 } else {
1189
1190 unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_CTAG_RX;
1191
1192 for_each_port(adapter, i)
1193 have_vlans |=
1194 adapter->port[i]->features &
1195 NETIF_F_HW_VLAN_CTAG_RX;
1196
1197 t3_set_vlan_accel(adapter, 1, have_vlans);
1198 }
1199 t3_synchronize_rx(adapter, pi);
1200}
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212static int cxgb_up(struct adapter *adap)
1213{
1214 int i, err;
1215
1216 if (!(adap->flags & FULL_INIT_DONE)) {
1217 err = t3_check_fw_version(adap);
1218 if (err == -EINVAL) {
1219 err = upgrade_fw(adap);
1220 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1221 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1222 FW_VERSION_MICRO, err ? "failed" : "succeeded");
1223 }
1224
1225 err = t3_check_tpsram_version(adap);
1226 if (err == -EINVAL) {
1227 err = update_tpsram(adap);
1228 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1229 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1230 TP_VERSION_MICRO, err ? "failed" : "succeeded");
1231 }
1232
1233
1234
1235
1236
1237
1238 t3_intr_clear(adap);
1239
1240 err = t3_init_hw(adap, 0);
1241 if (err)
1242 goto out;
1243
1244 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1245 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1246
1247 err = setup_sge_qsets(adap);
1248 if (err)
1249 goto out;
1250
1251 for_each_port(adap, i)
1252 cxgb_vlan_mode(adap->port[i], adap->port[i]->features);
1253
1254 setup_rss(adap);
1255 if (!(adap->flags & NAPI_INIT))
1256 init_napi(adap);
1257
1258 t3_start_sge_timers(adap);
1259 adap->flags |= FULL_INIT_DONE;
1260 }
1261
1262 t3_intr_clear(adap);
1263
1264 if (adap->flags & USING_MSIX) {
1265 name_msix_vecs(adap);
1266 err = request_irq(adap->msix_info[0].vec,
1267 t3_async_intr_handler, 0,
1268 adap->msix_info[0].desc, adap);
1269 if (err)
1270 goto irq_err;
1271
1272 err = request_msix_data_irqs(adap);
1273 if (err) {
1274 free_irq(adap->msix_info[0].vec, adap);
1275 goto irq_err;
1276 }
1277 } else if ((err = request_irq(adap->pdev->irq,
1278 t3_intr_handler(adap,
1279 adap->sge.qs[0].rspq.
1280 polling),
1281 (adap->flags & USING_MSI) ?
1282 0 : IRQF_SHARED,
1283 adap->name, adap)))
1284 goto irq_err;
1285
1286 enable_all_napi(adap);
1287 t3_sge_start(adap);
1288 t3_intr_enable(adap);
1289
1290 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1291 is_offload(adap) && init_tp_parity(adap) == 0)
1292 adap->flags |= TP_PARITY_INIT;
1293
1294 if (adap->flags & TP_PARITY_INIT) {
1295 t3_write_reg(adap, A_TP_INT_CAUSE,
1296 F_CMCACHEPERR | F_ARPLUTPERR);
1297 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1298 }
1299
1300 if (!(adap->flags & QUEUES_BOUND)) {
1301 int ret = bind_qsets(adap);
1302
1303 if (ret < 0) {
1304 CH_ERR(adap, "failed to bind qsets, err %d\n", ret);
1305 t3_intr_disable(adap);
1306 free_irq_resources(adap);
1307 err = ret;
1308 goto out;
1309 }
1310 adap->flags |= QUEUES_BOUND;
1311 }
1312
1313out:
1314 return err;
1315irq_err:
1316 CH_ERR(adap, "request_irq failed, err %d\n", err);
1317 goto out;
1318}
1319
1320
1321
1322
1323static void cxgb_down(struct adapter *adapter, int on_wq)
1324{
1325 t3_sge_stop(adapter);
1326 spin_lock_irq(&adapter->work_lock);
1327 t3_intr_disable(adapter);
1328 spin_unlock_irq(&adapter->work_lock);
1329
1330 free_irq_resources(adapter);
1331 quiesce_rx(adapter);
1332 t3_sge_stop(adapter);
1333 if (!on_wq)
1334 flush_workqueue(cxgb3_wq);
1335}
1336
1337static void schedule_chk_task(struct adapter *adap)
1338{
1339 unsigned int timeo;
1340
1341 timeo = adap->params.linkpoll_period ?
1342 (HZ * adap->params.linkpoll_period) / 10 :
1343 adap->params.stats_update_period * HZ;
1344 if (timeo)
1345 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1346}
1347
1348static int offload_open(struct net_device *dev)
1349{
1350 struct port_info *pi = netdev_priv(dev);
1351 struct adapter *adapter = pi->adapter;
1352 struct t3cdev *tdev = dev2t3cdev(dev);
1353 int adap_up = adapter->open_device_map & PORT_MASK;
1354 int err;
1355
1356 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1357 return 0;
1358
1359 if (!adap_up && (err = cxgb_up(adapter)) < 0)
1360 goto out;
1361
1362 t3_tp_set_offload_mode(adapter, 1);
1363 tdev->lldev = adapter->port[0];
1364 err = cxgb3_offload_activate(adapter);
1365 if (err)
1366 goto out;
1367
1368 init_port_mtus(adapter);
1369 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1370 adapter->params.b_wnd,
1371 adapter->params.rev == 0 ?
1372 adapter->port[0]->mtu : 0xffff);
1373 init_smt(adapter);
1374
1375 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1376 dev_dbg(&dev->dev, "cannot create sysfs group\n");
1377
1378
1379 cxgb3_add_clients(tdev);
1380
1381out:
1382
1383 if (err) {
1384 t3_tp_set_offload_mode(adapter, 0);
1385 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1386 cxgb3_set_dummy_ops(tdev);
1387 }
1388 return err;
1389}
1390
1391static int offload_close(struct t3cdev *tdev)
1392{
1393 struct adapter *adapter = tdev2adap(tdev);
1394 struct t3c_data *td = T3C_DATA(tdev);
1395
1396 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1397 return 0;
1398
1399
1400 cxgb3_remove_clients(tdev);
1401
1402 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
1403
1404
1405 flush_work(&td->tid_release_task);
1406
1407 tdev->lldev = NULL;
1408 cxgb3_set_dummy_ops(tdev);
1409 t3_tp_set_offload_mode(adapter, 0);
1410 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1411
1412 if (!adapter->open_device_map)
1413 cxgb_down(adapter, 0);
1414
1415 cxgb3_offload_deactivate(adapter);
1416 return 0;
1417}
1418
1419static int cxgb_open(struct net_device *dev)
1420{
1421 struct port_info *pi = netdev_priv(dev);
1422 struct adapter *adapter = pi->adapter;
1423 int other_ports = adapter->open_device_map & PORT_MASK;
1424 int err;
1425
1426 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
1427 return err;
1428
1429 set_bit(pi->port_id, &adapter->open_device_map);
1430 if (is_offload(adapter) && !ofld_disable) {
1431 err = offload_open(dev);
1432 if (err)
1433 pr_warn("Could not initialize offload capabilities\n");
1434 }
1435
1436 netif_set_real_num_tx_queues(dev, pi->nqsets);
1437 err = netif_set_real_num_rx_queues(dev, pi->nqsets);
1438 if (err)
1439 return err;
1440 link_start(dev);
1441 t3_port_intr_enable(adapter, pi->port_id);
1442 netif_tx_start_all_queues(dev);
1443 if (!other_ports)
1444 schedule_chk_task(adapter);
1445
1446 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
1447 return 0;
1448}
1449
1450static int __cxgb_close(struct net_device *dev, int on_wq)
1451{
1452 struct port_info *pi = netdev_priv(dev);
1453 struct adapter *adapter = pi->adapter;
1454
1455
1456 if (!adapter->open_device_map)
1457 return 0;
1458
1459
1460 t3_xgm_intr_disable(adapter, pi->port_id);
1461 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1462
1463 t3_port_intr_disable(adapter, pi->port_id);
1464 netif_tx_stop_all_queues(dev);
1465 pi->phy.ops->power_down(&pi->phy, 1);
1466 netif_carrier_off(dev);
1467 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
1468
1469 spin_lock_irq(&adapter->work_lock);
1470 clear_bit(pi->port_id, &adapter->open_device_map);
1471 spin_unlock_irq(&adapter->work_lock);
1472
1473 if (!(adapter->open_device_map & PORT_MASK))
1474 cancel_delayed_work_sync(&adapter->adap_check_task);
1475
1476 if (!adapter->open_device_map)
1477 cxgb_down(adapter, on_wq);
1478
1479 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
1480 return 0;
1481}
1482
1483static int cxgb_close(struct net_device *dev)
1484{
1485 return __cxgb_close(dev, 0);
1486}
1487
1488static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1489{
1490 struct port_info *pi = netdev_priv(dev);
1491 struct adapter *adapter = pi->adapter;
1492 struct net_device_stats *ns = &dev->stats;
1493 const struct mac_stats *pstats;
1494
1495 spin_lock(&adapter->stats_lock);
1496 pstats = t3_mac_update_stats(&pi->mac);
1497 spin_unlock(&adapter->stats_lock);
1498
1499 ns->tx_bytes = pstats->tx_octets;
1500 ns->tx_packets = pstats->tx_frames;
1501 ns->rx_bytes = pstats->rx_octets;
1502 ns->rx_packets = pstats->rx_frames;
1503 ns->multicast = pstats->rx_mcast_frames;
1504
1505 ns->tx_errors = pstats->tx_underrun;
1506 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1507 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1508 pstats->rx_fifo_ovfl;
1509
1510
1511 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1512 ns->rx_over_errors = 0;
1513 ns->rx_crc_errors = pstats->rx_fcs_errs;
1514 ns->rx_frame_errors = pstats->rx_symbol_errs;
1515 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1516 ns->rx_missed_errors = pstats->rx_cong_drops;
1517
1518
1519 ns->tx_aborted_errors = 0;
1520 ns->tx_carrier_errors = 0;
1521 ns->tx_fifo_errors = pstats->tx_underrun;
1522 ns->tx_heartbeat_errors = 0;
1523 ns->tx_window_errors = 0;
1524 return ns;
1525}
1526
1527static u32 get_msglevel(struct net_device *dev)
1528{
1529 struct port_info *pi = netdev_priv(dev);
1530 struct adapter *adapter = pi->adapter;
1531
1532 return adapter->msg_enable;
1533}
1534
1535static void set_msglevel(struct net_device *dev, u32 val)
1536{
1537 struct port_info *pi = netdev_priv(dev);
1538 struct adapter *adapter = pi->adapter;
1539
1540 adapter->msg_enable = val;
1541}
1542
1543static const char stats_strings[][ETH_GSTRING_LEN] = {
1544 "TxOctetsOK ",
1545 "TxFramesOK ",
1546 "TxMulticastFramesOK",
1547 "TxBroadcastFramesOK",
1548 "TxPauseFrames ",
1549 "TxUnderrun ",
1550 "TxExtUnderrun ",
1551
1552 "TxFrames64 ",
1553 "TxFrames65To127 ",
1554 "TxFrames128To255 ",
1555 "TxFrames256To511 ",
1556 "TxFrames512To1023 ",
1557 "TxFrames1024To1518 ",
1558 "TxFrames1519ToMax ",
1559
1560 "RxOctetsOK ",
1561 "RxFramesOK ",
1562 "RxMulticastFramesOK",
1563 "RxBroadcastFramesOK",
1564 "RxPauseFrames ",
1565 "RxFCSErrors ",
1566 "RxSymbolErrors ",
1567 "RxShortErrors ",
1568 "RxJabberErrors ",
1569 "RxLengthErrors ",
1570 "RxFIFOoverflow ",
1571
1572 "RxFrames64 ",
1573 "RxFrames65To127 ",
1574 "RxFrames128To255 ",
1575 "RxFrames256To511 ",
1576 "RxFrames512To1023 ",
1577 "RxFrames1024To1518 ",
1578 "RxFrames1519ToMax ",
1579
1580 "PhyFIFOErrors ",
1581 "TSO ",
1582 "VLANextractions ",
1583 "VLANinsertions ",
1584 "TxCsumOffload ",
1585 "RxCsumGood ",
1586 "LroAggregated ",
1587 "LroFlushed ",
1588 "LroNoDesc ",
1589 "RxDrops ",
1590
1591 "CheckTXEnToggled ",
1592 "CheckResets ",
1593
1594 "LinkFaults ",
1595};
1596
1597static int get_sset_count(struct net_device *dev, int sset)
1598{
1599 switch (sset) {
1600 case ETH_SS_STATS:
1601 return ARRAY_SIZE(stats_strings);
1602 default:
1603 return -EOPNOTSUPP;
1604 }
1605}
1606
1607#define T3_REGMAP_SIZE (3 * 1024)
1608
1609static int get_regs_len(struct net_device *dev)
1610{
1611 return T3_REGMAP_SIZE;
1612}
1613
1614static int get_eeprom_len(struct net_device *dev)
1615{
1616 return EEPROMSIZE;
1617}
1618
1619static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1620{
1621 struct port_info *pi = netdev_priv(dev);
1622 struct adapter *adapter = pi->adapter;
1623 u32 fw_vers = 0;
1624 u32 tp_vers = 0;
1625
1626 spin_lock(&adapter->stats_lock);
1627 t3_get_fw_version(adapter, &fw_vers);
1628 t3_get_tp_version(adapter, &tp_vers);
1629 spin_unlock(&adapter->stats_lock);
1630
1631 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1632 strlcpy(info->bus_info, pci_name(adapter->pdev),
1633 sizeof(info->bus_info));
1634 if (fw_vers)
1635 snprintf(info->fw_version, sizeof(info->fw_version),
1636 "%s %u.%u.%u TP %u.%u.%u",
1637 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1638 G_FW_VERSION_MAJOR(fw_vers),
1639 G_FW_VERSION_MINOR(fw_vers),
1640 G_FW_VERSION_MICRO(fw_vers),
1641 G_TP_VERSION_MAJOR(tp_vers),
1642 G_TP_VERSION_MINOR(tp_vers),
1643 G_TP_VERSION_MICRO(tp_vers));
1644}
1645
1646static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1647{
1648 if (stringset == ETH_SS_STATS)
1649 memcpy(data, stats_strings, sizeof(stats_strings));
1650}
1651
1652static unsigned long collect_sge_port_stats(struct adapter *adapter,
1653 struct port_info *p, int idx)
1654{
1655 int i;
1656 unsigned long tot = 0;
1657
1658 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1659 tot += adapter->sge.qs[i].port_stats[idx];
1660 return tot;
1661}
1662
1663static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1664 u64 *data)
1665{
1666 struct port_info *pi = netdev_priv(dev);
1667 struct adapter *adapter = pi->adapter;
1668 const struct mac_stats *s;
1669
1670 spin_lock(&adapter->stats_lock);
1671 s = t3_mac_update_stats(&pi->mac);
1672 spin_unlock(&adapter->stats_lock);
1673
1674 *data++ = s->tx_octets;
1675 *data++ = s->tx_frames;
1676 *data++ = s->tx_mcast_frames;
1677 *data++ = s->tx_bcast_frames;
1678 *data++ = s->tx_pause;
1679 *data++ = s->tx_underrun;
1680 *data++ = s->tx_fifo_urun;
1681
1682 *data++ = s->tx_frames_64;
1683 *data++ = s->tx_frames_65_127;
1684 *data++ = s->tx_frames_128_255;
1685 *data++ = s->tx_frames_256_511;
1686 *data++ = s->tx_frames_512_1023;
1687 *data++ = s->tx_frames_1024_1518;
1688 *data++ = s->tx_frames_1519_max;
1689
1690 *data++ = s->rx_octets;
1691 *data++ = s->rx_frames;
1692 *data++ = s->rx_mcast_frames;
1693 *data++ = s->rx_bcast_frames;
1694 *data++ = s->rx_pause;
1695 *data++ = s->rx_fcs_errs;
1696 *data++ = s->rx_symbol_errs;
1697 *data++ = s->rx_short;
1698 *data++ = s->rx_jabber;
1699 *data++ = s->rx_too_long;
1700 *data++ = s->rx_fifo_ovfl;
1701
1702 *data++ = s->rx_frames_64;
1703 *data++ = s->rx_frames_65_127;
1704 *data++ = s->rx_frames_128_255;
1705 *data++ = s->rx_frames_256_511;
1706 *data++ = s->rx_frames_512_1023;
1707 *data++ = s->rx_frames_1024_1518;
1708 *data++ = s->rx_frames_1519_max;
1709
1710 *data++ = pi->phy.fifo_errors;
1711
1712 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1713 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1714 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1715 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1716 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1717 *data++ = 0;
1718 *data++ = 0;
1719 *data++ = 0;
1720 *data++ = s->rx_cong_drops;
1721
1722 *data++ = s->num_toggled;
1723 *data++ = s->num_resets;
1724
1725 *data++ = s->link_faults;
1726}
1727
1728static inline void reg_block_dump(struct adapter *ap, void *buf,
1729 unsigned int start, unsigned int end)
1730{
1731 u32 *p = buf + start;
1732
1733 for (; start <= end; start += sizeof(u32))
1734 *p++ = t3_read_reg(ap, start);
1735}
1736
1737static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1738 void *buf)
1739{
1740 struct port_info *pi = netdev_priv(dev);
1741 struct adapter *ap = pi->adapter;
1742
1743
1744
1745
1746
1747
1748
1749 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1750
1751
1752
1753
1754
1755
1756 memset(buf, 0, T3_REGMAP_SIZE);
1757 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1758 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1759 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1760 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1761 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1762 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1763 XGM_REG(A_XGM_SERDES_STAT3, 1));
1764 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1765 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1766}
1767
1768static int restart_autoneg(struct net_device *dev)
1769{
1770 struct port_info *p = netdev_priv(dev);
1771
1772 if (!netif_running(dev))
1773 return -EAGAIN;
1774 if (p->link_config.autoneg != AUTONEG_ENABLE)
1775 return -EINVAL;
1776 p->phy.ops->autoneg_restart(&p->phy);
1777 return 0;
1778}
1779
1780static int set_phys_id(struct net_device *dev,
1781 enum ethtool_phys_id_state state)
1782{
1783 struct port_info *pi = netdev_priv(dev);
1784 struct adapter *adapter = pi->adapter;
1785
1786 switch (state) {
1787 case ETHTOOL_ID_ACTIVE:
1788 return 1;
1789
1790 case ETHTOOL_ID_OFF:
1791 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 0);
1792 break;
1793
1794 case ETHTOOL_ID_ON:
1795 case ETHTOOL_ID_INACTIVE:
1796 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1797 F_GPIO0_OUT_VAL);
1798 }
1799
1800 return 0;
1801}
1802
1803static int get_link_ksettings(struct net_device *dev,
1804 struct ethtool_link_ksettings *cmd)
1805{
1806 struct port_info *p = netdev_priv(dev);
1807 u32 supported;
1808
1809 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1810 p->link_config.supported);
1811 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1812 p->link_config.advertising);
1813
1814 if (netif_carrier_ok(dev)) {
1815 cmd->base.speed = p->link_config.speed;
1816 cmd->base.duplex = p->link_config.duplex;
1817 } else {
1818 cmd->base.speed = SPEED_UNKNOWN;
1819 cmd->base.duplex = DUPLEX_UNKNOWN;
1820 }
1821
1822 ethtool_convert_link_mode_to_legacy_u32(&supported,
1823 cmd->link_modes.supported);
1824
1825 cmd->base.port = (supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1826 cmd->base.phy_address = p->phy.mdio.prtad;
1827 cmd->base.autoneg = p->link_config.autoneg;
1828 return 0;
1829}
1830
1831static int speed_duplex_to_caps(int speed, int duplex)
1832{
1833 int cap = 0;
1834
1835 switch (speed) {
1836 case SPEED_10:
1837 if (duplex == DUPLEX_FULL)
1838 cap = SUPPORTED_10baseT_Full;
1839 else
1840 cap = SUPPORTED_10baseT_Half;
1841 break;
1842 case SPEED_100:
1843 if (duplex == DUPLEX_FULL)
1844 cap = SUPPORTED_100baseT_Full;
1845 else
1846 cap = SUPPORTED_100baseT_Half;
1847 break;
1848 case SPEED_1000:
1849 if (duplex == DUPLEX_FULL)
1850 cap = SUPPORTED_1000baseT_Full;
1851 else
1852 cap = SUPPORTED_1000baseT_Half;
1853 break;
1854 case SPEED_10000:
1855 if (duplex == DUPLEX_FULL)
1856 cap = SUPPORTED_10000baseT_Full;
1857 }
1858 return cap;
1859}
1860
1861#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1862 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1863 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1864 ADVERTISED_10000baseT_Full)
1865
1866static int set_link_ksettings(struct net_device *dev,
1867 const struct ethtool_link_ksettings *cmd)
1868{
1869 struct port_info *p = netdev_priv(dev);
1870 struct link_config *lc = &p->link_config;
1871 u32 advertising;
1872
1873 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1874 cmd->link_modes.advertising);
1875
1876 if (!(lc->supported & SUPPORTED_Autoneg)) {
1877
1878
1879
1880
1881 if (cmd->base.autoneg == AUTONEG_DISABLE) {
1882 u32 speed = cmd->base.speed;
1883 int cap = speed_duplex_to_caps(speed, cmd->base.duplex);
1884 if (lc->supported & cap)
1885 return 0;
1886 }
1887 return -EINVAL;
1888 }
1889
1890 if (cmd->base.autoneg == AUTONEG_DISABLE) {
1891 u32 speed = cmd->base.speed;
1892 int cap = speed_duplex_to_caps(speed, cmd->base.duplex);
1893
1894 if (!(lc->supported & cap) || (speed == SPEED_1000))
1895 return -EINVAL;
1896 lc->requested_speed = speed;
1897 lc->requested_duplex = cmd->base.duplex;
1898 lc->advertising = 0;
1899 } else {
1900 advertising &= ADVERTISED_MASK;
1901 advertising &= lc->supported;
1902 if (!advertising)
1903 return -EINVAL;
1904 lc->requested_speed = SPEED_INVALID;
1905 lc->requested_duplex = DUPLEX_INVALID;
1906 lc->advertising = advertising | ADVERTISED_Autoneg;
1907 }
1908 lc->autoneg = cmd->base.autoneg;
1909 if (netif_running(dev))
1910 t3_link_start(&p->phy, &p->mac, lc);
1911 return 0;
1912}
1913
1914static void get_pauseparam(struct net_device *dev,
1915 struct ethtool_pauseparam *epause)
1916{
1917 struct port_info *p = netdev_priv(dev);
1918
1919 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1920 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1921 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1922}
1923
1924static int set_pauseparam(struct net_device *dev,
1925 struct ethtool_pauseparam *epause)
1926{
1927 struct port_info *p = netdev_priv(dev);
1928 struct link_config *lc = &p->link_config;
1929
1930 if (epause->autoneg == AUTONEG_DISABLE)
1931 lc->requested_fc = 0;
1932 else if (lc->supported & SUPPORTED_Autoneg)
1933 lc->requested_fc = PAUSE_AUTONEG;
1934 else
1935 return -EINVAL;
1936
1937 if (epause->rx_pause)
1938 lc->requested_fc |= PAUSE_RX;
1939 if (epause->tx_pause)
1940 lc->requested_fc |= PAUSE_TX;
1941 if (lc->autoneg == AUTONEG_ENABLE) {
1942 if (netif_running(dev))
1943 t3_link_start(&p->phy, &p->mac, lc);
1944 } else {
1945 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1946 if (netif_running(dev))
1947 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1948 }
1949 return 0;
1950}
1951
1952static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1953{
1954 struct port_info *pi = netdev_priv(dev);
1955 struct adapter *adapter = pi->adapter;
1956 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
1957
1958 e->rx_max_pending = MAX_RX_BUFFERS;
1959 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1960 e->tx_max_pending = MAX_TXQ_ENTRIES;
1961
1962 e->rx_pending = q->fl_size;
1963 e->rx_mini_pending = q->rspq_size;
1964 e->rx_jumbo_pending = q->jumbo_size;
1965 e->tx_pending = q->txq_size[0];
1966}
1967
1968static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1969{
1970 struct port_info *pi = netdev_priv(dev);
1971 struct adapter *adapter = pi->adapter;
1972 struct qset_params *q;
1973 int i;
1974
1975 if (e->rx_pending > MAX_RX_BUFFERS ||
1976 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1977 e->tx_pending > MAX_TXQ_ENTRIES ||
1978 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1979 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1980 e->rx_pending < MIN_FL_ENTRIES ||
1981 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1982 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1983 return -EINVAL;
1984
1985 if (adapter->flags & FULL_INIT_DONE)
1986 return -EBUSY;
1987
1988 q = &adapter->params.sge.qset[pi->first_qset];
1989 for (i = 0; i < pi->nqsets; ++i, ++q) {
1990 q->rspq_size = e->rx_mini_pending;
1991 q->fl_size = e->rx_pending;
1992 q->jumbo_size = e->rx_jumbo_pending;
1993 q->txq_size[0] = e->tx_pending;
1994 q->txq_size[1] = e->tx_pending;
1995 q->txq_size[2] = e->tx_pending;
1996 }
1997 return 0;
1998}
1999
2000static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c,
2001 struct kernel_ethtool_coalesce *kernel_coal,
2002 struct netlink_ext_ack *extack)
2003{
2004 struct port_info *pi = netdev_priv(dev);
2005 struct adapter *adapter = pi->adapter;
2006 struct qset_params *qsp;
2007 struct sge_qset *qs;
2008 int i;
2009
2010 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
2011 return -EINVAL;
2012
2013 for (i = 0; i < pi->nqsets; i++) {
2014 qsp = &adapter->params.sge.qset[i];
2015 qs = &adapter->sge.qs[i];
2016 qsp->coalesce_usecs = c->rx_coalesce_usecs;
2017 t3_update_qset_coalesce(qs, qsp);
2018 }
2019
2020 return 0;
2021}
2022
2023static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c,
2024 struct kernel_ethtool_coalesce *kernel_coal,
2025 struct netlink_ext_ack *extack)
2026{
2027 struct port_info *pi = netdev_priv(dev);
2028 struct adapter *adapter = pi->adapter;
2029 struct qset_params *q = adapter->params.sge.qset;
2030
2031 c->rx_coalesce_usecs = q->coalesce_usecs;
2032 return 0;
2033}
2034
2035static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2036 u8 * data)
2037{
2038 struct port_info *pi = netdev_priv(dev);
2039 struct adapter *adapter = pi->adapter;
2040 int cnt;
2041
2042 e->magic = EEPROM_MAGIC;
2043 cnt = pci_read_vpd(adapter->pdev, e->offset, e->len, data);
2044 if (cnt < 0)
2045 return cnt;
2046
2047 e->len = cnt;
2048
2049 return 0;
2050}
2051
2052static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2053 u8 * data)
2054{
2055 struct port_info *pi = netdev_priv(dev);
2056 struct adapter *adapter = pi->adapter;
2057 u32 aligned_offset, aligned_len;
2058 u8 *buf;
2059 int err;
2060
2061 if (eeprom->magic != EEPROM_MAGIC)
2062 return -EINVAL;
2063
2064 aligned_offset = eeprom->offset & ~3;
2065 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2066
2067 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2068 buf = kmalloc(aligned_len, GFP_KERNEL);
2069 if (!buf)
2070 return -ENOMEM;
2071 err = pci_read_vpd(adapter->pdev, aligned_offset, aligned_len,
2072 buf);
2073 if (err < 0)
2074 goto out;
2075 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2076 } else
2077 buf = data;
2078
2079 err = t3_seeprom_wp(adapter, 0);
2080 if (err)
2081 goto out;
2082
2083 err = pci_write_vpd(adapter->pdev, aligned_offset, aligned_len, buf);
2084 if (err >= 0)
2085 err = t3_seeprom_wp(adapter, 1);
2086out:
2087 if (buf != data)
2088 kfree(buf);
2089 return err < 0 ? err : 0;
2090}
2091
2092static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2093{
2094 wol->supported = 0;
2095 wol->wolopts = 0;
2096 memset(&wol->sopass, 0, sizeof(wol->sopass));
2097}
2098
2099static const struct ethtool_ops cxgb_ethtool_ops = {
2100 .get_drvinfo = get_drvinfo,
2101 .get_msglevel = get_msglevel,
2102 .set_msglevel = set_msglevel,
2103 .get_ringparam = get_sge_param,
2104 .set_ringparam = set_sge_param,
2105 .get_coalesce = get_coalesce,
2106 .set_coalesce = set_coalesce,
2107 .get_eeprom_len = get_eeprom_len,
2108 .get_eeprom = get_eeprom,
2109 .set_eeprom = set_eeprom,
2110 .get_pauseparam = get_pauseparam,
2111 .set_pauseparam = set_pauseparam,
2112 .get_link = ethtool_op_get_link,
2113 .get_strings = get_strings,
2114 .set_phys_id = set_phys_id,
2115 .nway_reset = restart_autoneg,
2116 .get_sset_count = get_sset_count,
2117 .get_ethtool_stats = get_stats,
2118 .get_regs_len = get_regs_len,
2119 .get_regs = get_regs,
2120 .get_wol = get_wol,
2121 .get_link_ksettings = get_link_ksettings,
2122 .set_link_ksettings = set_link_ksettings,
2123};
2124
2125static int in_range(int val, int lo, int hi)
2126{
2127 return val < 0 || (val <= hi && val >= lo);
2128}
2129
2130static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2131{
2132 struct port_info *pi = netdev_priv(dev);
2133 struct adapter *adapter = pi->adapter;
2134 u32 cmd;
2135 int ret;
2136
2137 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2138 return -EFAULT;
2139
2140 switch (cmd) {
2141 case CHELSIO_SET_QSET_PARAMS:{
2142 int i;
2143 struct qset_params *q;
2144 struct ch_qset_params t;
2145 int q1 = pi->first_qset;
2146 int nqsets = pi->nqsets;
2147
2148 if (!capable(CAP_NET_ADMIN))
2149 return -EPERM;
2150 if (copy_from_user(&t, useraddr, sizeof(t)))
2151 return -EFAULT;
2152 if (t.qset_idx >= SGE_QSETS)
2153 return -EINVAL;
2154 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
2155 !in_range(t.cong_thres, 0, 255) ||
2156 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2157 MAX_TXQ_ENTRIES) ||
2158 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2159 MAX_TXQ_ENTRIES) ||
2160 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2161 MAX_CTRL_TXQ_ENTRIES) ||
2162 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2163 MAX_RX_BUFFERS) ||
2164 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2165 MAX_RX_JUMBO_BUFFERS) ||
2166 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2167 MAX_RSPQ_ENTRIES))
2168 return -EINVAL;
2169
2170 if ((adapter->flags & FULL_INIT_DONE) &&
2171 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2172 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2173 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2174 t.polling >= 0 || t.cong_thres >= 0))
2175 return -EBUSY;
2176
2177
2178 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2179 q1 = 0;
2180 for_each_port(adapter, i) {
2181 pi = adap2pinfo(adapter, i);
2182 nqsets += pi->first_qset + pi->nqsets;
2183 }
2184 }
2185
2186 if (t.qset_idx < q1)
2187 return -EINVAL;
2188 if (t.qset_idx > q1 + nqsets - 1)
2189 return -EINVAL;
2190
2191 q = &adapter->params.sge.qset[t.qset_idx];
2192
2193 if (t.rspq_size >= 0)
2194 q->rspq_size = t.rspq_size;
2195 if (t.fl_size[0] >= 0)
2196 q->fl_size = t.fl_size[0];
2197 if (t.fl_size[1] >= 0)
2198 q->jumbo_size = t.fl_size[1];
2199 if (t.txq_size[0] >= 0)
2200 q->txq_size[0] = t.txq_size[0];
2201 if (t.txq_size[1] >= 0)
2202 q->txq_size[1] = t.txq_size[1];
2203 if (t.txq_size[2] >= 0)
2204 q->txq_size[2] = t.txq_size[2];
2205 if (t.cong_thres >= 0)
2206 q->cong_thres = t.cong_thres;
2207 if (t.intr_lat >= 0) {
2208 struct sge_qset *qs =
2209 &adapter->sge.qs[t.qset_idx];
2210
2211 q->coalesce_usecs = t.intr_lat;
2212 t3_update_qset_coalesce(qs, q);
2213 }
2214 if (t.polling >= 0) {
2215 if (adapter->flags & USING_MSIX)
2216 q->polling = t.polling;
2217 else {
2218
2219 if (adapter->params.rev == 0 &&
2220 !(adapter->flags & USING_MSI))
2221 t.polling = 0;
2222
2223 for (i = 0; i < SGE_QSETS; i++) {
2224 q = &adapter->params.sge.
2225 qset[i];
2226 q->polling = t.polling;
2227 }
2228 }
2229 }
2230
2231 if (t.lro >= 0) {
2232 if (t.lro)
2233 dev->wanted_features |= NETIF_F_GRO;
2234 else
2235 dev->wanted_features &= ~NETIF_F_GRO;
2236 netdev_update_features(dev);
2237 }
2238
2239 break;
2240 }
2241 case CHELSIO_GET_QSET_PARAMS:{
2242 struct qset_params *q;
2243 struct ch_qset_params t;
2244 int q1 = pi->first_qset;
2245 int nqsets = pi->nqsets;
2246 int i;
2247
2248 if (copy_from_user(&t, useraddr, sizeof(t)))
2249 return -EFAULT;
2250
2251
2252 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2253 q1 = 0;
2254 for_each_port(adapter, i) {
2255 pi = adap2pinfo(adapter, i);
2256 nqsets = pi->first_qset + pi->nqsets;
2257 }
2258 }
2259
2260 if (t.qset_idx >= nqsets)
2261 return -EINVAL;
2262 t.qset_idx = array_index_nospec(t.qset_idx, nqsets);
2263
2264 q = &adapter->params.sge.qset[q1 + t.qset_idx];
2265 t.rspq_size = q->rspq_size;
2266 t.txq_size[0] = q->txq_size[0];
2267 t.txq_size[1] = q->txq_size[1];
2268 t.txq_size[2] = q->txq_size[2];
2269 t.fl_size[0] = q->fl_size;
2270 t.fl_size[1] = q->jumbo_size;
2271 t.polling = q->polling;
2272 t.lro = !!(dev->features & NETIF_F_GRO);
2273 t.intr_lat = q->coalesce_usecs;
2274 t.cong_thres = q->cong_thres;
2275 t.qnum = q1;
2276
2277 if (adapter->flags & USING_MSIX)
2278 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2279 else
2280 t.vector = adapter->pdev->irq;
2281
2282 if (copy_to_user(useraddr, &t, sizeof(t)))
2283 return -EFAULT;
2284 break;
2285 }
2286 case CHELSIO_SET_QSET_NUM:{
2287 struct ch_reg edata;
2288 unsigned int i, first_qset = 0, other_qsets = 0;
2289
2290 if (!capable(CAP_NET_ADMIN))
2291 return -EPERM;
2292 if (adapter->flags & FULL_INIT_DONE)
2293 return -EBUSY;
2294 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2295 return -EFAULT;
2296 if (edata.val < 1 ||
2297 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2298 return -EINVAL;
2299
2300 for_each_port(adapter, i)
2301 if (adapter->port[i] && adapter->port[i] != dev)
2302 other_qsets += adap2pinfo(adapter, i)->nqsets;
2303
2304 if (edata.val + other_qsets > SGE_QSETS)
2305 return -EINVAL;
2306
2307 pi->nqsets = edata.val;
2308
2309 for_each_port(adapter, i)
2310 if (adapter->port[i]) {
2311 pi = adap2pinfo(adapter, i);
2312 pi->first_qset = first_qset;
2313 first_qset += pi->nqsets;
2314 }
2315 break;
2316 }
2317 case CHELSIO_GET_QSET_NUM:{
2318 struct ch_reg edata;
2319
2320 memset(&edata, 0, sizeof(struct ch_reg));
2321
2322 edata.cmd = CHELSIO_GET_QSET_NUM;
2323 edata.val = pi->nqsets;
2324 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2325 return -EFAULT;
2326 break;
2327 }
2328 case CHELSIO_LOAD_FW:{
2329 u8 *fw_data;
2330 struct ch_mem_range t;
2331
2332 if (!capable(CAP_SYS_RAWIO))
2333 return -EPERM;
2334 if (copy_from_user(&t, useraddr, sizeof(t)))
2335 return -EFAULT;
2336
2337 fw_data = memdup_user(useraddr + sizeof(t), t.len);
2338 if (IS_ERR(fw_data))
2339 return PTR_ERR(fw_data);
2340
2341 ret = t3_load_fw(adapter, fw_data, t.len);
2342 kfree(fw_data);
2343 if (ret)
2344 return ret;
2345 break;
2346 }
2347 case CHELSIO_SETMTUTAB:{
2348 struct ch_mtus m;
2349 int i;
2350
2351 if (!is_offload(adapter))
2352 return -EOPNOTSUPP;
2353 if (!capable(CAP_NET_ADMIN))
2354 return -EPERM;
2355 if (offload_running(adapter))
2356 return -EBUSY;
2357 if (copy_from_user(&m, useraddr, sizeof(m)))
2358 return -EFAULT;
2359 if (m.nmtus != NMTUS)
2360 return -EINVAL;
2361 if (m.mtus[0] < 81)
2362 return -EINVAL;
2363
2364
2365 for (i = 1; i < NMTUS; ++i)
2366 if (m.mtus[i] < m.mtus[i - 1])
2367 return -EINVAL;
2368
2369 memcpy(adapter->params.mtus, m.mtus,
2370 sizeof(adapter->params.mtus));
2371 break;
2372 }
2373 case CHELSIO_GET_PM:{
2374 struct tp_params *p = &adapter->params.tp;
2375 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2376
2377 if (!is_offload(adapter))
2378 return -EOPNOTSUPP;
2379 m.tx_pg_sz = p->tx_pg_size;
2380 m.tx_num_pg = p->tx_num_pgs;
2381 m.rx_pg_sz = p->rx_pg_size;
2382 m.rx_num_pg = p->rx_num_pgs;
2383 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2384 if (copy_to_user(useraddr, &m, sizeof(m)))
2385 return -EFAULT;
2386 break;
2387 }
2388 case CHELSIO_SET_PM:{
2389 struct ch_pm m;
2390 struct tp_params *p = &adapter->params.tp;
2391
2392 if (!is_offload(adapter))
2393 return -EOPNOTSUPP;
2394 if (!capable(CAP_NET_ADMIN))
2395 return -EPERM;
2396 if (adapter->flags & FULL_INIT_DONE)
2397 return -EBUSY;
2398 if (copy_from_user(&m, useraddr, sizeof(m)))
2399 return -EFAULT;
2400 if (!is_power_of_2(m.rx_pg_sz) ||
2401 !is_power_of_2(m.tx_pg_sz))
2402 return -EINVAL;
2403 if (!(m.rx_pg_sz & 0x14000))
2404 return -EINVAL;
2405 if (!(m.tx_pg_sz & 0x1554000))
2406 return -EINVAL;
2407 if (m.tx_num_pg == -1)
2408 m.tx_num_pg = p->tx_num_pgs;
2409 if (m.rx_num_pg == -1)
2410 m.rx_num_pg = p->rx_num_pgs;
2411 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2412 return -EINVAL;
2413 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2414 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2415 return -EINVAL;
2416 p->rx_pg_size = m.rx_pg_sz;
2417 p->tx_pg_size = m.tx_pg_sz;
2418 p->rx_num_pgs = m.rx_num_pg;
2419 p->tx_num_pgs = m.tx_num_pg;
2420 break;
2421 }
2422 case CHELSIO_GET_MEM:{
2423 struct ch_mem_range t;
2424 struct mc7 *mem;
2425 u64 buf[32];
2426
2427 if (!is_offload(adapter))
2428 return -EOPNOTSUPP;
2429 if (!(adapter->flags & FULL_INIT_DONE))
2430 return -EIO;
2431 if (copy_from_user(&t, useraddr, sizeof(t)))
2432 return -EFAULT;
2433 if ((t.addr & 7) || (t.len & 7))
2434 return -EINVAL;
2435 if (t.mem_id == MEM_CM)
2436 mem = &adapter->cm;
2437 else if (t.mem_id == MEM_PMRX)
2438 mem = &adapter->pmrx;
2439 else if (t.mem_id == MEM_PMTX)
2440 mem = &adapter->pmtx;
2441 else
2442 return -EINVAL;
2443
2444
2445
2446
2447
2448
2449 t.version = 3 | (adapter->params.rev << 10);
2450 if (copy_to_user(useraddr, &t, sizeof(t)))
2451 return -EFAULT;
2452
2453
2454
2455
2456
2457 useraddr += sizeof(t);
2458 while (t.len) {
2459 unsigned int chunk =
2460 min_t(unsigned int, t.len, sizeof(buf));
2461
2462 ret =
2463 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2464 buf);
2465 if (ret)
2466 return ret;
2467 if (copy_to_user(useraddr, buf, chunk))
2468 return -EFAULT;
2469 useraddr += chunk;
2470 t.addr += chunk;
2471 t.len -= chunk;
2472 }
2473 break;
2474 }
2475 case CHELSIO_SET_TRACE_FILTER:{
2476 struct ch_trace t;
2477 const struct trace_params *tp;
2478
2479 if (!capable(CAP_NET_ADMIN))
2480 return -EPERM;
2481 if (!offload_running(adapter))
2482 return -EAGAIN;
2483 if (copy_from_user(&t, useraddr, sizeof(t)))
2484 return -EFAULT;
2485
2486 tp = (const struct trace_params *)&t.sip;
2487 if (t.config_tx)
2488 t3_config_trace_filter(adapter, tp, 0,
2489 t.invert_match,
2490 t.trace_tx);
2491 if (t.config_rx)
2492 t3_config_trace_filter(adapter, tp, 1,
2493 t.invert_match,
2494 t.trace_rx);
2495 break;
2496 }
2497 default:
2498 return -EOPNOTSUPP;
2499 }
2500 return 0;
2501}
2502
2503static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2504{
2505 struct mii_ioctl_data *data = if_mii(req);
2506 struct port_info *pi = netdev_priv(dev);
2507 struct adapter *adapter = pi->adapter;
2508
2509 switch (cmd) {
2510 case SIOCGMIIREG:
2511 case SIOCSMIIREG:
2512
2513 if (is_10G(adapter) &&
2514 !mdio_phy_id_is_c45(data->phy_id) &&
2515 (data->phy_id & 0x1f00) &&
2516 !(data->phy_id & 0xe0e0))
2517 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2518 data->phy_id & 0x1f);
2519
2520 case SIOCGMIIPHY:
2521 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
2522 case SIOCCHIOCTL:
2523 return cxgb_extension_ioctl(dev, req->ifr_data);
2524 default:
2525 return -EOPNOTSUPP;
2526 }
2527}
2528
2529static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2530{
2531 struct port_info *pi = netdev_priv(dev);
2532 struct adapter *adapter = pi->adapter;
2533 int ret;
2534
2535 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2536 return ret;
2537 dev->mtu = new_mtu;
2538 init_port_mtus(adapter);
2539 if (adapter->params.rev == 0 && offload_running(adapter))
2540 t3_load_mtus(adapter, adapter->params.mtus,
2541 adapter->params.a_wnd, adapter->params.b_wnd,
2542 adapter->port[0]->mtu);
2543 return 0;
2544}
2545
2546static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2547{
2548 struct port_info *pi = netdev_priv(dev);
2549 struct adapter *adapter = pi->adapter;
2550 struct sockaddr *addr = p;
2551
2552 if (!is_valid_ether_addr(addr->sa_data))
2553 return -EADDRNOTAVAIL;
2554
2555 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2556 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
2557 if (offload_running(adapter))
2558 write_smt_entry(adapter, pi->port_id);
2559 return 0;
2560}
2561
2562static netdev_features_t cxgb_fix_features(struct net_device *dev,
2563 netdev_features_t features)
2564{
2565
2566
2567
2568
2569 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2570 features |= NETIF_F_HW_VLAN_CTAG_TX;
2571 else
2572 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2573
2574 return features;
2575}
2576
2577static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2578{
2579 netdev_features_t changed = dev->features ^ features;
2580
2581 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2582 cxgb_vlan_mode(dev, features);
2583
2584 return 0;
2585}
2586
2587#ifdef CONFIG_NET_POLL_CONTROLLER
2588static void cxgb_netpoll(struct net_device *dev)
2589{
2590 struct port_info *pi = netdev_priv(dev);
2591 struct adapter *adapter = pi->adapter;
2592 int qidx;
2593
2594 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2595 struct sge_qset *qs = &adapter->sge.qs[qidx];
2596 void *source;
2597
2598 if (adapter->flags & USING_MSIX)
2599 source = qs;
2600 else
2601 source = adapter;
2602
2603 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2604 }
2605}
2606#endif
2607
2608
2609
2610
2611static void mac_stats_update(struct adapter *adapter)
2612{
2613 int i;
2614
2615 for_each_port(adapter, i) {
2616 struct net_device *dev = adapter->port[i];
2617 struct port_info *p = netdev_priv(dev);
2618
2619 if (netif_running(dev)) {
2620 spin_lock(&adapter->stats_lock);
2621 t3_mac_update_stats(&p->mac);
2622 spin_unlock(&adapter->stats_lock);
2623 }
2624 }
2625}
2626
2627static void check_link_status(struct adapter *adapter)
2628{
2629 int i;
2630
2631 for_each_port(adapter, i) {
2632 struct net_device *dev = adapter->port[i];
2633 struct port_info *p = netdev_priv(dev);
2634 int link_fault;
2635
2636 spin_lock_irq(&adapter->work_lock);
2637 link_fault = p->link_fault;
2638 spin_unlock_irq(&adapter->work_lock);
2639
2640 if (link_fault) {
2641 t3_link_fault(adapter, i);
2642 continue;
2643 }
2644
2645 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2646 t3_xgm_intr_disable(adapter, i);
2647 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2648
2649 t3_link_changed(adapter, i);
2650 t3_xgm_intr_enable(adapter, i);
2651 }
2652 }
2653}
2654
2655static void check_t3b2_mac(struct adapter *adapter)
2656{
2657 int i;
2658
2659 if (!rtnl_trylock())
2660 return;
2661
2662 for_each_port(adapter, i) {
2663 struct net_device *dev = adapter->port[i];
2664 struct port_info *p = netdev_priv(dev);
2665 int status;
2666
2667 if (!netif_running(dev))
2668 continue;
2669
2670 status = 0;
2671 if (netif_running(dev) && netif_carrier_ok(dev))
2672 status = t3b2_mac_watchdog_task(&p->mac);
2673 if (status == 1)
2674 p->mac.stats.num_toggled++;
2675 else if (status == 2) {
2676 struct cmac *mac = &p->mac;
2677
2678 t3_mac_set_mtu(mac, dev->mtu);
2679 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
2680 cxgb_set_rxmode(dev);
2681 t3_link_start(&p->phy, mac, &p->link_config);
2682 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2683 t3_port_intr_enable(adapter, p->port_id);
2684 p->mac.stats.num_resets++;
2685 }
2686 }
2687 rtnl_unlock();
2688}
2689
2690
2691static void t3_adap_check_task(struct work_struct *work)
2692{
2693 struct adapter *adapter = container_of(work, struct adapter,
2694 adap_check_task.work);
2695 const struct adapter_params *p = &adapter->params;
2696 int port;
2697 unsigned int v, status, reset;
2698
2699 adapter->check_task_cnt++;
2700
2701 check_link_status(adapter);
2702
2703
2704 if (!p->linkpoll_period ||
2705 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2706 p->stats_update_period) {
2707 mac_stats_update(adapter);
2708 adapter->check_task_cnt = 0;
2709 }
2710
2711 if (p->rev == T3_REV_B2)
2712 check_t3b2_mac(adapter);
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722 for_each_port(adapter, port) {
2723 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2724 u32 cause;
2725
2726 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2727 reset = 0;
2728 if (cause & F_RXFIFO_OVERFLOW) {
2729 mac->stats.rx_fifo_ovfl++;
2730 reset |= F_RXFIFO_OVERFLOW;
2731 }
2732
2733 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2734 }
2735
2736
2737
2738
2739 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2740 reset = 0;
2741
2742 if (status & F_FLEMPTY) {
2743 struct sge_qset *qs = &adapter->sge.qs[0];
2744 int i = 0;
2745
2746 reset |= F_FLEMPTY;
2747
2748 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2749 0xffff;
2750
2751 while (v) {
2752 qs->fl[i].empty += (v & 1);
2753 if (i)
2754 qs++;
2755 i ^= 1;
2756 v >>= 1;
2757 }
2758 }
2759
2760 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2761
2762
2763 spin_lock_irq(&adapter->work_lock);
2764 if (adapter->open_device_map & PORT_MASK)
2765 schedule_chk_task(adapter);
2766 spin_unlock_irq(&adapter->work_lock);
2767}
2768
2769static void db_full_task(struct work_struct *work)
2770{
2771 struct adapter *adapter = container_of(work, struct adapter,
2772 db_full_task);
2773
2774 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2775}
2776
2777static void db_empty_task(struct work_struct *work)
2778{
2779 struct adapter *adapter = container_of(work, struct adapter,
2780 db_empty_task);
2781
2782 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2783}
2784
2785static void db_drop_task(struct work_struct *work)
2786{
2787 struct adapter *adapter = container_of(work, struct adapter,
2788 db_drop_task);
2789 unsigned long delay = 1000;
2790 unsigned short r;
2791
2792 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2793
2794
2795
2796
2797
2798 get_random_bytes(&r, 2);
2799 delay += r & 1023;
2800 set_current_state(TASK_UNINTERRUPTIBLE);
2801 schedule_timeout(usecs_to_jiffies(delay));
2802 ring_dbs(adapter);
2803}
2804
2805
2806
2807
2808static void ext_intr_task(struct work_struct *work)
2809{
2810 struct adapter *adapter = container_of(work, struct adapter,
2811 ext_intr_handler_task);
2812 int i;
2813
2814
2815 for_each_port(adapter, i) {
2816 struct net_device *dev = adapter->port[i];
2817 struct port_info *p = netdev_priv(dev);
2818
2819 t3_xgm_intr_disable(adapter, i);
2820 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2821 }
2822
2823
2824 t3_phy_intr_handler(adapter);
2825
2826 for_each_port(adapter, i)
2827 t3_xgm_intr_enable(adapter, i);
2828
2829
2830 spin_lock_irq(&adapter->work_lock);
2831 if (adapter->slow_intr_mask) {
2832 adapter->slow_intr_mask |= F_T3DBG;
2833 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2834 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2835 adapter->slow_intr_mask);
2836 }
2837 spin_unlock_irq(&adapter->work_lock);
2838}
2839
2840
2841
2842
2843void t3_os_ext_intr_handler(struct adapter *adapter)
2844{
2845
2846
2847
2848
2849
2850
2851 spin_lock(&adapter->work_lock);
2852 if (adapter->slow_intr_mask) {
2853 adapter->slow_intr_mask &= ~F_T3DBG;
2854 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2855 adapter->slow_intr_mask);
2856 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2857 }
2858 spin_unlock(&adapter->work_lock);
2859}
2860
2861void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2862{
2863 struct net_device *netdev = adapter->port[port_id];
2864 struct port_info *pi = netdev_priv(netdev);
2865
2866 spin_lock(&adapter->work_lock);
2867 pi->link_fault = 1;
2868 spin_unlock(&adapter->work_lock);
2869}
2870
2871static int t3_adapter_error(struct adapter *adapter, int reset, int on_wq)
2872{
2873 int i, ret = 0;
2874
2875 if (is_offload(adapter) &&
2876 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2877 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2878 offload_close(&adapter->tdev);
2879 }
2880
2881
2882 for_each_port(adapter, i) {
2883 struct net_device *netdev = adapter->port[i];
2884
2885 if (netif_running(netdev))
2886 __cxgb_close(netdev, on_wq);
2887 }
2888
2889
2890 t3_stop_sge_timers(adapter);
2891
2892 adapter->flags &= ~FULL_INIT_DONE;
2893
2894 if (reset)
2895 ret = t3_reset_adapter(adapter);
2896
2897 pci_disable_device(adapter->pdev);
2898
2899 return ret;
2900}
2901
2902static int t3_reenable_adapter(struct adapter *adapter)
2903{
2904 if (pci_enable_device(adapter->pdev)) {
2905 dev_err(&adapter->pdev->dev,
2906 "Cannot re-enable PCI device after reset.\n");
2907 goto err;
2908 }
2909 pci_set_master(adapter->pdev);
2910 pci_restore_state(adapter->pdev);
2911 pci_save_state(adapter->pdev);
2912
2913
2914 t3_free_sge_resources(adapter);
2915
2916 if (t3_replay_prep_adapter(adapter))
2917 goto err;
2918
2919 return 0;
2920err:
2921 return -1;
2922}
2923
2924static void t3_resume_ports(struct adapter *adapter)
2925{
2926 int i;
2927
2928
2929 for_each_port(adapter, i) {
2930 struct net_device *netdev = adapter->port[i];
2931
2932 if (netif_running(netdev)) {
2933 if (cxgb_open(netdev)) {
2934 dev_err(&adapter->pdev->dev,
2935 "can't bring device back up"
2936 " after reset\n");
2937 continue;
2938 }
2939 }
2940 }
2941
2942 if (is_offload(adapter) && !ofld_disable)
2943 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
2944}
2945
2946
2947
2948
2949
2950static void fatal_error_task(struct work_struct *work)
2951{
2952 struct adapter *adapter = container_of(work, struct adapter,
2953 fatal_error_handler_task);
2954 int err = 0;
2955
2956 rtnl_lock();
2957 err = t3_adapter_error(adapter, 1, 1);
2958 if (!err)
2959 err = t3_reenable_adapter(adapter);
2960 if (!err)
2961 t3_resume_ports(adapter);
2962
2963 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2964 rtnl_unlock();
2965}
2966
2967void t3_fatal_err(struct adapter *adapter)
2968{
2969 unsigned int fw_status[4];
2970
2971 if (adapter->flags & FULL_INIT_DONE) {
2972 t3_sge_stop(adapter);
2973 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2974 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2975 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2976 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
2977
2978 spin_lock(&adapter->work_lock);
2979 t3_intr_disable(adapter);
2980 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2981 spin_unlock(&adapter->work_lock);
2982 }
2983 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2984 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2985 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2986 fw_status[0], fw_status[1],
2987 fw_status[2], fw_status[3]);
2988}
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2999 pci_channel_state_t state)
3000{
3001 struct adapter *adapter = pci_get_drvdata(pdev);
3002
3003 if (state == pci_channel_io_perm_failure)
3004 return PCI_ERS_RESULT_DISCONNECT;
3005
3006 t3_adapter_error(adapter, 0, 0);
3007
3008
3009 return PCI_ERS_RESULT_NEED_RESET;
3010}
3011
3012
3013
3014
3015
3016
3017
3018static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3019{
3020 struct adapter *adapter = pci_get_drvdata(pdev);
3021
3022 if (!t3_reenable_adapter(adapter))
3023 return PCI_ERS_RESULT_RECOVERED;
3024
3025 return PCI_ERS_RESULT_DISCONNECT;
3026}
3027
3028
3029
3030
3031
3032
3033
3034
3035static void t3_io_resume(struct pci_dev *pdev)
3036{
3037 struct adapter *adapter = pci_get_drvdata(pdev);
3038
3039 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3040 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3041
3042 rtnl_lock();
3043 t3_resume_ports(adapter);
3044 rtnl_unlock();
3045}
3046
3047static const struct pci_error_handlers t3_err_handler = {
3048 .error_detected = t3_io_error_detected,
3049 .slot_reset = t3_io_slot_reset,
3050 .resume = t3_io_resume,
3051};
3052
3053
3054
3055
3056
3057
3058static void set_nqsets(struct adapter *adap)
3059{
3060 int i, j = 0;
3061 int num_cpus = netif_get_num_default_rss_queues();
3062 int hwports = adap->params.nports;
3063 int nqsets = adap->msix_nvectors - 1;
3064
3065 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
3066 if (hwports == 2 &&
3067 (hwports * nqsets > SGE_QSETS ||
3068 num_cpus >= nqsets / hwports))
3069 nqsets /= hwports;
3070 if (nqsets > num_cpus)
3071 nqsets = num_cpus;
3072 if (nqsets < 1 || hwports == 4)
3073 nqsets = 1;
3074 } else
3075 nqsets = 1;
3076
3077 for_each_port(adap, i) {
3078 struct port_info *pi = adap2pinfo(adap, i);
3079
3080 pi->first_qset = j;
3081 pi->nqsets = nqsets;
3082 j = pi->first_qset + nqsets;
3083
3084 dev_info(&adap->pdev->dev,
3085 "Port %d using %d queue sets.\n", i, nqsets);
3086 }
3087}
3088
3089static int cxgb_enable_msix(struct adapter *adap)
3090{
3091 struct msix_entry entries[SGE_QSETS + 1];
3092 int vectors;
3093 int i;
3094
3095 vectors = ARRAY_SIZE(entries);
3096 for (i = 0; i < vectors; ++i)
3097 entries[i].entry = i;
3098
3099 vectors = pci_enable_msix_range(adap->pdev, entries,
3100 adap->params.nports + 1, vectors);
3101 if (vectors < 0)
3102 return vectors;
3103
3104 for (i = 0; i < vectors; ++i)
3105 adap->msix_info[i].vec = entries[i].vector;
3106 adap->msix_nvectors = vectors;
3107
3108 return 0;
3109}
3110
3111static void print_port_info(struct adapter *adap, const struct adapter_info *ai)
3112{
3113 static const char *pci_variant[] = {
3114 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3115 };
3116
3117 int i;
3118 char buf[80];
3119
3120 if (is_pcie(adap))
3121 snprintf(buf, sizeof(buf), "%s x%d",
3122 pci_variant[adap->params.pci.variant],
3123 adap->params.pci.width);
3124 else
3125 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3126 pci_variant[adap->params.pci.variant],
3127 adap->params.pci.speed, adap->params.pci.width);
3128
3129 for_each_port(adap, i) {
3130 struct net_device *dev = adap->port[i];
3131 const struct port_info *pi = netdev_priv(dev);
3132
3133 if (!test_bit(i, &adap->registered_device_map))
3134 continue;
3135 netdev_info(dev, "%s %s %sNIC (rev %d) %s%s\n",
3136 ai->desc, pi->phy.desc,
3137 is_offload(adap) ? "R" : "", adap->params.rev, buf,
3138 (adap->flags & USING_MSIX) ? " MSI-X" :
3139 (adap->flags & USING_MSI) ? " MSI" : "");
3140 if (adap->name == dev->name && adap->params.vpd.mclk)
3141 pr_info("%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
3142 adap->name, t3_mc7_size(&adap->cm) >> 20,
3143 t3_mc7_size(&adap->pmtx) >> 20,
3144 t3_mc7_size(&adap->pmrx) >> 20,
3145 adap->params.vpd.sn);
3146 }
3147}
3148
3149static const struct net_device_ops cxgb_netdev_ops = {
3150 .ndo_open = cxgb_open,
3151 .ndo_stop = cxgb_close,
3152 .ndo_start_xmit = t3_eth_xmit,
3153 .ndo_get_stats = cxgb_get_stats,
3154 .ndo_validate_addr = eth_validate_addr,
3155 .ndo_set_rx_mode = cxgb_set_rxmode,
3156 .ndo_do_ioctl = cxgb_ioctl,
3157 .ndo_change_mtu = cxgb_change_mtu,
3158 .ndo_set_mac_address = cxgb_set_mac_addr,
3159 .ndo_fix_features = cxgb_fix_features,
3160 .ndo_set_features = cxgb_set_features,
3161#ifdef CONFIG_NET_POLL_CONTROLLER
3162 .ndo_poll_controller = cxgb_netpoll,
3163#endif
3164};
3165
3166static void cxgb3_init_iscsi_mac(struct net_device *dev)
3167{
3168 struct port_info *pi = netdev_priv(dev);
3169
3170 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3171 pi->iscsic.mac_addr[3] |= 0x80;
3172}
3173
3174#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
3175#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
3176 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
3177static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3178{
3179 int i, err, pci_using_dac = 0;
3180 resource_size_t mmio_start, mmio_len;
3181 const struct adapter_info *ai;
3182 struct adapter *adapter = NULL;
3183 struct port_info *pi;
3184
3185 if (!cxgb3_wq) {
3186 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3187 if (!cxgb3_wq) {
3188 pr_err("cannot initialize work queue\n");
3189 return -ENOMEM;
3190 }
3191 }
3192
3193 err = pci_enable_device(pdev);
3194 if (err) {
3195 dev_err(&pdev->dev, "cannot enable PCI device\n");
3196 goto out;
3197 }
3198
3199 err = pci_request_regions(pdev, DRV_NAME);
3200 if (err) {
3201
3202 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3203 goto out_disable_device;
3204 }
3205
3206 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3207 pci_using_dac = 1;
3208 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3209 if (err) {
3210 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3211 "coherent allocations\n");
3212 goto out_release_regions;
3213 }
3214 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3215 dev_err(&pdev->dev, "no usable DMA configuration\n");
3216 goto out_release_regions;
3217 }
3218
3219 pci_set_master(pdev);
3220 pci_save_state(pdev);
3221
3222 mmio_start = pci_resource_start(pdev, 0);
3223 mmio_len = pci_resource_len(pdev, 0);
3224 ai = t3_get_adapter_info(ent->driver_data);
3225
3226 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3227 if (!adapter) {
3228 err = -ENOMEM;
3229 goto out_release_regions;
3230 }
3231
3232 adapter->nofail_skb =
3233 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3234 if (!adapter->nofail_skb) {
3235 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3236 err = -ENOMEM;
3237 goto out_free_adapter;
3238 }
3239
3240 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3241 if (!adapter->regs) {
3242 dev_err(&pdev->dev, "cannot map device registers\n");
3243 err = -ENOMEM;
3244 goto out_free_adapter;
3245 }
3246
3247 adapter->pdev = pdev;
3248 adapter->name = pci_name(pdev);
3249 adapter->msg_enable = dflt_msg_enable;
3250 adapter->mmio_len = mmio_len;
3251
3252 mutex_init(&adapter->mdio_lock);
3253 spin_lock_init(&adapter->work_lock);
3254 spin_lock_init(&adapter->stats_lock);
3255
3256 INIT_LIST_HEAD(&adapter->adapter_list);
3257 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
3258 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
3259
3260 INIT_WORK(&adapter->db_full_task, db_full_task);
3261 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3262 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3263
3264 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3265
3266 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
3267 struct net_device *netdev;
3268
3269 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
3270 if (!netdev) {
3271 err = -ENOMEM;
3272 goto out_free_dev;
3273 }
3274
3275 SET_NETDEV_DEV(netdev, &pdev->dev);
3276
3277 adapter->port[i] = netdev;
3278 pi = netdev_priv(netdev);
3279 pi->adapter = adapter;
3280 pi->port_id = i;
3281 netif_carrier_off(netdev);
3282 netdev->irq = pdev->irq;
3283 netdev->mem_start = mmio_start;
3284 netdev->mem_end = mmio_start + mmio_len - 1;
3285 netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
3286 NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
3287 netdev->features |= netdev->hw_features |
3288 NETIF_F_HW_VLAN_CTAG_TX;
3289 netdev->vlan_features |= netdev->features & VLAN_FEAT;
3290 if (pci_using_dac)
3291 netdev->features |= NETIF_F_HIGHDMA;
3292
3293 netdev->netdev_ops = &cxgb_netdev_ops;
3294 netdev->ethtool_ops = &cxgb_ethtool_ops;
3295 netdev->min_mtu = 81;
3296 netdev->max_mtu = ETH_MAX_MTU;
3297 netdev->dev_port = pi->port_id;
3298 }
3299
3300 pci_set_drvdata(pdev, adapter);
3301 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3302 err = -ENODEV;
3303 goto out_free_dev;
3304 }
3305
3306
3307
3308
3309
3310
3311
3312 for_each_port(adapter, i) {
3313 err = register_netdev(adapter->port[i]);
3314 if (err)
3315 dev_warn(&pdev->dev,
3316 "cannot register net device %s, skipping\n",
3317 adapter->port[i]->name);
3318 else {
3319
3320
3321
3322
3323 if (!adapter->registered_device_map)
3324 adapter->name = adapter->port[i]->name;
3325
3326 __set_bit(i, &adapter->registered_device_map);
3327 }
3328 }
3329 if (!adapter->registered_device_map) {
3330 dev_err(&pdev->dev, "could not register any net devices\n");
3331 goto out_free_dev;
3332 }
3333
3334 for_each_port(adapter, i)
3335 cxgb3_init_iscsi_mac(adapter->port[i]);
3336
3337
3338 t3_led_ready(adapter);
3339
3340 if (is_offload(adapter)) {
3341 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3342 cxgb3_adapter_ofld(adapter);
3343 }
3344
3345
3346 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3347 adapter->flags |= USING_MSIX;
3348 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3349 adapter->flags |= USING_MSI;
3350
3351 set_nqsets(adapter);
3352
3353 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
3354 &cxgb3_attr_group);
3355 if (err) {
3356 dev_err(&pdev->dev, "cannot create sysfs group\n");
3357 goto out_close_led;
3358 }
3359
3360 print_port_info(adapter, ai);
3361 return 0;
3362
3363out_close_led:
3364 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 0);
3365
3366out_free_dev:
3367 iounmap(adapter->regs);
3368 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
3369 if (adapter->port[i])
3370 free_netdev(adapter->port[i]);
3371
3372out_free_adapter:
3373 kfree(adapter);
3374
3375out_release_regions:
3376 pci_release_regions(pdev);
3377out_disable_device:
3378 pci_disable_device(pdev);
3379out:
3380 return err;
3381}
3382
3383static void remove_one(struct pci_dev *pdev)
3384{
3385 struct adapter *adapter = pci_get_drvdata(pdev);
3386
3387 if (adapter) {
3388 int i;
3389
3390 t3_sge_stop(adapter);
3391 sysfs_remove_group(&adapter->port[0]->dev.kobj,
3392 &cxgb3_attr_group);
3393
3394 if (is_offload(adapter)) {
3395 cxgb3_adapter_unofld(adapter);
3396 if (test_bit(OFFLOAD_DEVMAP_BIT,
3397 &adapter->open_device_map))
3398 offload_close(&adapter->tdev);
3399 }
3400
3401 for_each_port(adapter, i)
3402 if (test_bit(i, &adapter->registered_device_map))
3403 unregister_netdev(adapter->port[i]);
3404
3405 t3_stop_sge_timers(adapter);
3406 t3_free_sge_resources(adapter);
3407 cxgb_disable_msi(adapter);
3408
3409 for_each_port(adapter, i)
3410 if (adapter->port[i])
3411 free_netdev(adapter->port[i]);
3412
3413 iounmap(adapter->regs);
3414 if (adapter->nofail_skb)
3415 kfree_skb(adapter->nofail_skb);
3416 kfree(adapter);
3417 pci_release_regions(pdev);
3418 pci_disable_device(pdev);
3419 }
3420}
3421
3422static struct pci_driver driver = {
3423 .name = DRV_NAME,
3424 .id_table = cxgb3_pci_tbl,
3425 .probe = init_one,
3426 .remove = remove_one,
3427 .err_handler = &t3_err_handler,
3428};
3429
3430static int __init cxgb3_init_module(void)
3431{
3432 int ret;
3433
3434 cxgb3_offload_init();
3435
3436 ret = pci_register_driver(&driver);
3437 return ret;
3438}
3439
3440static void __exit cxgb3_cleanup_module(void)
3441{
3442 pci_unregister_driver(&driver);
3443 if (cxgb3_wq)
3444 destroy_workqueue(cxgb3_wq);
3445}
3446
3447module_init(cxgb3_init_module);
3448module_exit(cxgb3_cleanup_module);
3449