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16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/slab.h>
22#include <linux/stddef.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/dma-mapping.h>
31#include <linux/mii.h>
32#include <linux/phy.h>
33#include <linux/workqueue.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/of_mdio.h>
37#include <linux/of_net.h>
38#include <linux/of_platform.h>
39
40#include <linux/uaccess.h>
41#include <asm/irq.h>
42#include <asm/io.h>
43#include <soc/fsl/qe/immap_qe.h>
44#include <soc/fsl/qe/qe.h>
45#include <soc/fsl/qe/ucc.h>
46#include <soc/fsl/qe/ucc_fast.h>
47#include <asm/machdep.h>
48
49#include "ucc_geth.h"
50
51#undef DEBUG
52
53#define ugeth_printk(level, format, arg...) \
54 printk(level format "\n", ## arg)
55
56#define ugeth_dbg(format, arg...) \
57 ugeth_printk(KERN_DEBUG , format , ## arg)
58
59#ifdef UGETH_VERBOSE_DEBUG
60#define ugeth_vdbg ugeth_dbg
61#else
62#define ugeth_vdbg(fmt, args...) do { } while (0)
63#endif
64#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
65
66
67static DEFINE_SPINLOCK(ugeth_lock);
68
69static struct {
70 u32 msg_enable;
71} debug = { -1 };
72
73module_param_named(debug, debug.msg_enable, int, 0);
74MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
75
76static struct ucc_geth_info ugeth_primary_info = {
77 .uf_info = {
78 .bd_mem_part = MEM_PART_SYSTEM,
79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
80 .max_rx_buf_length = 1536,
81
82 .urfs = UCC_GETH_URFS_INIT,
83 .urfet = UCC_GETH_URFET_INIT,
84 .urfset = UCC_GETH_URFSET_INIT,
85 .utfs = UCC_GETH_UTFS_INIT,
86 .utfet = UCC_GETH_UTFET_INIT,
87 .utftt = UCC_GETH_UTFTT_INIT,
88 .ufpt = 256,
89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
91 .tenc = UCC_FAST_TX_ENCODING_NRZ,
92 .renc = UCC_FAST_RX_ENCODING_NRZ,
93 .tcrc = UCC_FAST_16_BIT_CRC,
94 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
95 },
96 .numQueuesTx = 1,
97 .numQueuesRx = 1,
98 .extendedFilteringChainPointer = ((uint32_t) NULL),
99 .typeorlen = 3072 ,
100 .nonBackToBackIfgPart1 = 0x40,
101 .nonBackToBackIfgPart2 = 0x60,
102 .miminumInterFrameGapEnforcement = 0x50,
103 .backToBackInterFrameGap = 0x60,
104 .mblinterval = 128,
105 .nortsrbytetime = 5,
106 .fracsiz = 1,
107 .strictpriorityq = 0xff,
108 .altBebTruncation = 0xa,
109 .excessDefer = 1,
110 .maxRetransmission = 0xf,
111 .collisionWindow = 0x37,
112 .receiveFlowControl = 1,
113 .transmitFlowControl = 1,
114 .maxGroupAddrInHash = 4,
115 .maxIndAddrInHash = 4,
116 .prel = 7,
117 .maxFrameLength = 1518+16,
118 .minFrameLength = 64,
119 .maxD1Length = 1520+16,
120 .maxD2Length = 1520+16,
121 .vlantype = 0x8100,
122 .ecamptr = ((uint32_t) NULL),
123 .eventRegMask = UCCE_OTHER,
124 .pausePeriod = 0xf000,
125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
126 .bdRingLenTx = {
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN},
135
136 .bdRingLenRx = {
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN},
145
146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
147 .largestexternallookupkeysize =
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161};
162
163static struct ucc_geth_info ugeth_info[8];
164
165#ifdef DEBUG
166static void mem_disp(u8 *addr, int size)
167{
168 u8 *i;
169 int size16Aling = (size >> 4) << 4;
170 int size4Aling = (size >> 2) << 2;
171 int notAlign = 0;
172 if (size % 16)
173 notAlign = 1;
174
175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
177 (u32) i,
178 *((u32 *) (i)),
179 *((u32 *) (i + 4)),
180 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
181 if (notAlign == 1)
182 printk("0x%08x: ", (u32) i);
183 for (; (u32) i < (u32) addr + size4Aling; i += 4)
184 printk("%08x ", *((u32 *) (i)));
185 for (; (u32) i < (u32) addr + size; i++)
186 printk("%02x", *((i)));
187 if (notAlign == 1)
188 printk("\r\n");
189}
190#endif
191
192static struct list_head *dequeue(struct list_head *lh)
193{
194 unsigned long flags;
195
196 spin_lock_irqsave(&ugeth_lock, flags);
197 if (!list_empty(lh)) {
198 struct list_head *node = lh->next;
199 list_del(node);
200 spin_unlock_irqrestore(&ugeth_lock, flags);
201 return node;
202 } else {
203 spin_unlock_irqrestore(&ugeth_lock, flags);
204 return NULL;
205 }
206}
207
208static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
209 u8 __iomem *bd)
210{
211 struct sk_buff *skb;
212
213 skb = netdev_alloc_skb(ugeth->ndev,
214 ugeth->ug_info->uf_info.max_rx_buf_length +
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
216 if (!skb)
217 return NULL;
218
219
220
221
222 skb_reserve(skb,
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225 1)));
226
227 out_be32(&((struct qe_bd __iomem *)bd)->buf,
228 dma_map_single(ugeth->dev,
229 skb->data,
230 ugeth->ug_info->uf_info.max_rx_buf_length +
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
232 DMA_FROM_DEVICE));
233
234 out_be32((u32 __iomem *)bd,
235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
236
237 return skb;
238}
239
240static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
241{
242 u8 __iomem *bd;
243 u32 bd_status;
244 struct sk_buff *skb;
245 int i;
246
247 bd = ugeth->p_rx_bd_ring[rxQ];
248 i = 0;
249
250 do {
251 bd_status = in_be32((u32 __iomem *)bd);
252 skb = get_new_skb(ugeth, bd);
253
254 if (!skb)
255
256 return -ENOMEM;
257
258 ugeth->rx_skbuff[rxQ][i] = skb;
259
260
261 bd += sizeof(struct qe_bd);
262 i++;
263 } while (!(bd_status & R_W));
264
265 return 0;
266}
267
268static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
269 u32 *p_start,
270 u8 num_entries,
271 u32 thread_size,
272 u32 thread_alignment,
273 unsigned int risc,
274 int skip_page_for_first_entry)
275{
276 u32 init_enet_offset;
277 u8 i;
278 int snum;
279
280 for (i = 0; i < num_entries; i++) {
281 if ((snum = qe_get_snum()) < 0) {
282 if (netif_msg_ifup(ugeth))
283 pr_err("Can not get SNUM\n");
284 return snum;
285 }
286 if ((i == 0) && skip_page_for_first_entry)
287
288 init_enet_offset = 0;
289 else {
290 init_enet_offset =
291 qe_muram_alloc(thread_size, thread_alignment);
292 if (IS_ERR_VALUE(init_enet_offset)) {
293 if (netif_msg_ifup(ugeth))
294 pr_err("Can not allocate DPRAM memory\n");
295 qe_put_snum((u8) snum);
296 return -ENOMEM;
297 }
298 }
299 *(p_start++) =
300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
301 | risc;
302 }
303
304 return 0;
305}
306
307static int return_init_enet_entries(struct ucc_geth_private *ugeth,
308 u32 *p_start,
309 u8 num_entries,
310 unsigned int risc,
311 int skip_page_for_first_entry)
312{
313 u32 init_enet_offset;
314 u8 i;
315 int snum;
316
317 for (i = 0; i < num_entries; i++) {
318 u32 val = *p_start;
319
320
321
322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
323 snum =
324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
325 ENET_INIT_PARAM_SNUM_SHIFT;
326 qe_put_snum((u8) snum);
327 if (!((i == 0) && skip_page_for_first_entry)) {
328
329 init_enet_offset =
330 (val & ENET_INIT_PARAM_PTR_MASK);
331 qe_muram_free(init_enet_offset);
332 }
333 *p_start++ = 0;
334 }
335 }
336
337 return 0;
338}
339
340#ifdef DEBUG
341static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
342 u32 __iomem *p_start,
343 u8 num_entries,
344 u32 thread_size,
345 unsigned int risc,
346 int skip_page_for_first_entry)
347{
348 u32 init_enet_offset;
349 u8 i;
350 int snum;
351
352 for (i = 0; i < num_entries; i++) {
353 u32 val = in_be32(p_start);
354
355
356
357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
358 snum =
359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
367 pr_info("Init enet entry %d:\n", i);
368 pr_info("Base address: 0x%08x\n",
369 (u32)qe_muram_addr(init_enet_offset));
370 mem_disp(qe_muram_addr(init_enet_offset),
371 thread_size);
372 }
373 p_start++;
374 }
375 }
376
377 return 0;
378}
379#endif
380
381static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
382{
383 kfree(enet_addr_cont);
384}
385
386static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
387{
388 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]);
389 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]);
390 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]);
391}
392
393static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
394{
395 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
396
397 if (paddr_num >= NUM_OF_PADDRS) {
398 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
399 return -EINVAL;
400 }
401
402 p_82xx_addr_filt =
403 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
404 addressfiltering;
405
406
407
408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
411
412 return 0;
413}
414
415static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
416 u8 *p_enet_addr)
417{
418 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
419 u32 cecr_subblock;
420
421 p_82xx_addr_filt =
422 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
423 addressfiltering;
424
425 cecr_subblock =
426 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
427
428
429
430
431
432 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
433
434 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
435 QE_CR_PROTOCOL_ETHERNET, 0);
436}
437
438#ifdef DEBUG
439static void get_statistics(struct ucc_geth_private *ugeth,
440 struct ucc_geth_tx_firmware_statistics *
441 tx_firmware_statistics,
442 struct ucc_geth_rx_firmware_statistics *
443 rx_firmware_statistics,
444 struct ucc_geth_hardware_statistics *hardware_statistics)
445{
446 struct ucc_fast __iomem *uf_regs;
447 struct ucc_geth __iomem *ug_regs;
448 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
449 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
450
451 ug_regs = ugeth->ug_regs;
452 uf_regs = (struct ucc_fast __iomem *) ug_regs;
453 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
454 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
455
456
457
458 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
459 tx_firmware_statistics->sicoltx =
460 in_be32(&p_tx_fw_statistics_pram->sicoltx);
461 tx_firmware_statistics->mulcoltx =
462 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
463 tx_firmware_statistics->latecoltxfr =
464 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
465 tx_firmware_statistics->frabortduecol =
466 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
467 tx_firmware_statistics->frlostinmactxer =
468 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
469 tx_firmware_statistics->carriersenseertx =
470 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
471 tx_firmware_statistics->frtxok =
472 in_be32(&p_tx_fw_statistics_pram->frtxok);
473 tx_firmware_statistics->txfrexcessivedefer =
474 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
475 tx_firmware_statistics->txpkts256 =
476 in_be32(&p_tx_fw_statistics_pram->txpkts256);
477 tx_firmware_statistics->txpkts512 =
478 in_be32(&p_tx_fw_statistics_pram->txpkts512);
479 tx_firmware_statistics->txpkts1024 =
480 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
481 tx_firmware_statistics->txpktsjumbo =
482 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
483 }
484
485
486
487 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
488 int i;
489 rx_firmware_statistics->frrxfcser =
490 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
491 rx_firmware_statistics->fraligner =
492 in_be32(&p_rx_fw_statistics_pram->fraligner);
493 rx_firmware_statistics->inrangelenrxer =
494 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
495 rx_firmware_statistics->outrangelenrxer =
496 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
497 rx_firmware_statistics->frtoolong =
498 in_be32(&p_rx_fw_statistics_pram->frtoolong);
499 rx_firmware_statistics->runt =
500 in_be32(&p_rx_fw_statistics_pram->runt);
501 rx_firmware_statistics->verylongevent =
502 in_be32(&p_rx_fw_statistics_pram->verylongevent);
503 rx_firmware_statistics->symbolerror =
504 in_be32(&p_rx_fw_statistics_pram->symbolerror);
505 rx_firmware_statistics->dropbsy =
506 in_be32(&p_rx_fw_statistics_pram->dropbsy);
507 for (i = 0; i < 0x8; i++)
508 rx_firmware_statistics->res0[i] =
509 p_rx_fw_statistics_pram->res0[i];
510 rx_firmware_statistics->mismatchdrop =
511 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
512 rx_firmware_statistics->underpkts =
513 in_be32(&p_rx_fw_statistics_pram->underpkts);
514 rx_firmware_statistics->pkts256 =
515 in_be32(&p_rx_fw_statistics_pram->pkts256);
516 rx_firmware_statistics->pkts512 =
517 in_be32(&p_rx_fw_statistics_pram->pkts512);
518 rx_firmware_statistics->pkts1024 =
519 in_be32(&p_rx_fw_statistics_pram->pkts1024);
520 rx_firmware_statistics->pktsjumbo =
521 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
522 rx_firmware_statistics->frlossinmacer =
523 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
524 rx_firmware_statistics->pausefr =
525 in_be32(&p_rx_fw_statistics_pram->pausefr);
526 for (i = 0; i < 0x4; i++)
527 rx_firmware_statistics->res1[i] =
528 p_rx_fw_statistics_pram->res1[i];
529 rx_firmware_statistics->removevlan =
530 in_be32(&p_rx_fw_statistics_pram->removevlan);
531 rx_firmware_statistics->replacevlan =
532 in_be32(&p_rx_fw_statistics_pram->replacevlan);
533 rx_firmware_statistics->insertvlan =
534 in_be32(&p_rx_fw_statistics_pram->insertvlan);
535 }
536
537
538
539 if (hardware_statistics &&
540 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
541 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
542 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
543 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
544 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
545 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
546 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
547 hardware_statistics->txok = in_be32(&ug_regs->txok);
548 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
549 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
550 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
551 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
552 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
553 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
554 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
555 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
556 }
557}
558
559static void dump_bds(struct ucc_geth_private *ugeth)
560{
561 int i;
562 int length;
563
564 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
565 if (ugeth->p_tx_bd_ring[i]) {
566 length =
567 (ugeth->ug_info->bdRingLenTx[i] *
568 sizeof(struct qe_bd));
569 pr_info("TX BDs[%d]\n", i);
570 mem_disp(ugeth->p_tx_bd_ring[i], length);
571 }
572 }
573 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
574 if (ugeth->p_rx_bd_ring[i]) {
575 length =
576 (ugeth->ug_info->bdRingLenRx[i] *
577 sizeof(struct qe_bd));
578 pr_info("RX BDs[%d]\n", i);
579 mem_disp(ugeth->p_rx_bd_ring[i], length);
580 }
581 }
582}
583
584static void dump_regs(struct ucc_geth_private *ugeth)
585{
586 int i;
587
588 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
589 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
590
591 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n",
592 (u32)&ugeth->ug_regs->maccfg1,
593 in_be32(&ugeth->ug_regs->maccfg1));
594 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n",
595 (u32)&ugeth->ug_regs->maccfg2,
596 in_be32(&ugeth->ug_regs->maccfg2));
597 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n",
598 (u32)&ugeth->ug_regs->ipgifg,
599 in_be32(&ugeth->ug_regs->ipgifg));
600 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n",
601 (u32)&ugeth->ug_regs->hafdup,
602 in_be32(&ugeth->ug_regs->hafdup));
603 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n",
604 (u32)&ugeth->ug_regs->ifctl,
605 in_be32(&ugeth->ug_regs->ifctl));
606 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n",
607 (u32)&ugeth->ug_regs->ifstat,
608 in_be32(&ugeth->ug_regs->ifstat));
609 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
610 (u32)&ugeth->ug_regs->macstnaddr1,
611 in_be32(&ugeth->ug_regs->macstnaddr1));
612 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
613 (u32)&ugeth->ug_regs->macstnaddr2,
614 in_be32(&ugeth->ug_regs->macstnaddr2));
615 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n",
616 (u32)&ugeth->ug_regs->uempr,
617 in_be32(&ugeth->ug_regs->uempr));
618 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n",
619 (u32)&ugeth->ug_regs->utbipar,
620 in_be32(&ugeth->ug_regs->utbipar));
621 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n",
622 (u32)&ugeth->ug_regs->uescr,
623 in_be16(&ugeth->ug_regs->uescr));
624 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n",
625 (u32)&ugeth->ug_regs->tx64,
626 in_be32(&ugeth->ug_regs->tx64));
627 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n",
628 (u32)&ugeth->ug_regs->tx127,
629 in_be32(&ugeth->ug_regs->tx127));
630 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n",
631 (u32)&ugeth->ug_regs->tx255,
632 in_be32(&ugeth->ug_regs->tx255));
633 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n",
634 (u32)&ugeth->ug_regs->rx64,
635 in_be32(&ugeth->ug_regs->rx64));
636 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n",
637 (u32)&ugeth->ug_regs->rx127,
638 in_be32(&ugeth->ug_regs->rx127));
639 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n",
640 (u32)&ugeth->ug_regs->rx255,
641 in_be32(&ugeth->ug_regs->rx255));
642 pr_info("txok : addr - 0x%08x, val - 0x%08x\n",
643 (u32)&ugeth->ug_regs->txok,
644 in_be32(&ugeth->ug_regs->txok));
645 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n",
646 (u32)&ugeth->ug_regs->txcf,
647 in_be16(&ugeth->ug_regs->txcf));
648 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n",
649 (u32)&ugeth->ug_regs->tmca,
650 in_be32(&ugeth->ug_regs->tmca));
651 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n",
652 (u32)&ugeth->ug_regs->tbca,
653 in_be32(&ugeth->ug_regs->tbca));
654 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n",
655 (u32)&ugeth->ug_regs->rxfok,
656 in_be32(&ugeth->ug_regs->rxfok));
657 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n",
658 (u32)&ugeth->ug_regs->rxbok,
659 in_be32(&ugeth->ug_regs->rxbok));
660 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n",
661 (u32)&ugeth->ug_regs->rbyt,
662 in_be32(&ugeth->ug_regs->rbyt));
663 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n",
664 (u32)&ugeth->ug_regs->rmca,
665 in_be32(&ugeth->ug_regs->rmca));
666 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n",
667 (u32)&ugeth->ug_regs->rbca,
668 in_be32(&ugeth->ug_regs->rbca));
669 pr_info("scar : addr - 0x%08x, val - 0x%08x\n",
670 (u32)&ugeth->ug_regs->scar,
671 in_be32(&ugeth->ug_regs->scar));
672 pr_info("scam : addr - 0x%08x, val - 0x%08x\n",
673 (u32)&ugeth->ug_regs->scam,
674 in_be32(&ugeth->ug_regs->scam));
675
676 if (ugeth->p_thread_data_tx) {
677 int numThreadsTxNumerical;
678 switch (ugeth->ug_info->numThreadsTx) {
679 case UCC_GETH_NUM_OF_THREADS_1:
680 numThreadsTxNumerical = 1;
681 break;
682 case UCC_GETH_NUM_OF_THREADS_2:
683 numThreadsTxNumerical = 2;
684 break;
685 case UCC_GETH_NUM_OF_THREADS_4:
686 numThreadsTxNumerical = 4;
687 break;
688 case UCC_GETH_NUM_OF_THREADS_6:
689 numThreadsTxNumerical = 6;
690 break;
691 case UCC_GETH_NUM_OF_THREADS_8:
692 numThreadsTxNumerical = 8;
693 break;
694 default:
695 numThreadsTxNumerical = 0;
696 break;
697 }
698
699 pr_info("Thread data TXs:\n");
700 pr_info("Base address: 0x%08x\n",
701 (u32)ugeth->p_thread_data_tx);
702 for (i = 0; i < numThreadsTxNumerical; i++) {
703 pr_info("Thread data TX[%d]:\n", i);
704 pr_info("Base address: 0x%08x\n",
705 (u32)&ugeth->p_thread_data_tx[i]);
706 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
707 sizeof(struct ucc_geth_thread_data_tx));
708 }
709 }
710 if (ugeth->p_thread_data_rx) {
711 int numThreadsRxNumerical;
712 switch (ugeth->ug_info->numThreadsRx) {
713 case UCC_GETH_NUM_OF_THREADS_1:
714 numThreadsRxNumerical = 1;
715 break;
716 case UCC_GETH_NUM_OF_THREADS_2:
717 numThreadsRxNumerical = 2;
718 break;
719 case UCC_GETH_NUM_OF_THREADS_4:
720 numThreadsRxNumerical = 4;
721 break;
722 case UCC_GETH_NUM_OF_THREADS_6:
723 numThreadsRxNumerical = 6;
724 break;
725 case UCC_GETH_NUM_OF_THREADS_8:
726 numThreadsRxNumerical = 8;
727 break;
728 default:
729 numThreadsRxNumerical = 0;
730 break;
731 }
732
733 pr_info("Thread data RX:\n");
734 pr_info("Base address: 0x%08x\n",
735 (u32)ugeth->p_thread_data_rx);
736 for (i = 0; i < numThreadsRxNumerical; i++) {
737 pr_info("Thread data RX[%d]:\n", i);
738 pr_info("Base address: 0x%08x\n",
739 (u32)&ugeth->p_thread_data_rx[i]);
740 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
741 sizeof(struct ucc_geth_thread_data_rx));
742 }
743 }
744 if (ugeth->p_exf_glbl_param) {
745 pr_info("EXF global param:\n");
746 pr_info("Base address: 0x%08x\n",
747 (u32)ugeth->p_exf_glbl_param);
748 mem_disp((u8 *) ugeth->p_exf_glbl_param,
749 sizeof(*ugeth->p_exf_glbl_param));
750 }
751 if (ugeth->p_tx_glbl_pram) {
752 pr_info("TX global param:\n");
753 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
754 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n",
755 (u32)&ugeth->p_tx_glbl_pram->temoder,
756 in_be16(&ugeth->p_tx_glbl_pram->temoder));
757 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n",
758 (u32)&ugeth->p_tx_glbl_pram->sqptr,
759 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
760 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
761 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
762 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
763 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
764 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
765 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
766 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n",
767 (u32)&ugeth->p_tx_glbl_pram->tstate,
768 in_be32(&ugeth->p_tx_glbl_pram->tstate));
769 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
770 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
771 ugeth->p_tx_glbl_pram->iphoffset[0]);
772 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
773 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
774 ugeth->p_tx_glbl_pram->iphoffset[1]);
775 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
776 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
777 ugeth->p_tx_glbl_pram->iphoffset[2]);
778 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
779 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
780 ugeth->p_tx_glbl_pram->iphoffset[3]);
781 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
782 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
783 ugeth->p_tx_glbl_pram->iphoffset[4]);
784 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
785 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
786 ugeth->p_tx_glbl_pram->iphoffset[5]);
787 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
788 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
789 ugeth->p_tx_glbl_pram->iphoffset[6]);
790 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
791 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
792 ugeth->p_tx_glbl_pram->iphoffset[7]);
793 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
794 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
795 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
796 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
797 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
798 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
799 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
800 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
801 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
802 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
803 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
805 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
806 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
808 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
809 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
811 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
812 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
814 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
815 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
817 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n",
818 (u32)&ugeth->p_tx_glbl_pram->tqptr,
819 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
820 }
821 if (ugeth->p_rx_glbl_pram) {
822 pr_info("RX global param:\n");
823 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
824 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n",
825 (u32)&ugeth->p_rx_glbl_pram->remoder,
826 in_be32(&ugeth->p_rx_glbl_pram->remoder));
827 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n",
828 (u32)&ugeth->p_rx_glbl_pram->rqptr,
829 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
830 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n",
831 (u32)&ugeth->p_rx_glbl_pram->typeorlen,
832 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
833 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n",
834 (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
835 ugeth->p_rx_glbl_pram->rxgstpack);
836 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n",
837 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
838 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
839 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
840 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
841 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
842 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n",
843 (u32)&ugeth->p_rx_glbl_pram->rstate,
844 ugeth->p_rx_glbl_pram->rstate);
845 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n",
846 (u32)&ugeth->p_rx_glbl_pram->mrblr,
847 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
848 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n",
849 (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
850 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
851 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n",
852 (u32)&ugeth->p_rx_glbl_pram->mflr,
853 in_be16(&ugeth->p_rx_glbl_pram->mflr));
854 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n",
855 (u32)&ugeth->p_rx_glbl_pram->minflr,
856 in_be16(&ugeth->p_rx_glbl_pram->minflr));
857 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n",
858 (u32)&ugeth->p_rx_glbl_pram->maxd1,
859 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
860 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n",
861 (u32)&ugeth->p_rx_glbl_pram->maxd2,
862 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
863 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n",
864 (u32)&ugeth->p_rx_glbl_pram->ecamptr,
865 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
866 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n",
867 (u32)&ugeth->p_rx_glbl_pram->l2qt,
868 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
869 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n",
870 (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
871 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
872 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n",
873 (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
874 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
875 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n",
876 (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
877 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
878 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n",
879 (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
881 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n",
882 (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
884 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n",
885 (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
887 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n",
888 (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
890 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n",
891 (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
893 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n",
894 (u32)&ugeth->p_rx_glbl_pram->vlantype,
895 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
896 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n",
897 (u32)&ugeth->p_rx_glbl_pram->vlantci,
898 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
899 for (i = 0; i < 64; i++)
900 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
901 i,
902 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
903 ugeth->p_rx_glbl_pram->addressfiltering[i]);
904 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n",
905 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
906 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
907 }
908 if (ugeth->p_send_q_mem_reg) {
909 pr_info("Send Q memory registers:\n");
910 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
911 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
912 pr_info("SQQD[%d]:\n", i);
913 pr_info("Base address: 0x%08x\n",
914 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
915 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
916 sizeof(struct ucc_geth_send_queue_qd));
917 }
918 }
919 if (ugeth->p_scheduler) {
920 pr_info("Scheduler:\n");
921 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
922 mem_disp((u8 *) ugeth->p_scheduler,
923 sizeof(*ugeth->p_scheduler));
924 }
925 if (ugeth->p_tx_fw_statistics_pram) {
926 pr_info("TX FW statistics pram:\n");
927 pr_info("Base address: 0x%08x\n",
928 (u32)ugeth->p_tx_fw_statistics_pram);
929 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
930 sizeof(*ugeth->p_tx_fw_statistics_pram));
931 }
932 if (ugeth->p_rx_fw_statistics_pram) {
933 pr_info("RX FW statistics pram:\n");
934 pr_info("Base address: 0x%08x\n",
935 (u32)ugeth->p_rx_fw_statistics_pram);
936 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
937 sizeof(*ugeth->p_rx_fw_statistics_pram));
938 }
939 if (ugeth->p_rx_irq_coalescing_tbl) {
940 pr_info("RX IRQ coalescing tables:\n");
941 pr_info("Base address: 0x%08x\n",
942 (u32)ugeth->p_rx_irq_coalescing_tbl);
943 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
944 pr_info("RX IRQ coalescing table entry[%d]:\n", i);
945 pr_info("Base address: 0x%08x\n",
946 (u32)&ugeth->p_rx_irq_coalescing_tbl->
947 coalescingentry[i]);
948 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
949 (u32)&ugeth->p_rx_irq_coalescing_tbl->
950 coalescingentry[i].interruptcoalescingmaxvalue,
951 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
952 coalescingentry[i].
953 interruptcoalescingmaxvalue));
954 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
955 (u32)&ugeth->p_rx_irq_coalescing_tbl->
956 coalescingentry[i].interruptcoalescingcounter,
957 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
958 coalescingentry[i].
959 interruptcoalescingcounter));
960 }
961 }
962 if (ugeth->p_rx_bd_qs_tbl) {
963 pr_info("RX BD QS tables:\n");
964 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
965 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
966 pr_info("RX BD QS table[%d]:\n", i);
967 pr_info("Base address: 0x%08x\n",
968 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
969 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n",
970 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
971 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
972 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n",
973 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
974 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
975 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
976 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
977 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
978 externalbdbaseptr));
979 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n",
980 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
981 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
982 pr_info("ucode RX Prefetched BDs:\n");
983 pr_info("Base address: 0x%08x\n",
984 (u32)qe_muram_addr(in_be32
985 (&ugeth->p_rx_bd_qs_tbl[i].
986 bdbaseptr)));
987 mem_disp((u8 *)
988 qe_muram_addr(in_be32
989 (&ugeth->p_rx_bd_qs_tbl[i].
990 bdbaseptr)),
991 sizeof(struct ucc_geth_rx_prefetched_bds));
992 }
993 }
994 if (ugeth->p_init_enet_param_shadow) {
995 int size;
996 pr_info("Init enet param shadow:\n");
997 pr_info("Base address: 0x%08x\n",
998 (u32) ugeth->p_init_enet_param_shadow);
999 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1000 sizeof(*ugeth->p_init_enet_param_shadow));
1001
1002 size = sizeof(struct ucc_geth_thread_rx_pram);
1003 if (ugeth->ug_info->rxExtendedFiltering) {
1004 size +=
1005 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1006 if (ugeth->ug_info->largestexternallookupkeysize ==
1007 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1008 size +=
1009 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1010 if (ugeth->ug_info->largestexternallookupkeysize ==
1011 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1012 size +=
1013 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1014 }
1015
1016 dump_init_enet_entries(ugeth,
1017 &(ugeth->p_init_enet_param_shadow->
1018 txthread[0]),
1019 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1020 sizeof(struct ucc_geth_thread_tx_pram),
1021 ugeth->ug_info->riscTx, 0);
1022 dump_init_enet_entries(ugeth,
1023 &(ugeth->p_init_enet_param_shadow->
1024 rxthread[0]),
1025 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1026 ugeth->ug_info->riscRx, 1);
1027 }
1028}
1029#endif
1030
1031static void init_default_reg_vals(u32 __iomem *upsmr_register,
1032 u32 __iomem *maccfg1_register,
1033 u32 __iomem *maccfg2_register)
1034{
1035 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1036 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1037 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1038}
1039
1040static int init_half_duplex_params(int alt_beb,
1041 int back_pressure_no_backoff,
1042 int no_backoff,
1043 int excess_defer,
1044 u8 alt_beb_truncation,
1045 u8 max_retransmissions,
1046 u8 collision_window,
1047 u32 __iomem *hafdup_register)
1048{
1049 u32 value = 0;
1050
1051 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1052 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1053 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1054 return -EINVAL;
1055
1056 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1057
1058 if (alt_beb)
1059 value |= HALFDUP_ALT_BEB;
1060 if (back_pressure_no_backoff)
1061 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1062 if (no_backoff)
1063 value |= HALFDUP_NO_BACKOFF;
1064 if (excess_defer)
1065 value |= HALFDUP_EXCESSIVE_DEFER;
1066
1067 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1068
1069 value |= collision_window;
1070
1071 out_be32(hafdup_register, value);
1072 return 0;
1073}
1074
1075static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1076 u8 non_btb_ipg,
1077 u8 min_ifg,
1078 u8 btb_ipg,
1079 u32 __iomem *ipgifg_register)
1080{
1081 u32 value = 0;
1082
1083
1084
1085 if (non_btb_cs_ipg > non_btb_ipg)
1086 return -EINVAL;
1087
1088 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1089 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1090
1091 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1092 return -EINVAL;
1093
1094 value |=
1095 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1096 IPGIFG_NBTB_CS_IPG_MASK);
1097 value |=
1098 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1099 IPGIFG_NBTB_IPG_MASK);
1100 value |=
1101 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1102 IPGIFG_MIN_IFG_MASK);
1103 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1104
1105 out_be32(ipgifg_register, value);
1106 return 0;
1107}
1108
1109int init_flow_control_params(u32 automatic_flow_control_mode,
1110 int rx_flow_control_enable,
1111 int tx_flow_control_enable,
1112 u16 pause_period,
1113 u16 extension_field,
1114 u32 __iomem *upsmr_register,
1115 u32 __iomem *uempr_register,
1116 u32 __iomem *maccfg1_register)
1117{
1118 u32 value = 0;
1119
1120
1121 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1122 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1123 out_be32(uempr_register, value);
1124
1125
1126 setbits32(upsmr_register, automatic_flow_control_mode);
1127
1128 value = in_be32(maccfg1_register);
1129 if (rx_flow_control_enable)
1130 value |= MACCFG1_FLOW_RX;
1131 if (tx_flow_control_enable)
1132 value |= MACCFG1_FLOW_TX;
1133 out_be32(maccfg1_register, value);
1134
1135 return 0;
1136}
1137
1138static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1139 int auto_zero_hardware_statistics,
1140 u32 __iomem *upsmr_register,
1141 u16 __iomem *uescr_register)
1142{
1143 u16 uescr_value = 0;
1144
1145
1146 if (enable_hardware_statistics)
1147 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1148
1149
1150 uescr_value = in_be16(uescr_register);
1151 uescr_value |= UESCR_CLRCNT;
1152
1153
1154 if (auto_zero_hardware_statistics)
1155 uescr_value |= UESCR_AUTOZ;
1156 out_be16(uescr_register, uescr_value);
1157
1158 return 0;
1159}
1160
1161static int init_firmware_statistics_gathering_mode(int
1162 enable_tx_firmware_statistics,
1163 int enable_rx_firmware_statistics,
1164 u32 __iomem *tx_rmon_base_ptr,
1165 u32 tx_firmware_statistics_structure_address,
1166 u32 __iomem *rx_rmon_base_ptr,
1167 u32 rx_firmware_statistics_structure_address,
1168 u16 __iomem *temoder_register,
1169 u32 __iomem *remoder_register)
1170{
1171
1172
1173
1174 if (enable_tx_firmware_statistics) {
1175 out_be32(tx_rmon_base_ptr,
1176 tx_firmware_statistics_structure_address);
1177 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1178 }
1179
1180 if (enable_rx_firmware_statistics) {
1181 out_be32(rx_rmon_base_ptr,
1182 rx_firmware_statistics_structure_address);
1183 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1184 }
1185
1186 return 0;
1187}
1188
1189static int init_mac_station_addr_regs(u8 address_byte_0,
1190 u8 address_byte_1,
1191 u8 address_byte_2,
1192 u8 address_byte_3,
1193 u8 address_byte_4,
1194 u8 address_byte_5,
1195 u32 __iomem *macstnaddr1_register,
1196 u32 __iomem *macstnaddr2_register)
1197{
1198 u32 value = 0;
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1210 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1211 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1212 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1213
1214 out_be32(macstnaddr1_register, value);
1215
1216
1217
1218
1219
1220
1221
1222 value = 0;
1223 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1224 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1225
1226 out_be32(macstnaddr2_register, value);
1227
1228 return 0;
1229}
1230
1231static int init_check_frame_length_mode(int length_check,
1232 u32 __iomem *maccfg2_register)
1233{
1234 u32 value = 0;
1235
1236 value = in_be32(maccfg2_register);
1237
1238 if (length_check)
1239 value |= MACCFG2_LC;
1240 else
1241 value &= ~MACCFG2_LC;
1242
1243 out_be32(maccfg2_register, value);
1244 return 0;
1245}
1246
1247static int init_preamble_length(u8 preamble_length,
1248 u32 __iomem *maccfg2_register)
1249{
1250 if ((preamble_length < 3) || (preamble_length > 7))
1251 return -EINVAL;
1252
1253 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1254 preamble_length << MACCFG2_PREL_SHIFT);
1255
1256 return 0;
1257}
1258
1259static int init_rx_parameters(int reject_broadcast,
1260 int receive_short_frames,
1261 int promiscuous, u32 __iomem *upsmr_register)
1262{
1263 u32 value = 0;
1264
1265 value = in_be32(upsmr_register);
1266
1267 if (reject_broadcast)
1268 value |= UCC_GETH_UPSMR_BRO;
1269 else
1270 value &= ~UCC_GETH_UPSMR_BRO;
1271
1272 if (receive_short_frames)
1273 value |= UCC_GETH_UPSMR_RSH;
1274 else
1275 value &= ~UCC_GETH_UPSMR_RSH;
1276
1277 if (promiscuous)
1278 value |= UCC_GETH_UPSMR_PRO;
1279 else
1280 value &= ~UCC_GETH_UPSMR_PRO;
1281
1282 out_be32(upsmr_register, value);
1283
1284 return 0;
1285}
1286
1287static int init_max_rx_buff_len(u16 max_rx_buf_len,
1288 u16 __iomem *mrblr_register)
1289{
1290
1291 if ((max_rx_buf_len == 0) ||
1292 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1293 return -EINVAL;
1294
1295 out_be16(mrblr_register, max_rx_buf_len);
1296 return 0;
1297}
1298
1299static int init_min_frame_len(u16 min_frame_length,
1300 u16 __iomem *minflr_register,
1301 u16 __iomem *mrblr_register)
1302{
1303 u16 mrblr_value = 0;
1304
1305 mrblr_value = in_be16(mrblr_register);
1306 if (min_frame_length >= (mrblr_value - 4))
1307 return -EINVAL;
1308
1309 out_be16(minflr_register, min_frame_length);
1310 return 0;
1311}
1312
1313static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1314{
1315 struct ucc_geth_info *ug_info;
1316 struct ucc_geth __iomem *ug_regs;
1317 struct ucc_fast __iomem *uf_regs;
1318 int ret_val;
1319 u32 upsmr, maccfg2;
1320 u16 value;
1321
1322 ugeth_vdbg("%s: IN", __func__);
1323
1324 ug_info = ugeth->ug_info;
1325 ug_regs = ugeth->ug_regs;
1326 uf_regs = ugeth->uccf->uf_regs;
1327
1328
1329 maccfg2 = in_be32(&ug_regs->maccfg2);
1330 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1331 if ((ugeth->max_speed == SPEED_10) ||
1332 (ugeth->max_speed == SPEED_100))
1333 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1334 else if (ugeth->max_speed == SPEED_1000)
1335 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1336 maccfg2 |= ug_info->padAndCrc;
1337 out_be32(&ug_regs->maccfg2, maccfg2);
1338
1339
1340 upsmr = in_be32(&uf_regs->upsmr);
1341 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1342 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1343 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1344 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1349 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1350 upsmr |= UCC_GETH_UPSMR_RPM;
1351 switch (ugeth->max_speed) {
1352 case SPEED_10:
1353 upsmr |= UCC_GETH_UPSMR_R10M;
1354
1355 case SPEED_100:
1356 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1357 upsmr |= UCC_GETH_UPSMR_RMM;
1358 }
1359 }
1360 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1361 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1362 upsmr |= UCC_GETH_UPSMR_TBIM;
1363 }
1364 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1365 upsmr |= UCC_GETH_UPSMR_SGMM;
1366
1367 out_be32(&uf_regs->upsmr, upsmr);
1368
1369
1370
1371
1372 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1373 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1374 struct ucc_geth_info *ug_info = ugeth->ug_info;
1375 struct phy_device *tbiphy;
1376
1377 if (!ug_info->tbi_node)
1378 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1379
1380 tbiphy = of_phy_find_device(ug_info->tbi_node);
1381 if (!tbiphy)
1382 pr_warn("Could not get TBI device\n");
1383
1384 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1385 value &= ~0x1000;
1386 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1387
1388 put_device(&tbiphy->mdio.dev);
1389 }
1390
1391 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1392
1393 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1394 if (ret_val != 0) {
1395 if (netif_msg_probe(ugeth))
1396 pr_err("Preamble length must be between 3 and 7 inclusive\n");
1397 return ret_val;
1398 }
1399
1400 return 0;
1401}
1402
1403static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1404{
1405 struct ucc_fast_private *uccf;
1406 u32 cecr_subblock;
1407 u32 temp;
1408 int i = 10;
1409
1410 uccf = ugeth->uccf;
1411
1412
1413 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1414 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);
1415
1416
1417 cecr_subblock =
1418 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1419 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1420 QE_CR_PROTOCOL_ETHERNET, 0);
1421
1422
1423 do {
1424 msleep(10);
1425 temp = in_be32(uccf->p_ucce);
1426 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1427
1428 uccf->stopped_tx = 1;
1429
1430 return 0;
1431}
1432
1433static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1434{
1435 struct ucc_fast_private *uccf;
1436 u32 cecr_subblock;
1437 u8 temp;
1438 int i = 10;
1439
1440 uccf = ugeth->uccf;
1441
1442
1443 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1444 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1445 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1446
1447
1448
1449 do {
1450
1451 cecr_subblock =
1452 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1453 ucc_num);
1454 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1455 QE_CR_PROTOCOL_ETHERNET, 0);
1456 msleep(10);
1457 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1458 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1459
1460 uccf->stopped_rx = 1;
1461
1462 return 0;
1463}
1464
1465static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1466{
1467 struct ucc_fast_private *uccf;
1468 u32 cecr_subblock;
1469
1470 uccf = ugeth->uccf;
1471
1472 cecr_subblock =
1473 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1474 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1475 uccf->stopped_tx = 0;
1476
1477 return 0;
1478}
1479
1480static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1481{
1482 struct ucc_fast_private *uccf;
1483 u32 cecr_subblock;
1484
1485 uccf = ugeth->uccf;
1486
1487 cecr_subblock =
1488 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1489 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1490 0);
1491 uccf->stopped_rx = 0;
1492
1493 return 0;
1494}
1495
1496static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1497{
1498 struct ucc_fast_private *uccf;
1499 int enabled_tx, enabled_rx;
1500
1501 uccf = ugeth->uccf;
1502
1503
1504 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1505 if (netif_msg_probe(ugeth))
1506 pr_err("ucc_num out of range\n");
1507 return -EINVAL;
1508 }
1509
1510 enabled_tx = uccf->enabled_tx;
1511 enabled_rx = uccf->enabled_rx;
1512
1513
1514
1515 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1516 ugeth_restart_tx(ugeth);
1517 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1518 ugeth_restart_rx(ugeth);
1519
1520 ucc_fast_enable(uccf, mode);
1521
1522 return 0;
1523
1524}
1525
1526static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1527{
1528 struct ucc_fast_private *uccf;
1529
1530 uccf = ugeth->uccf;
1531
1532
1533 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1534 if (netif_msg_probe(ugeth))
1535 pr_err("ucc_num out of range\n");
1536 return -EINVAL;
1537 }
1538
1539
1540 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1541 ugeth_graceful_stop_tx(ugeth);
1542
1543
1544 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1545 ugeth_graceful_stop_rx(ugeth);
1546
1547 ucc_fast_disable(ugeth->uccf, mode);
1548
1549 return 0;
1550}
1551
1552static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1553{
1554
1555 netif_device_detach(ugeth->ndev);
1556
1557
1558 netif_tx_disable(ugeth->ndev);
1559
1560
1561 disable_irq(ugeth->ug_info->uf_info.irq);
1562
1563
1564 napi_disable(&ugeth->napi);
1565}
1566
1567static void ugeth_activate(struct ucc_geth_private *ugeth)
1568{
1569 napi_enable(&ugeth->napi);
1570 enable_irq(ugeth->ug_info->uf_info.irq);
1571 netif_device_attach(ugeth->ndev);
1572}
1573
1574
1575
1576
1577
1578
1579
1580
1581static void adjust_link(struct net_device *dev)
1582{
1583 struct ucc_geth_private *ugeth = netdev_priv(dev);
1584 struct ucc_geth __iomem *ug_regs;
1585 struct ucc_fast __iomem *uf_regs;
1586 struct phy_device *phydev = ugeth->phydev;
1587 int new_state = 0;
1588
1589 ug_regs = ugeth->ug_regs;
1590 uf_regs = ugeth->uccf->uf_regs;
1591
1592 if (phydev->link) {
1593 u32 tempval = in_be32(&ug_regs->maccfg2);
1594 u32 upsmr = in_be32(&uf_regs->upsmr);
1595
1596
1597 if (phydev->duplex != ugeth->oldduplex) {
1598 new_state = 1;
1599 if (!(phydev->duplex))
1600 tempval &= ~(MACCFG2_FDX);
1601 else
1602 tempval |= MACCFG2_FDX;
1603 ugeth->oldduplex = phydev->duplex;
1604 }
1605
1606 if (phydev->speed != ugeth->oldspeed) {
1607 new_state = 1;
1608 switch (phydev->speed) {
1609 case SPEED_1000:
1610 tempval = ((tempval &
1611 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1612 MACCFG2_INTERFACE_MODE_BYTE);
1613 break;
1614 case SPEED_100:
1615 case SPEED_10:
1616 tempval = ((tempval &
1617 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1618 MACCFG2_INTERFACE_MODE_NIBBLE);
1619
1620 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1621 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1626 if (phydev->speed == SPEED_10)
1627 upsmr |= UCC_GETH_UPSMR_R10M;
1628 else
1629 upsmr &= ~UCC_GETH_UPSMR_R10M;
1630 }
1631 break;
1632 default:
1633 if (netif_msg_link(ugeth))
1634 pr_warn(
1635 "%s: Ack! Speed (%d) is not 10/100/1000!",
1636 dev->name, phydev->speed);
1637 break;
1638 }
1639 ugeth->oldspeed = phydev->speed;
1640 }
1641
1642 if (!ugeth->oldlink) {
1643 new_state = 1;
1644 ugeth->oldlink = 1;
1645 }
1646
1647 if (new_state) {
1648
1649
1650
1651
1652
1653
1654
1655 ugeth_quiesce(ugeth);
1656 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1657
1658 out_be32(&ug_regs->maccfg2, tempval);
1659 out_be32(&uf_regs->upsmr, upsmr);
1660
1661 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1662 ugeth_activate(ugeth);
1663 }
1664 } else if (ugeth->oldlink) {
1665 new_state = 1;
1666 ugeth->oldlink = 0;
1667 ugeth->oldspeed = 0;
1668 ugeth->oldduplex = -1;
1669 }
1670
1671 if (new_state && netif_msg_link(ugeth))
1672 phy_print_status(phydev);
1673}
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683static void uec_configure_serdes(struct net_device *dev)
1684{
1685 struct ucc_geth_private *ugeth = netdev_priv(dev);
1686 struct ucc_geth_info *ug_info = ugeth->ug_info;
1687 struct phy_device *tbiphy;
1688
1689 if (!ug_info->tbi_node) {
1690 dev_warn(&dev->dev, "SGMII mode requires that the device "
1691 "tree specify a tbi-handle\n");
1692 return;
1693 }
1694
1695 tbiphy = of_phy_find_device(ug_info->tbi_node);
1696 if (!tbiphy) {
1697 dev_err(&dev->dev, "error: Could not get TBI device\n");
1698 return;
1699 }
1700
1701
1702
1703
1704
1705
1706
1707 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
1708 put_device(&tbiphy->mdio.dev);
1709 return;
1710 }
1711
1712
1713 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1714
1715 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1716
1717 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1718
1719 put_device(&tbiphy->mdio.dev);
1720}
1721
1722
1723
1724
1725static int init_phy(struct net_device *dev)
1726{
1727 struct ucc_geth_private *priv = netdev_priv(dev);
1728 struct ucc_geth_info *ug_info = priv->ug_info;
1729 struct phy_device *phydev;
1730
1731 priv->oldlink = 0;
1732 priv->oldspeed = 0;
1733 priv->oldduplex = -1;
1734
1735 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1736 priv->phy_interface);
1737 if (!phydev) {
1738 dev_err(&dev->dev, "Could not attach to PHY\n");
1739 return -ENODEV;
1740 }
1741
1742 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1743 uec_configure_serdes(dev);
1744
1745 phy_set_max_speed(phydev, priv->max_speed);
1746
1747 priv->phydev = phydev;
1748
1749 return 0;
1750}
1751
1752static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1753{
1754#ifdef DEBUG
1755 ucc_fast_dump_regs(ugeth->uccf);
1756 dump_regs(ugeth);
1757 dump_bds(ugeth);
1758#endif
1759}
1760
1761static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1762 ugeth,
1763 enum enet_addr_type
1764 enet_addr_type)
1765{
1766 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1767 struct ucc_fast_private *uccf;
1768 enum comm_dir comm_dir;
1769 struct list_head *p_lh;
1770 u16 i, num;
1771 u32 __iomem *addr_h;
1772 u32 __iomem *addr_l;
1773 u8 *p_counter;
1774
1775 uccf = ugeth->uccf;
1776
1777 p_82xx_addr_filt =
1778 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1779 ugeth->p_rx_glbl_pram->addressfiltering;
1780
1781 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1782 addr_h = &(p_82xx_addr_filt->gaddr_h);
1783 addr_l = &(p_82xx_addr_filt->gaddr_l);
1784 p_lh = &ugeth->group_hash_q;
1785 p_counter = &(ugeth->numGroupAddrInHash);
1786 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1787 addr_h = &(p_82xx_addr_filt->iaddr_h);
1788 addr_l = &(p_82xx_addr_filt->iaddr_l);
1789 p_lh = &ugeth->ind_hash_q;
1790 p_counter = &(ugeth->numIndAddrInHash);
1791 } else
1792 return -EINVAL;
1793
1794 comm_dir = 0;
1795 if (uccf->enabled_tx)
1796 comm_dir |= COMM_DIR_TX;
1797 if (uccf->enabled_rx)
1798 comm_dir |= COMM_DIR_RX;
1799 if (comm_dir)
1800 ugeth_disable(ugeth, comm_dir);
1801
1802
1803 out_be32(addr_h, 0x00000000);
1804 out_be32(addr_l, 0x00000000);
1805
1806 if (!p_lh)
1807 return 0;
1808
1809 num = *p_counter;
1810
1811
1812 for (i = 0; i < num; i++)
1813 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1814
1815 *p_counter = 0;
1816
1817 if (comm_dir)
1818 ugeth_enable(ugeth, comm_dir);
1819
1820 return 0;
1821}
1822
1823static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1824 u8 paddr_num)
1825{
1826 ugeth->indAddrRegUsed[paddr_num] = 0;
1827 return hw_clear_addr_in_paddr(ugeth, paddr_num);
1828}
1829
1830static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1831{
1832 struct ucc_geth_info *ug_info;
1833 struct ucc_fast_info *uf_info;
1834 u16 i, j;
1835 u8 __iomem *bd;
1836
1837
1838 ug_info = ugeth->ug_info;
1839 uf_info = &ug_info->uf_info;
1840
1841 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1842 if (ugeth->p_rx_bd_ring[i]) {
1843
1844 bd = ugeth->p_rx_bd_ring[i];
1845 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1846 if (ugeth->rx_skbuff[i][j]) {
1847 dma_unmap_single(ugeth->dev,
1848 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1849 ugeth->ug_info->
1850 uf_info.max_rx_buf_length +
1851 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1852 DMA_FROM_DEVICE);
1853 dev_kfree_skb_any(
1854 ugeth->rx_skbuff[i][j]);
1855 ugeth->rx_skbuff[i][j] = NULL;
1856 }
1857 bd += sizeof(struct qe_bd);
1858 }
1859
1860 kfree(ugeth->rx_skbuff[i]);
1861
1862 if (ugeth->ug_info->uf_info.bd_mem_part ==
1863 MEM_PART_SYSTEM)
1864 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1865 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1866 MEM_PART_MURAM)
1867 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1868 ugeth->p_rx_bd_ring[i] = NULL;
1869 }
1870 }
1871
1872}
1873
1874static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1875{
1876 struct ucc_geth_info *ug_info;
1877 struct ucc_fast_info *uf_info;
1878 u16 i, j;
1879 u8 __iomem *bd;
1880
1881 ug_info = ugeth->ug_info;
1882 uf_info = &ug_info->uf_info;
1883
1884 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1885 bd = ugeth->p_tx_bd_ring[i];
1886 if (!bd)
1887 continue;
1888 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1889 if (ugeth->tx_skbuff[i][j]) {
1890 dma_unmap_single(ugeth->dev,
1891 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1892 (in_be32((u32 __iomem *)bd) &
1893 BD_LENGTH_MASK),
1894 DMA_TO_DEVICE);
1895 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1896 ugeth->tx_skbuff[i][j] = NULL;
1897 }
1898 }
1899
1900 kfree(ugeth->tx_skbuff[i]);
1901
1902 if (ugeth->p_tx_bd_ring[i]) {
1903 if (ugeth->ug_info->uf_info.bd_mem_part ==
1904 MEM_PART_SYSTEM)
1905 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1906 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1907 MEM_PART_MURAM)
1908 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1909 ugeth->p_tx_bd_ring[i] = NULL;
1910 }
1911 }
1912
1913}
1914
1915static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1916{
1917 if (!ugeth)
1918 return;
1919
1920 if (ugeth->uccf) {
1921 ucc_fast_free(ugeth->uccf);
1922 ugeth->uccf = NULL;
1923 }
1924
1925 if (ugeth->p_thread_data_tx) {
1926 qe_muram_free(ugeth->thread_dat_tx_offset);
1927 ugeth->p_thread_data_tx = NULL;
1928 }
1929 if (ugeth->p_thread_data_rx) {
1930 qe_muram_free(ugeth->thread_dat_rx_offset);
1931 ugeth->p_thread_data_rx = NULL;
1932 }
1933 if (ugeth->p_exf_glbl_param) {
1934 qe_muram_free(ugeth->exf_glbl_param_offset);
1935 ugeth->p_exf_glbl_param = NULL;
1936 }
1937 if (ugeth->p_rx_glbl_pram) {
1938 qe_muram_free(ugeth->rx_glbl_pram_offset);
1939 ugeth->p_rx_glbl_pram = NULL;
1940 }
1941 if (ugeth->p_tx_glbl_pram) {
1942 qe_muram_free(ugeth->tx_glbl_pram_offset);
1943 ugeth->p_tx_glbl_pram = NULL;
1944 }
1945 if (ugeth->p_send_q_mem_reg) {
1946 qe_muram_free(ugeth->send_q_mem_reg_offset);
1947 ugeth->p_send_q_mem_reg = NULL;
1948 }
1949 if (ugeth->p_scheduler) {
1950 qe_muram_free(ugeth->scheduler_offset);
1951 ugeth->p_scheduler = NULL;
1952 }
1953 if (ugeth->p_tx_fw_statistics_pram) {
1954 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1955 ugeth->p_tx_fw_statistics_pram = NULL;
1956 }
1957 if (ugeth->p_rx_fw_statistics_pram) {
1958 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1959 ugeth->p_rx_fw_statistics_pram = NULL;
1960 }
1961 if (ugeth->p_rx_irq_coalescing_tbl) {
1962 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1963 ugeth->p_rx_irq_coalescing_tbl = NULL;
1964 }
1965 if (ugeth->p_rx_bd_qs_tbl) {
1966 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1967 ugeth->p_rx_bd_qs_tbl = NULL;
1968 }
1969 if (ugeth->p_init_enet_param_shadow) {
1970 return_init_enet_entries(ugeth,
1971 &(ugeth->p_init_enet_param_shadow->
1972 rxthread[0]),
1973 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1974 ugeth->ug_info->riscRx, 1);
1975 return_init_enet_entries(ugeth,
1976 &(ugeth->p_init_enet_param_shadow->
1977 txthread[0]),
1978 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1979 ugeth->ug_info->riscTx, 0);
1980 kfree(ugeth->p_init_enet_param_shadow);
1981 ugeth->p_init_enet_param_shadow = NULL;
1982 }
1983 ucc_geth_free_tx(ugeth);
1984 ucc_geth_free_rx(ugeth);
1985 while (!list_empty(&ugeth->group_hash_q))
1986 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1987 (dequeue(&ugeth->group_hash_q)));
1988 while (!list_empty(&ugeth->ind_hash_q))
1989 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1990 (dequeue(&ugeth->ind_hash_q)));
1991 if (ugeth->ug_regs) {
1992 iounmap(ugeth->ug_regs);
1993 ugeth->ug_regs = NULL;
1994 }
1995}
1996
1997static void ucc_geth_set_multi(struct net_device *dev)
1998{
1999 struct ucc_geth_private *ugeth;
2000 struct netdev_hw_addr *ha;
2001 struct ucc_fast __iomem *uf_regs;
2002 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2003
2004 ugeth = netdev_priv(dev);
2005
2006 uf_regs = ugeth->uccf->uf_regs;
2007
2008 if (dev->flags & IFF_PROMISC) {
2009 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2010 } else {
2011 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2012
2013 p_82xx_addr_filt =
2014 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2015 p_rx_glbl_pram->addressfiltering;
2016
2017 if (dev->flags & IFF_ALLMULTI) {
2018
2019
2020
2021 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2022 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2023 } else {
2024
2025
2026 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2027 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2028
2029 netdev_for_each_mc_addr(ha, dev) {
2030
2031
2032
2033 hw_add_addr_in_hash(ugeth, ha->addr);
2034 }
2035 }
2036 }
2037}
2038
2039static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2040{
2041 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2042 struct phy_device *phydev = ugeth->phydev;
2043
2044 ugeth_vdbg("%s: IN", __func__);
2045
2046
2047
2048
2049
2050
2051 phy_stop(phydev);
2052
2053
2054 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2055
2056
2057 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2058
2059
2060 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2061
2062
2063 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2064
2065 ucc_geth_memclean(ugeth);
2066}
2067
2068static int ucc_struct_init(struct ucc_geth_private *ugeth)
2069{
2070 struct ucc_geth_info *ug_info;
2071 struct ucc_fast_info *uf_info;
2072 int i;
2073
2074 ug_info = ugeth->ug_info;
2075 uf_info = &ug_info->uf_info;
2076
2077 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2078 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2079 if (netif_msg_probe(ugeth))
2080 pr_err("Bad memory partition value\n");
2081 return -EINVAL;
2082 }
2083
2084
2085 for (i = 0; i < ug_info->numQueuesRx; i++) {
2086 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2087 (ug_info->bdRingLenRx[i] %
2088 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2089 if (netif_msg_probe(ugeth))
2090 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2091 return -EINVAL;
2092 }
2093 }
2094
2095
2096 for (i = 0; i < ug_info->numQueuesTx; i++) {
2097 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2098 if (netif_msg_probe(ugeth))
2099 pr_err("Tx BD ring length must be no smaller than 2\n");
2100 return -EINVAL;
2101 }
2102 }
2103
2104
2105 if ((uf_info->max_rx_buf_length == 0) ||
2106 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2107 if (netif_msg_probe(ugeth))
2108 pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2109 return -EINVAL;
2110 }
2111
2112
2113 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2114 if (netif_msg_probe(ugeth))
2115 pr_err("number of tx queues too large\n");
2116 return -EINVAL;
2117 }
2118
2119
2120 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2121 if (netif_msg_probe(ugeth))
2122 pr_err("number of rx queues too large\n");
2123 return -EINVAL;
2124 }
2125
2126
2127 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2128 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2129 if (netif_msg_probe(ugeth))
2130 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2131 return -EINVAL;
2132 }
2133 }
2134
2135
2136 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2137 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2138 if (netif_msg_probe(ugeth))
2139 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2140 return -EINVAL;
2141 }
2142 }
2143
2144 if (ug_info->cam && !ug_info->ecamptr) {
2145 if (netif_msg_probe(ugeth))
2146 pr_err("If cam mode is chosen, must supply cam ptr\n");
2147 return -EINVAL;
2148 }
2149
2150 if ((ug_info->numStationAddresses !=
2151 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2152 ug_info->rxExtendedFiltering) {
2153 if (netif_msg_probe(ugeth))
2154 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2155 return -EINVAL;
2156 }
2157
2158
2159 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;
2160 for (i = 0; i < ug_info->numQueuesRx; i++)
2161 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2162
2163 for (i = 0; i < ug_info->numQueuesTx; i++)
2164 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2165
2166 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2167 if (netif_msg_probe(ugeth))
2168 pr_err("Failed to init uccf\n");
2169 return -ENOMEM;
2170 }
2171
2172
2173
2174
2175 if (qe_get_num_of_risc() == 4) {
2176 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2177 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2178 }
2179
2180 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2181 if (!ugeth->ug_regs) {
2182 if (netif_msg_probe(ugeth))
2183 pr_err("Failed to ioremap regs\n");
2184 return -ENOMEM;
2185 }
2186
2187 return 0;
2188}
2189
2190static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2191{
2192 struct ucc_geth_info *ug_info;
2193 struct ucc_fast_info *uf_info;
2194 int length;
2195 u16 i, j;
2196 u8 __iomem *bd;
2197
2198 ug_info = ugeth->ug_info;
2199 uf_info = &ug_info->uf_info;
2200
2201
2202 for (j = 0; j < ug_info->numQueuesTx; j++) {
2203
2204
2205
2206 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2207 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2208 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2209 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2210 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2211 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2212 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2213 u32 align = 4;
2214 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2215 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2216 ugeth->tx_bd_ring_offset[j] =
2217 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2218
2219 if (ugeth->tx_bd_ring_offset[j] != 0)
2220 ugeth->p_tx_bd_ring[j] =
2221 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2222 align) & ~(align - 1));
2223 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2224 ugeth->tx_bd_ring_offset[j] =
2225 qe_muram_alloc(length,
2226 UCC_GETH_TX_BD_RING_ALIGNMENT);
2227 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2228 ugeth->p_tx_bd_ring[j] =
2229 (u8 __iomem *) qe_muram_addr(ugeth->
2230 tx_bd_ring_offset[j]);
2231 }
2232 if (!ugeth->p_tx_bd_ring[j]) {
2233 if (netif_msg_ifup(ugeth))
2234 pr_err("Can not allocate memory for Tx bd rings\n");
2235 return -ENOMEM;
2236 }
2237
2238 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2239 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2240 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2241 }
2242
2243
2244 for (j = 0; j < ug_info->numQueuesTx; j++) {
2245
2246 ugeth->tx_skbuff[j] =
2247 kmalloc_array(ugeth->ug_info->bdRingLenTx[j],
2248 sizeof(struct sk_buff *), GFP_KERNEL);
2249
2250 if (ugeth->tx_skbuff[j] == NULL) {
2251 if (netif_msg_ifup(ugeth))
2252 pr_err("Could not allocate tx_skbuff\n");
2253 return -ENOMEM;
2254 }
2255
2256 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2257 ugeth->tx_skbuff[j][i] = NULL;
2258
2259 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2260 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2261 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2262
2263 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2264
2265 out_be32((u32 __iomem *)bd, 0);
2266 bd += sizeof(struct qe_bd);
2267 }
2268 bd -= sizeof(struct qe_bd);
2269
2270 out_be32((u32 __iomem *)bd, T_W);
2271 }
2272
2273 return 0;
2274}
2275
2276static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2277{
2278 struct ucc_geth_info *ug_info;
2279 struct ucc_fast_info *uf_info;
2280 int length;
2281 u16 i, j;
2282 u8 __iomem *bd;
2283
2284 ug_info = ugeth->ug_info;
2285 uf_info = &ug_info->uf_info;
2286
2287
2288 for (j = 0; j < ug_info->numQueuesRx; j++) {
2289 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2290 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2291 u32 align = 4;
2292 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2293 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2294 ugeth->rx_bd_ring_offset[j] =
2295 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2296 if (ugeth->rx_bd_ring_offset[j] != 0)
2297 ugeth->p_rx_bd_ring[j] =
2298 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2299 align) & ~(align - 1));
2300 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2301 ugeth->rx_bd_ring_offset[j] =
2302 qe_muram_alloc(length,
2303 UCC_GETH_RX_BD_RING_ALIGNMENT);
2304 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2305 ugeth->p_rx_bd_ring[j] =
2306 (u8 __iomem *) qe_muram_addr(ugeth->
2307 rx_bd_ring_offset[j]);
2308 }
2309 if (!ugeth->p_rx_bd_ring[j]) {
2310 if (netif_msg_ifup(ugeth))
2311 pr_err("Can not allocate memory for Rx bd rings\n");
2312 return -ENOMEM;
2313 }
2314 }
2315
2316
2317 for (j = 0; j < ug_info->numQueuesRx; j++) {
2318
2319 ugeth->rx_skbuff[j] =
2320 kmalloc_array(ugeth->ug_info->bdRingLenRx[j],
2321 sizeof(struct sk_buff *), GFP_KERNEL);
2322
2323 if (ugeth->rx_skbuff[j] == NULL) {
2324 if (netif_msg_ifup(ugeth))
2325 pr_err("Could not allocate rx_skbuff\n");
2326 return -ENOMEM;
2327 }
2328
2329 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2330 ugeth->rx_skbuff[j][i] = NULL;
2331
2332 ugeth->skb_currx[j] = 0;
2333 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2334 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2335
2336 out_be32((u32 __iomem *)bd, R_I);
2337
2338 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2339 bd += sizeof(struct qe_bd);
2340 }
2341 bd -= sizeof(struct qe_bd);
2342
2343 out_be32((u32 __iomem *)bd, R_W);
2344 }
2345
2346 return 0;
2347}
2348
2349static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2350{
2351 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2352 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2353 struct ucc_fast_private *uccf;
2354 struct ucc_geth_info *ug_info;
2355 struct ucc_fast_info *uf_info;
2356 struct ucc_fast __iomem *uf_regs;
2357 struct ucc_geth __iomem *ug_regs;
2358 int ret_val = -EINVAL;
2359 u32 remoder = UCC_GETH_REMODER_INIT;
2360 u32 init_enet_pram_offset, cecr_subblock, command;
2361 u32 ifstat, i, j, size, l2qt, l3qt;
2362 u16 temoder = UCC_GETH_TEMODER_INIT;
2363 u16 test;
2364 u8 function_code = 0;
2365 u8 __iomem *endOfRing;
2366 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2367
2368 ugeth_vdbg("%s: IN", __func__);
2369 uccf = ugeth->uccf;
2370 ug_info = ugeth->ug_info;
2371 uf_info = &ug_info->uf_info;
2372 uf_regs = uccf->uf_regs;
2373 ug_regs = ugeth->ug_regs;
2374
2375 switch (ug_info->numThreadsRx) {
2376 case UCC_GETH_NUM_OF_THREADS_1:
2377 numThreadsRxNumerical = 1;
2378 break;
2379 case UCC_GETH_NUM_OF_THREADS_2:
2380 numThreadsRxNumerical = 2;
2381 break;
2382 case UCC_GETH_NUM_OF_THREADS_4:
2383 numThreadsRxNumerical = 4;
2384 break;
2385 case UCC_GETH_NUM_OF_THREADS_6:
2386 numThreadsRxNumerical = 6;
2387 break;
2388 case UCC_GETH_NUM_OF_THREADS_8:
2389 numThreadsRxNumerical = 8;
2390 break;
2391 default:
2392 if (netif_msg_ifup(ugeth))
2393 pr_err("Bad number of Rx threads value\n");
2394 return -EINVAL;
2395 }
2396
2397 switch (ug_info->numThreadsTx) {
2398 case UCC_GETH_NUM_OF_THREADS_1:
2399 numThreadsTxNumerical = 1;
2400 break;
2401 case UCC_GETH_NUM_OF_THREADS_2:
2402 numThreadsTxNumerical = 2;
2403 break;
2404 case UCC_GETH_NUM_OF_THREADS_4:
2405 numThreadsTxNumerical = 4;
2406 break;
2407 case UCC_GETH_NUM_OF_THREADS_6:
2408 numThreadsTxNumerical = 6;
2409 break;
2410 case UCC_GETH_NUM_OF_THREADS_8:
2411 numThreadsTxNumerical = 8;
2412 break;
2413 default:
2414 if (netif_msg_ifup(ugeth))
2415 pr_err("Bad number of Tx threads value\n");
2416 return -EINVAL;
2417 }
2418
2419
2420 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2421 ug_info->ipAddressAlignment ||
2422 (ug_info->numStationAddresses !=
2423 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2424
2425 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2426 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2427 (ug_info->vlanOperationNonTagged !=
2428 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2429
2430 init_default_reg_vals(&uf_regs->upsmr,
2431 &ug_regs->maccfg1, &ug_regs->maccfg2);
2432
2433
2434
2435 init_rx_parameters(ug_info->bro,
2436 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2437
2438
2439
2440
2441
2442
2443 init_flow_control_params(ug_info->aufc,
2444 ug_info->receiveFlowControl,
2445 ug_info->transmitFlowControl,
2446 ug_info->pausePeriod,
2447 ug_info->extensionField,
2448 &uf_regs->upsmr,
2449 &ug_regs->uempr, &ug_regs->maccfg1);
2450
2451 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2452
2453
2454
2455 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2456 ug_info->nonBackToBackIfgPart2,
2457 ug_info->
2458 miminumInterFrameGapEnforcement,
2459 ug_info->backToBackInterFrameGap,
2460 &ug_regs->ipgifg);
2461 if (ret_val != 0) {
2462 if (netif_msg_ifup(ugeth))
2463 pr_err("IPGIFG initialization parameter too large\n");
2464 return ret_val;
2465 }
2466
2467
2468
2469 ret_val = init_half_duplex_params(ug_info->altBeb,
2470 ug_info->backPressureNoBackoff,
2471 ug_info->noBackoff,
2472 ug_info->excessDefer,
2473 ug_info->altBebTruncation,
2474 ug_info->maxRetransmission,
2475 ug_info->collisionWindow,
2476 &ug_regs->hafdup);
2477 if (ret_val != 0) {
2478 if (netif_msg_ifup(ugeth))
2479 pr_err("Half Duplex initialization parameter too large\n");
2480 return ret_val;
2481 }
2482
2483
2484
2485
2486 ifstat = in_be32(&ug_regs->ifstat);
2487
2488
2489
2490 out_be32(&ug_regs->uempr, 0);
2491
2492
2493
2494 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2495 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2496 0, &uf_regs->upsmr, &ug_regs->uescr);
2497
2498 ret_val = ucc_geth_alloc_tx(ugeth);
2499 if (ret_val != 0)
2500 return ret_val;
2501
2502 ret_val = ucc_geth_alloc_rx(ugeth);
2503 if (ret_val != 0)
2504 return ret_val;
2505
2506
2507
2508
2509
2510
2511 ugeth->tx_glbl_pram_offset =
2512 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2513 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2514 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2515 if (netif_msg_ifup(ugeth))
2516 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2517 return -ENOMEM;
2518 }
2519 ugeth->p_tx_glbl_pram =
2520 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2521 tx_glbl_pram_offset);
2522
2523 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2524
2525
2526
2527
2528
2529 ugeth->thread_dat_tx_offset =
2530 qe_muram_alloc(numThreadsTxNumerical *
2531 sizeof(struct ucc_geth_thread_data_tx) +
2532 32 * (numThreadsTxNumerical == 1),
2533 UCC_GETH_THREAD_DATA_ALIGNMENT);
2534 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2535 if (netif_msg_ifup(ugeth))
2536 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2537 return -ENOMEM;
2538 }
2539
2540 ugeth->p_thread_data_tx =
2541 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2542 thread_dat_tx_offset);
2543 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2544
2545
2546 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2547 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2548 ug_info->vtagtable[i]);
2549
2550
2551 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2552 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2553 ug_info->iphoffset[i]);
2554
2555
2556
2557 ugeth->send_q_mem_reg_offset =
2558 qe_muram_alloc(ug_info->numQueuesTx *
2559 sizeof(struct ucc_geth_send_queue_qd),
2560 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2561 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2562 if (netif_msg_ifup(ugeth))
2563 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2564 return -ENOMEM;
2565 }
2566
2567 ugeth->p_send_q_mem_reg =
2568 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2569 send_q_mem_reg_offset);
2570 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2571
2572
2573
2574 for (i = 0; i < ug_info->numQueuesTx; i++) {
2575 endOfRing =
2576 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2577 1) * sizeof(struct qe_bd);
2578 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2579 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2580 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2581 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2582 last_bd_completed_address,
2583 (u32) virt_to_phys(endOfRing));
2584 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2585 MEM_PART_MURAM) {
2586 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2587 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2588 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2589 last_bd_completed_address,
2590 (u32)qe_muram_dma(endOfRing));
2591 }
2592 }
2593
2594
2595
2596 if (ug_info->numQueuesTx > 1) {
2597
2598 ugeth->scheduler_offset =
2599 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2600 UCC_GETH_SCHEDULER_ALIGNMENT);
2601 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2602 if (netif_msg_ifup(ugeth))
2603 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2604 return -ENOMEM;
2605 }
2606
2607 ugeth->p_scheduler =
2608 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2609 scheduler_offset);
2610 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2611 ugeth->scheduler_offset);
2612
2613 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2614
2615
2616 out_be32(&ugeth->p_scheduler->mblinterval,
2617 ug_info->mblinterval);
2618 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2619 ug_info->nortsrbytetime);
2620 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2621 out_8(&ugeth->p_scheduler->strictpriorityq,
2622 ug_info->strictpriorityq);
2623 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2624 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2625 for (i = 0; i < NUM_TX_QUEUES; i++)
2626 out_8(&ugeth->p_scheduler->weightfactor[i],
2627 ug_info->weightfactor[i]);
2628
2629
2630 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2631 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2632 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2633 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2634 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2635 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2636 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2637 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2638 }
2639
2640
2641
2642 if (ug_info->
2643 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2644 ugeth->tx_fw_statistics_pram_offset =
2645 qe_muram_alloc(sizeof
2646 (struct ucc_geth_tx_firmware_statistics_pram),
2647 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2648 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2649 if (netif_msg_ifup(ugeth))
2650 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2651 return -ENOMEM;
2652 }
2653 ugeth->p_tx_fw_statistics_pram =
2654 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2655 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2656
2657 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2658 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2659 }
2660
2661
2662
2663
2664 if (ug_info->numQueuesTx > 1)
2665 temoder |= TEMODER_SCHEDULER_ENABLE;
2666 if (ug_info->ipCheckSumGenerate)
2667 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2668 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2669 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2670
2671 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2672
2673
2674 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2675
2676
2677
2678 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2679
2680
2681
2682 ugeth->rx_glbl_pram_offset =
2683 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2684 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2685 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2686 if (netif_msg_ifup(ugeth))
2687 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2688 return -ENOMEM;
2689 }
2690 ugeth->p_rx_glbl_pram =
2691 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2692 rx_glbl_pram_offset);
2693
2694 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2695
2696
2697
2698
2699
2700 ugeth->thread_dat_rx_offset =
2701 qe_muram_alloc(numThreadsRxNumerical *
2702 sizeof(struct ucc_geth_thread_data_rx),
2703 UCC_GETH_THREAD_DATA_ALIGNMENT);
2704 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2705 if (netif_msg_ifup(ugeth))
2706 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2707 return -ENOMEM;
2708 }
2709
2710 ugeth->p_thread_data_rx =
2711 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2712 thread_dat_rx_offset);
2713 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2714
2715
2716 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2717
2718
2719 if (ug_info->
2720 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2721 ugeth->rx_fw_statistics_pram_offset =
2722 qe_muram_alloc(sizeof
2723 (struct ucc_geth_rx_firmware_statistics_pram),
2724 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2725 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2726 if (netif_msg_ifup(ugeth))
2727 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2728 return -ENOMEM;
2729 }
2730 ugeth->p_rx_fw_statistics_pram =
2731 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2732 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2733
2734 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2735 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2736 }
2737
2738
2739
2740
2741 ugeth->rx_irq_coalescing_tbl_offset =
2742 qe_muram_alloc(ug_info->numQueuesRx *
2743 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2744 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2745 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2746 if (netif_msg_ifup(ugeth))
2747 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2748 return -ENOMEM;
2749 }
2750
2751 ugeth->p_rx_irq_coalescing_tbl =
2752 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2753 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2754 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2755 ugeth->rx_irq_coalescing_tbl_offset);
2756
2757
2758 for (i = 0; i < ug_info->numQueuesRx; i++) {
2759 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2760 interruptcoalescingmaxvalue,
2761 ug_info->interruptcoalescingmaxvalue[i]);
2762 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2763 interruptcoalescingcounter,
2764 ug_info->interruptcoalescingmaxvalue[i]);
2765 }
2766
2767
2768 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2769 &ugeth->p_rx_glbl_pram->mrblr);
2770
2771 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2772
2773 init_min_frame_len(ug_info->minFrameLength,
2774 &ugeth->p_rx_glbl_pram->minflr,
2775 &ugeth->p_rx_glbl_pram->mrblr);
2776
2777 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2778
2779 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2780
2781
2782 l2qt = 0;
2783 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2784 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2785 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2786
2787
2788 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2789 l3qt = 0;
2790 for (i = 0; i < 8; i++)
2791 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2792 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2793 }
2794
2795
2796 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2797
2798
2799 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2800
2801
2802 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2803
2804
2805
2806 ugeth->rx_bd_qs_tbl_offset =
2807 qe_muram_alloc(ug_info->numQueuesRx *
2808 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2809 sizeof(struct ucc_geth_rx_prefetched_bds)),
2810 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2811 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2812 if (netif_msg_ifup(ugeth))
2813 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2814 return -ENOMEM;
2815 }
2816
2817 ugeth->p_rx_bd_qs_tbl =
2818 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2819 rx_bd_qs_tbl_offset);
2820 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2821
2822 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2823 0,
2824 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2825 sizeof(struct ucc_geth_rx_prefetched_bds)));
2826
2827
2828
2829 for (i = 0; i < ug_info->numQueuesRx; i++) {
2830 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2831 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2832 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2833 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2834 MEM_PART_MURAM) {
2835 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2836 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2837 }
2838
2839 }
2840
2841
2842
2843
2844 if (ugeth->rx_extended_features)
2845 remoder |= REMODER_RX_EXTENDED_FEATURES;
2846 if (ug_info->rxExtendedFiltering)
2847 remoder |= REMODER_RX_EXTENDED_FILTERING;
2848 if (ug_info->dynamicMaxFrameLength)
2849 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2850 if (ug_info->dynamicMinFrameLength)
2851 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2852 remoder |=
2853 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2854 remoder |=
2855 ug_info->
2856 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2857 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2858 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2859 if (ug_info->ipCheckSumCheck)
2860 remoder |= REMODER_IP_CHECKSUM_CHECK;
2861 if (ug_info->ipAddressAlignment)
2862 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2863 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2864
2865
2866
2867
2868 init_firmware_statistics_gathering_mode((ug_info->
2869 statisticsMode &
2870 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2871 (ug_info->statisticsMode &
2872 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2873 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2874 ugeth->tx_fw_statistics_pram_offset,
2875 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2876 ugeth->rx_fw_statistics_pram_offset,
2877 &ugeth->p_tx_glbl_pram->temoder,
2878 &ugeth->p_rx_glbl_pram->remoder);
2879
2880
2881 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2882
2883
2884 if (ug_info->rxExtendedFiltering) {
2885 if (!ug_info->extendedFilteringChainPointer) {
2886 if (netif_msg_ifup(ugeth))
2887 pr_err("Null Extended Filtering Chain Pointer\n");
2888 return -EINVAL;
2889 }
2890
2891
2892
2893 ugeth->exf_glbl_param_offset =
2894 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2895 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2896 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2897 if (netif_msg_ifup(ugeth))
2898 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2899 return -ENOMEM;
2900 }
2901
2902 ugeth->p_exf_glbl_param =
2903 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2904 exf_glbl_param_offset);
2905 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2906 ugeth->exf_glbl_param_offset);
2907 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2908 (u32) ug_info->extendedFilteringChainPointer);
2909
2910 } else {
2911
2912
2913
2914 for (j = 0; j < NUM_OF_PADDRS; j++)
2915 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2916
2917 p_82xx_addr_filt =
2918 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2919 p_rx_glbl_pram->addressfiltering;
2920
2921 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2922 ENET_ADDR_TYPE_GROUP);
2923 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2924 ENET_ADDR_TYPE_INDIVIDUAL);
2925 }
2926
2927
2928
2929
2930
2931 command = QE_INIT_TX_RX;
2932
2933
2934
2935
2936
2937
2938
2939
2940 if (!(ugeth->p_init_enet_param_shadow =
2941 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2942 if (netif_msg_ifup(ugeth))
2943 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2944 return -ENOMEM;
2945 }
2946
2947 memset((char *)ugeth->p_init_enet_param_shadow,
2948 0, sizeof(struct ucc_geth_init_pram));
2949
2950
2951
2952 ugeth->p_init_enet_param_shadow->resinit1 =
2953 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2954 ugeth->p_init_enet_param_shadow->resinit2 =
2955 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2956 ugeth->p_init_enet_param_shadow->resinit3 =
2957 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2958 ugeth->p_init_enet_param_shadow->resinit4 =
2959 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2960 ugeth->p_init_enet_param_shadow->resinit5 =
2961 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2962 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2963 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2964 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2965 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2966
2967 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2968 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2969 if ((ug_info->largestexternallookupkeysize !=
2970 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2971 (ug_info->largestexternallookupkeysize !=
2972 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2973 (ug_info->largestexternallookupkeysize !=
2974 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2975 if (netif_msg_ifup(ugeth))
2976 pr_err("Invalid largest External Lookup Key Size\n");
2977 return -EINVAL;
2978 }
2979 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2980 ug_info->largestexternallookupkeysize;
2981 size = sizeof(struct ucc_geth_thread_rx_pram);
2982 if (ug_info->rxExtendedFiltering) {
2983 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2984 if (ug_info->largestexternallookupkeysize ==
2985 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2986 size +=
2987 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2988 if (ug_info->largestexternallookupkeysize ==
2989 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2990 size +=
2991 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2992 }
2993
2994 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2995 p_init_enet_param_shadow->rxthread[0]),
2996 (u8) (numThreadsRxNumerical + 1)
2997
2998 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2999 ug_info->riscRx, 1)) != 0) {
3000 if (netif_msg_ifup(ugeth))
3001 pr_err("Can not fill p_init_enet_param_shadow\n");
3002 return ret_val;
3003 }
3004
3005 ugeth->p_init_enet_param_shadow->txglobal =
3006 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3007 if ((ret_val =
3008 fill_init_enet_entries(ugeth,
3009 &(ugeth->p_init_enet_param_shadow->
3010 txthread[0]), numThreadsTxNumerical,
3011 sizeof(struct ucc_geth_thread_tx_pram),
3012 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3013 ug_info->riscTx, 0)) != 0) {
3014 if (netif_msg_ifup(ugeth))
3015 pr_err("Can not fill p_init_enet_param_shadow\n");
3016 return ret_val;
3017 }
3018
3019
3020 for (i = 0; i < ug_info->numQueuesRx; i++) {
3021 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3022 if (netif_msg_ifup(ugeth))
3023 pr_err("Can not fill Rx bds with buffers\n");
3024 return ret_val;
3025 }
3026 }
3027
3028
3029 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3030 if (IS_ERR_VALUE(init_enet_pram_offset)) {
3031 if (netif_msg_ifup(ugeth))
3032 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
3033 return -ENOMEM;
3034 }
3035 p_init_enet_pram =
3036 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3037
3038
3039 out_8(&p_init_enet_pram->resinit1,
3040 ugeth->p_init_enet_param_shadow->resinit1);
3041 out_8(&p_init_enet_pram->resinit2,
3042 ugeth->p_init_enet_param_shadow->resinit2);
3043 out_8(&p_init_enet_pram->resinit3,
3044 ugeth->p_init_enet_param_shadow->resinit3);
3045 out_8(&p_init_enet_pram->resinit4,
3046 ugeth->p_init_enet_param_shadow->resinit4);
3047 out_be16(&p_init_enet_pram->resinit5,
3048 ugeth->p_init_enet_param_shadow->resinit5);
3049 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3050 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3051 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3052 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3053 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3054 out_be32(&p_init_enet_pram->rxthread[i],
3055 ugeth->p_init_enet_param_shadow->rxthread[i]);
3056 out_be32(&p_init_enet_pram->txglobal,
3057 ugeth->p_init_enet_param_shadow->txglobal);
3058 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3059 out_be32(&p_init_enet_pram->txthread[i],
3060 ugeth->p_init_enet_param_shadow->txthread[i]);
3061
3062
3063 cecr_subblock =
3064 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3065 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3066 init_enet_pram_offset);
3067
3068
3069 qe_muram_free(init_enet_pram_offset);
3070
3071 return 0;
3072}
3073
3074
3075
3076static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3077{
3078 struct ucc_geth_private *ugeth = netdev_priv(dev);
3079#ifdef CONFIG_UGETH_TX_ON_DEMAND
3080 struct ucc_fast_private *uccf;
3081#endif
3082 u8 __iomem *bd;
3083 u32 bd_status;
3084 u8 txQ = 0;
3085 unsigned long flags;
3086
3087 ugeth_vdbg("%s: IN", __func__);
3088
3089 spin_lock_irqsave(&ugeth->lock, flags);
3090
3091 dev->stats.tx_bytes += skb->len;
3092
3093
3094 bd = ugeth->txBd[txQ];
3095 bd_status = in_be32((u32 __iomem *)bd);
3096
3097 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3098
3099
3100 ugeth->skb_curtx[txQ] =
3101 (ugeth->skb_curtx[txQ] +
3102 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3103
3104
3105 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3106 dma_map_single(ugeth->dev, skb->data,
3107 skb->len, DMA_TO_DEVICE));
3108
3109
3110
3111 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3112
3113
3114 out_be32((u32 __iomem *)bd, bd_status);
3115
3116
3117 if (!(bd_status & T_W))
3118 bd += sizeof(struct qe_bd);
3119 else
3120 bd = ugeth->p_tx_bd_ring[txQ];
3121
3122
3123
3124 if (bd == ugeth->confBd[txQ]) {
3125 if (!netif_queue_stopped(dev))
3126 netif_stop_queue(dev);
3127 }
3128
3129 ugeth->txBd[txQ] = bd;
3130
3131 skb_tx_timestamp(skb);
3132
3133 if (ugeth->p_scheduler) {
3134 ugeth->cpucount[txQ]++;
3135
3136
3137
3138
3139 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3140 }
3141
3142#ifdef CONFIG_UGETH_TX_ON_DEMAND
3143 uccf = ugeth->uccf;
3144 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3145#endif
3146 spin_unlock_irqrestore(&ugeth->lock, flags);
3147
3148 return NETDEV_TX_OK;
3149}
3150
3151static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3152{
3153 struct sk_buff *skb;
3154 u8 __iomem *bd;
3155 u16 length, howmany = 0;
3156 u32 bd_status;
3157 u8 *bdBuffer;
3158 struct net_device *dev;
3159
3160 ugeth_vdbg("%s: IN", __func__);
3161
3162 dev = ugeth->ndev;
3163
3164
3165 bd = ugeth->rxBd[rxQ];
3166
3167 bd_status = in_be32((u32 __iomem *)bd);
3168
3169
3170 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3171 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3172 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3173 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3174
3175
3176
3177 if (!skb ||
3178 (!(bd_status & (R_F | R_L))) ||
3179 (bd_status & R_ERRORS_FATAL)) {
3180 if (netif_msg_rx_err(ugeth))
3181 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3182 __LINE__, (u32)skb);
3183 dev_kfree_skb(skb);
3184
3185 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3186 dev->stats.rx_dropped++;
3187 } else {
3188 dev->stats.rx_packets++;
3189 howmany++;
3190
3191
3192 skb_put(skb, length);
3193
3194
3195 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3196
3197 dev->stats.rx_bytes += length;
3198
3199 netif_receive_skb(skb);
3200 }
3201
3202 skb = get_new_skb(ugeth, bd);
3203 if (!skb) {
3204 if (netif_msg_rx_err(ugeth))
3205 pr_warn("No Rx Data Buffer\n");
3206 dev->stats.rx_dropped++;
3207 break;
3208 }
3209
3210 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3211
3212
3213 ugeth->skb_currx[rxQ] =
3214 (ugeth->skb_currx[rxQ] +
3215 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3216
3217 if (bd_status & R_W)
3218 bd = ugeth->p_rx_bd_ring[rxQ];
3219 else
3220 bd += sizeof(struct qe_bd);
3221
3222 bd_status = in_be32((u32 __iomem *)bd);
3223 }
3224
3225 ugeth->rxBd[rxQ] = bd;
3226 return howmany;
3227}
3228
3229static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3230{
3231
3232 struct ucc_geth_private *ugeth = netdev_priv(dev);
3233 u8 __iomem *bd;
3234 u32 bd_status;
3235
3236 bd = ugeth->confBd[txQ];
3237 bd_status = in_be32((u32 __iomem *)bd);
3238
3239
3240 while ((bd_status & T_R) == 0) {
3241 struct sk_buff *skb;
3242
3243
3244
3245
3246
3247 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3248 if (!skb)
3249 break;
3250
3251 dev->stats.tx_packets++;
3252
3253 dev_consume_skb_any(skb);
3254
3255 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3256 ugeth->skb_dirtytx[txQ] =
3257 (ugeth->skb_dirtytx[txQ] +
3258 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3259
3260
3261 if (netif_queue_stopped(dev))
3262 netif_wake_queue(dev);
3263
3264
3265 if (!(bd_status & T_W))
3266 bd += sizeof(struct qe_bd);
3267 else
3268 bd = ugeth->p_tx_bd_ring[txQ];
3269 bd_status = in_be32((u32 __iomem *)bd);
3270 }
3271 ugeth->confBd[txQ] = bd;
3272 return 0;
3273}
3274
3275static int ucc_geth_poll(struct napi_struct *napi, int budget)
3276{
3277 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3278 struct ucc_geth_info *ug_info;
3279 int howmany, i;
3280
3281 ug_info = ugeth->ug_info;
3282
3283
3284 spin_lock(&ugeth->lock);
3285 for (i = 0; i < ug_info->numQueuesTx; i++)
3286 ucc_geth_tx(ugeth->ndev, i);
3287 spin_unlock(&ugeth->lock);
3288
3289 howmany = 0;
3290 for (i = 0; i < ug_info->numQueuesRx; i++)
3291 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3292
3293 if (howmany < budget) {
3294 napi_complete_done(napi, howmany);
3295 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3296 }
3297
3298 return howmany;
3299}
3300
3301static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3302{
3303 struct net_device *dev = info;
3304 struct ucc_geth_private *ugeth = netdev_priv(dev);
3305 struct ucc_fast_private *uccf;
3306 struct ucc_geth_info *ug_info;
3307 register u32 ucce;
3308 register u32 uccm;
3309
3310 ugeth_vdbg("%s: IN", __func__);
3311
3312 uccf = ugeth->uccf;
3313 ug_info = ugeth->ug_info;
3314
3315
3316 ucce = (u32) in_be32(uccf->p_ucce);
3317 uccm = (u32) in_be32(uccf->p_uccm);
3318 ucce &= uccm;
3319 out_be32(uccf->p_ucce, ucce);
3320
3321
3322 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3323 if (napi_schedule_prep(&ugeth->napi)) {
3324 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3325 out_be32(uccf->p_uccm, uccm);
3326 __napi_schedule(&ugeth->napi);
3327 }
3328 }
3329
3330
3331 if (ucce & UCCE_OTHER) {
3332 if (ucce & UCC_GETH_UCCE_BSY)
3333 dev->stats.rx_errors++;
3334 if (ucce & UCC_GETH_UCCE_TXE)
3335 dev->stats.tx_errors++;
3336 }
3337
3338 return IRQ_HANDLED;
3339}
3340
3341#ifdef CONFIG_NET_POLL_CONTROLLER
3342
3343
3344
3345
3346
3347static void ucc_netpoll(struct net_device *dev)
3348{
3349 struct ucc_geth_private *ugeth = netdev_priv(dev);
3350 int irq = ugeth->ug_info->uf_info.irq;
3351
3352 disable_irq(irq);
3353 ucc_geth_irq_handler(irq, dev);
3354 enable_irq(irq);
3355}
3356#endif
3357
3358static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3359{
3360 struct ucc_geth_private *ugeth = netdev_priv(dev);
3361 struct sockaddr *addr = p;
3362
3363 if (!is_valid_ether_addr(addr->sa_data))
3364 return -EADDRNOTAVAIL;
3365
3366 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3367
3368
3369
3370
3371
3372 if (!netif_running(dev))
3373 return 0;
3374
3375 spin_lock_irq(&ugeth->lock);
3376 init_mac_station_addr_regs(dev->dev_addr[0],
3377 dev->dev_addr[1],
3378 dev->dev_addr[2],
3379 dev->dev_addr[3],
3380 dev->dev_addr[4],
3381 dev->dev_addr[5],
3382 &ugeth->ug_regs->macstnaddr1,
3383 &ugeth->ug_regs->macstnaddr2);
3384 spin_unlock_irq(&ugeth->lock);
3385
3386 return 0;
3387}
3388
3389static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3390{
3391 struct net_device *dev = ugeth->ndev;
3392 int err;
3393
3394 err = ucc_struct_init(ugeth);
3395 if (err) {
3396 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3397 goto err;
3398 }
3399
3400 err = ucc_geth_startup(ugeth);
3401 if (err) {
3402 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3403 goto err;
3404 }
3405
3406 err = adjust_enet_interface(ugeth);
3407 if (err) {
3408 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3409 goto err;
3410 }
3411
3412
3413
3414 init_mac_station_addr_regs(dev->dev_addr[0],
3415 dev->dev_addr[1],
3416 dev->dev_addr[2],
3417 dev->dev_addr[3],
3418 dev->dev_addr[4],
3419 dev->dev_addr[5],
3420 &ugeth->ug_regs->macstnaddr1,
3421 &ugeth->ug_regs->macstnaddr2);
3422
3423 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3424 if (err) {
3425 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3426 goto err;
3427 }
3428
3429 return 0;
3430err:
3431 ucc_geth_stop(ugeth);
3432 return err;
3433}
3434
3435
3436
3437static int ucc_geth_open(struct net_device *dev)
3438{
3439 struct ucc_geth_private *ugeth = netdev_priv(dev);
3440 int err;
3441
3442 ugeth_vdbg("%s: IN", __func__);
3443
3444
3445 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3446 netif_err(ugeth, ifup, dev,
3447 "Multicast address used for station address - is this what you wanted?\n");
3448 return -EINVAL;
3449 }
3450
3451 err = init_phy(dev);
3452 if (err) {
3453 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3454 return err;
3455 }
3456
3457 err = ucc_geth_init_mac(ugeth);
3458 if (err) {
3459 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3460 goto err;
3461 }
3462
3463 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3464 0, "UCC Geth", dev);
3465 if (err) {
3466 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3467 goto err;
3468 }
3469
3470 phy_start(ugeth->phydev);
3471 napi_enable(&ugeth->napi);
3472 netif_start_queue(dev);
3473
3474 device_set_wakeup_capable(&dev->dev,
3475 qe_alive_during_sleep() || ugeth->phydev->irq);
3476 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3477
3478 return err;
3479
3480err:
3481 ucc_geth_stop(ugeth);
3482 return err;
3483}
3484
3485
3486static int ucc_geth_close(struct net_device *dev)
3487{
3488 struct ucc_geth_private *ugeth = netdev_priv(dev);
3489
3490 ugeth_vdbg("%s: IN", __func__);
3491
3492 napi_disable(&ugeth->napi);
3493
3494 cancel_work_sync(&ugeth->timeout_work);
3495 ucc_geth_stop(ugeth);
3496 phy_disconnect(ugeth->phydev);
3497 ugeth->phydev = NULL;
3498
3499 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3500
3501 netif_stop_queue(dev);
3502
3503 return 0;
3504}
3505
3506
3507static void ucc_geth_timeout_work(struct work_struct *work)
3508{
3509 struct ucc_geth_private *ugeth;
3510 struct net_device *dev;
3511
3512 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3513 dev = ugeth->ndev;
3514
3515 ugeth_vdbg("%s: IN", __func__);
3516
3517 dev->stats.tx_errors++;
3518
3519 ugeth_dump_regs(ugeth);
3520
3521 if (dev->flags & IFF_UP) {
3522
3523
3524
3525
3526 netif_tx_stop_all_queues(dev);
3527 ucc_geth_stop(ugeth);
3528 ucc_geth_init_mac(ugeth);
3529
3530 phy_start(ugeth->phydev);
3531 netif_tx_start_all_queues(dev);
3532 }
3533
3534 netif_tx_schedule_all(dev);
3535}
3536
3537
3538
3539
3540
3541static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue)
3542{
3543 struct ucc_geth_private *ugeth = netdev_priv(dev);
3544
3545 schedule_work(&ugeth->timeout_work);
3546}
3547
3548
3549#ifdef CONFIG_PM
3550
3551static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3552{
3553 struct net_device *ndev = platform_get_drvdata(ofdev);
3554 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3555
3556 if (!netif_running(ndev))
3557 return 0;
3558
3559 netif_device_detach(ndev);
3560 napi_disable(&ugeth->napi);
3561
3562
3563
3564
3565
3566 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3567
3568 if (ugeth->wol_en & WAKE_MAGIC) {
3569 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3570 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3571 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3572 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3573 phy_stop(ugeth->phydev);
3574 }
3575
3576 return 0;
3577}
3578
3579static int ucc_geth_resume(struct platform_device *ofdev)
3580{
3581 struct net_device *ndev = platform_get_drvdata(ofdev);
3582 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3583 int err;
3584
3585 if (!netif_running(ndev))
3586 return 0;
3587
3588 if (qe_alive_during_sleep()) {
3589 if (ugeth->wol_en & WAKE_MAGIC) {
3590 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3591 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3592 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3593 }
3594 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3595 } else {
3596
3597
3598
3599
3600 ucc_geth_memclean(ugeth);
3601
3602 err = ucc_geth_init_mac(ugeth);
3603 if (err) {
3604 netdev_err(ndev, "Cannot initialize MAC, aborting\n");
3605 return err;
3606 }
3607 }
3608
3609 ugeth->oldlink = 0;
3610 ugeth->oldspeed = 0;
3611 ugeth->oldduplex = -1;
3612
3613 phy_stop(ugeth->phydev);
3614 phy_start(ugeth->phydev);
3615
3616 napi_enable(&ugeth->napi);
3617 netif_device_attach(ndev);
3618
3619 return 0;
3620}
3621
3622#else
3623#define ucc_geth_suspend NULL
3624#define ucc_geth_resume NULL
3625#endif
3626
3627static phy_interface_t to_phy_interface(const char *phy_connection_type)
3628{
3629 if (strcasecmp(phy_connection_type, "mii") == 0)
3630 return PHY_INTERFACE_MODE_MII;
3631 if (strcasecmp(phy_connection_type, "gmii") == 0)
3632 return PHY_INTERFACE_MODE_GMII;
3633 if (strcasecmp(phy_connection_type, "tbi") == 0)
3634 return PHY_INTERFACE_MODE_TBI;
3635 if (strcasecmp(phy_connection_type, "rmii") == 0)
3636 return PHY_INTERFACE_MODE_RMII;
3637 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3638 return PHY_INTERFACE_MODE_RGMII;
3639 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3640 return PHY_INTERFACE_MODE_RGMII_ID;
3641 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3642 return PHY_INTERFACE_MODE_RGMII_TXID;
3643 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3644 return PHY_INTERFACE_MODE_RGMII_RXID;
3645 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3646 return PHY_INTERFACE_MODE_RTBI;
3647 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3648 return PHY_INTERFACE_MODE_SGMII;
3649
3650 return PHY_INTERFACE_MODE_MII;
3651}
3652
3653static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3654{
3655 struct ucc_geth_private *ugeth = netdev_priv(dev);
3656
3657 if (!netif_running(dev))
3658 return -EINVAL;
3659
3660 if (!ugeth->phydev)
3661 return -ENODEV;
3662
3663 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3664}
3665
3666static const struct net_device_ops ucc_geth_netdev_ops = {
3667 .ndo_open = ucc_geth_open,
3668 .ndo_stop = ucc_geth_close,
3669 .ndo_start_xmit = ucc_geth_start_xmit,
3670 .ndo_validate_addr = eth_validate_addr,
3671 .ndo_set_mac_address = ucc_geth_set_mac_addr,
3672 .ndo_set_rx_mode = ucc_geth_set_multi,
3673 .ndo_tx_timeout = ucc_geth_timeout,
3674 .ndo_do_ioctl = ucc_geth_ioctl,
3675#ifdef CONFIG_NET_POLL_CONTROLLER
3676 .ndo_poll_controller = ucc_netpoll,
3677#endif
3678};
3679
3680static int ucc_geth_probe(struct platform_device* ofdev)
3681{
3682 struct device *device = &ofdev->dev;
3683 struct device_node *np = ofdev->dev.of_node;
3684 struct net_device *dev = NULL;
3685 struct ucc_geth_private *ugeth = NULL;
3686 struct ucc_geth_info *ug_info;
3687 struct resource res;
3688 int err, ucc_num, max_speed = 0;
3689 const unsigned int *prop;
3690 const char *sprop;
3691 phy_interface_t phy_interface;
3692 static const int enet_to_speed[] = {
3693 SPEED_10, SPEED_10, SPEED_10,
3694 SPEED_100, SPEED_100, SPEED_100,
3695 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3696 };
3697 static const phy_interface_t enet_to_phy_interface[] = {
3698 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3699 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3700 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3701 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3702 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3703 PHY_INTERFACE_MODE_SGMII,
3704 };
3705
3706 ugeth_vdbg("%s: IN", __func__);
3707
3708 prop = of_get_property(np, "cell-index", NULL);
3709 if (!prop) {
3710 prop = of_get_property(np, "device-id", NULL);
3711 if (!prop)
3712 return -ENODEV;
3713 }
3714
3715 ucc_num = *prop - 1;
3716 if ((ucc_num < 0) || (ucc_num > 7))
3717 return -ENODEV;
3718
3719 ug_info = &ugeth_info[ucc_num];
3720 if (ug_info == NULL) {
3721 if (netif_msg_probe(&debug))
3722 pr_err("[%d] Missing additional data!\n", ucc_num);
3723 return -ENODEV;
3724 }
3725
3726 ug_info->uf_info.ucc_num = ucc_num;
3727
3728 sprop = of_get_property(np, "rx-clock-name", NULL);
3729 if (sprop) {
3730 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3731 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3732 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3733 pr_err("invalid rx-clock-name property\n");
3734 return -EINVAL;
3735 }
3736 } else {
3737 prop = of_get_property(np, "rx-clock", NULL);
3738 if (!prop) {
3739
3740
3741 pr_err("missing rx-clock-name property\n");
3742 return -EINVAL;
3743 }
3744 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3745 pr_err("invalid rx-clock property\n");
3746 return -EINVAL;
3747 }
3748 ug_info->uf_info.rx_clock = *prop;
3749 }
3750
3751 sprop = of_get_property(np, "tx-clock-name", NULL);
3752 if (sprop) {
3753 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3754 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3755 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3756 pr_err("invalid tx-clock-name property\n");
3757 return -EINVAL;
3758 }
3759 } else {
3760 prop = of_get_property(np, "tx-clock", NULL);
3761 if (!prop) {
3762 pr_err("missing tx-clock-name property\n");
3763 return -EINVAL;
3764 }
3765 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3766 pr_err("invalid tx-clock property\n");
3767 return -EINVAL;
3768 }
3769 ug_info->uf_info.tx_clock = *prop;
3770 }
3771
3772 err = of_address_to_resource(np, 0, &res);
3773 if (err)
3774 return -EINVAL;
3775
3776 ug_info->uf_info.regs = res.start;
3777 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3778
3779 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3780 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3781
3782
3783
3784
3785 err = of_phy_register_fixed_link(np);
3786 if (err)
3787 return err;
3788 ug_info->phy_node = of_node_get(np);
3789 }
3790
3791
3792 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3793
3794
3795 prop = of_get_property(np, "phy-connection-type", NULL);
3796 if (!prop) {
3797
3798 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3799 if (prop != NULL) {
3800 phy_interface = enet_to_phy_interface[*prop];
3801 max_speed = enet_to_speed[*prop];
3802 } else
3803 phy_interface = PHY_INTERFACE_MODE_MII;
3804 } else {
3805 phy_interface = to_phy_interface((const char *)prop);
3806 }
3807
3808
3809 if (max_speed == 0)
3810 switch (phy_interface) {
3811 case PHY_INTERFACE_MODE_GMII:
3812 case PHY_INTERFACE_MODE_RGMII:
3813 case PHY_INTERFACE_MODE_RGMII_ID:
3814 case PHY_INTERFACE_MODE_RGMII_RXID:
3815 case PHY_INTERFACE_MODE_RGMII_TXID:
3816 case PHY_INTERFACE_MODE_TBI:
3817 case PHY_INTERFACE_MODE_RTBI:
3818 case PHY_INTERFACE_MODE_SGMII:
3819 max_speed = SPEED_1000;
3820 break;
3821 default:
3822 max_speed = SPEED_100;
3823 break;
3824 }
3825
3826 if (max_speed == SPEED_1000) {
3827 unsigned int snums = qe_get_num_of_snums();
3828
3829
3830 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3831 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3832 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3833 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3834 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3835 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3836 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3837
3838
3839
3840
3841
3842 if ((snums == 76) || (snums == 46))
3843 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3844 else
3845 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3846 }
3847
3848 if (netif_msg_probe(&debug))
3849 pr_info("UCC%1d at 0x%8llx (irq = %d)\n",
3850 ug_info->uf_info.ucc_num + 1,
3851 (u64)ug_info->uf_info.regs,
3852 ug_info->uf_info.irq);
3853
3854
3855 dev = alloc_etherdev(sizeof(*ugeth));
3856
3857 if (dev == NULL) {
3858 err = -ENOMEM;
3859 goto err_deregister_fixed_link;
3860 }
3861
3862 ugeth = netdev_priv(dev);
3863 spin_lock_init(&ugeth->lock);
3864
3865
3866 INIT_LIST_HEAD(&ugeth->group_hash_q);
3867 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3868
3869 dev_set_drvdata(device, dev);
3870
3871
3872 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3873
3874 SET_NETDEV_DEV(dev, device);
3875
3876
3877 uec_set_ethtool_ops(dev);
3878 dev->netdev_ops = &ucc_geth_netdev_ops;
3879 dev->watchdog_timeo = TX_TIMEOUT;
3880 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3881 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3882 dev->mtu = 1500;
3883
3884 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3885 ugeth->phy_interface = phy_interface;
3886 ugeth->max_speed = max_speed;
3887
3888
3889 netif_carrier_off(dev);
3890
3891 err = register_netdev(dev);
3892 if (err) {
3893 if (netif_msg_probe(ugeth))
3894 pr_err("%s: Cannot register net device, aborting\n",
3895 dev->name);
3896 goto err_free_netdev;
3897 }
3898
3899 of_get_mac_address(np, dev->dev_addr);
3900
3901 ugeth->ug_info = ug_info;
3902 ugeth->dev = device;
3903 ugeth->ndev = dev;
3904 ugeth->node = np;
3905
3906 return 0;
3907
3908err_free_netdev:
3909 free_netdev(dev);
3910err_deregister_fixed_link:
3911 if (of_phy_is_fixed_link(np))
3912 of_phy_deregister_fixed_link(np);
3913 of_node_put(ug_info->tbi_node);
3914 of_node_put(ug_info->phy_node);
3915
3916 return err;
3917}
3918
3919static int ucc_geth_remove(struct platform_device* ofdev)
3920{
3921 struct net_device *dev = platform_get_drvdata(ofdev);
3922 struct ucc_geth_private *ugeth = netdev_priv(dev);
3923 struct device_node *np = ofdev->dev.of_node;
3924
3925 unregister_netdev(dev);
3926 free_netdev(dev);
3927 ucc_geth_memclean(ugeth);
3928 if (of_phy_is_fixed_link(np))
3929 of_phy_deregister_fixed_link(np);
3930 of_node_put(ugeth->ug_info->tbi_node);
3931 of_node_put(ugeth->ug_info->phy_node);
3932
3933 return 0;
3934}
3935
3936static const struct of_device_id ucc_geth_match[] = {
3937 {
3938 .type = "network",
3939 .compatible = "ucc_geth",
3940 },
3941 {},
3942};
3943
3944MODULE_DEVICE_TABLE(of, ucc_geth_match);
3945
3946static struct platform_driver ucc_geth_driver = {
3947 .driver = {
3948 .name = DRV_NAME,
3949 .of_match_table = ucc_geth_match,
3950 },
3951 .probe = ucc_geth_probe,
3952 .remove = ucc_geth_remove,
3953 .suspend = ucc_geth_suspend,
3954 .resume = ucc_geth_resume,
3955};
3956
3957static int __init ucc_geth_init(void)
3958{
3959 int i, ret;
3960
3961 if (netif_msg_drv(&debug))
3962 pr_info(DRV_DESC "\n");
3963 for (i = 0; i < 8; i++)
3964 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3965 sizeof(ugeth_primary_info));
3966
3967 ret = platform_driver_register(&ucc_geth_driver);
3968
3969 return ret;
3970}
3971
3972static void __exit ucc_geth_exit(void)
3973{
3974 platform_driver_unregister(&ucc_geth_driver);
3975}
3976
3977module_init(ucc_geth_init);
3978module_exit(ucc_geth_exit);
3979
3980MODULE_AUTHOR("Freescale Semiconductor, Inc");
3981MODULE_DESCRIPTION(DRV_DESC);
3982MODULE_VERSION(DRV_VERSION);
3983MODULE_LICENSE("GPL");
3984
