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10#ifndef __HNS3_ENET_H
11#define __HNS3_ENET_H
12
13#include <linux/if_vlan.h>
14
15#include "hnae3.h"
16
17#define HNS3_MOD_VERSION "1.0"
18
19extern const char hns3_driver_version[];
20
21enum hns3_nic_state {
22 HNS3_NIC_STATE_TESTING,
23 HNS3_NIC_STATE_RESETTING,
24 HNS3_NIC_STATE_REINITING,
25 HNS3_NIC_STATE_DOWN,
26 HNS3_NIC_STATE_DISABLED,
27 HNS3_NIC_STATE_REMOVING,
28 HNS3_NIC_STATE_SERVICE_INITED,
29 HNS3_NIC_STATE_SERVICE_SCHED,
30 HNS3_NIC_STATE2_RESET_REQUESTED,
31 HNS3_NIC_STATE_MAX
32};
33
34#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
35#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
36#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
37#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
38#define HNS3_RING_RX_RING_TAIL_REG 0x00018
39#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
40#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
41#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
42
43#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
44#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
45#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
46#define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C
47#define HNS3_RING_TX_RING_TC_REG 0x00050
48#define HNS3_RING_TX_RING_TAIL_REG 0x00058
49#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
50#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
51#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
52#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
53
54#define HNS3_RING_PREFETCH_EN_REG 0x0007C
55#define HNS3_RING_CFG_VF_NUM_REG 0x00080
56#define HNS3_RING_ASID_REG 0x0008C
57#define HNS3_RING_RX_VM_REG 0x00090
58#define HNS3_RING_T0_BE_RST 0x00094
59#define HNS3_RING_COULD_BE_RST 0x00098
60#define HNS3_RING_WRR_WEIGHT_REG 0x0009c
61
62#define HNS3_RING_INTMSK_RXWL_REG 0x000A0
63#define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
64#define HNS3_RX_RING_INT_STS_REG 0x000A8
65#define HNS3_RING_INTMSK_TXWL_REG 0x000AC
66#define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
67#define HNS3_TX_RING_INT_STS_REG 0x000B4
68#define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
69#define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
70#define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
71#define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
72
73#define HNS3_RING_MB_CTRL_REG 0x00100
74#define HNS3_RING_MB_DATA_BASE_REG 0x00200
75
76#define HNS3_TX_REG_OFFSET 0x40
77
78#define HNS3_RX_HEAD_SIZE 256
79
80#define HNS3_TX_TIMEOUT (5 * HZ)
81#define HNS3_RING_NAME_LEN 16
82#define HNS3_BUFFER_SIZE_2048 2048
83#define HNS3_RING_MAX_PENDING 32768
84#define HNS3_RING_MIN_PENDING 8
85#define HNS3_RING_BD_MULTIPLE 8
86#define HNS3_MAX_MTU 9728
87
88#define HNS3_BD_SIZE_512_TYPE 0
89#define HNS3_BD_SIZE_1024_TYPE 1
90#define HNS3_BD_SIZE_2048_TYPE 2
91#define HNS3_BD_SIZE_4096_TYPE 3
92
93#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
94#define HNS3_RX_FLAG_L3ID_IPV4 0x0
95#define HNS3_RX_FLAG_L3ID_IPV6 0x1
96#define HNS3_RX_FLAG_L4ID_UDP 0x0
97#define HNS3_RX_FLAG_L4ID_TCP 0x1
98
99#define HNS3_RXD_DMAC_S 0
100#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
101#define HNS3_RXD_VLAN_S 2
102#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
103#define HNS3_RXD_L3ID_S 4
104#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
105#define HNS3_RXD_L4ID_S 8
106#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
107#define HNS3_RXD_FRAG_B 12
108#define HNS3_RXD_STRP_TAGP_S 13
109#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
110
111#define HNS3_RXD_L2E_B 16
112#define HNS3_RXD_L3E_B 17
113#define HNS3_RXD_L4E_B 18
114#define HNS3_RXD_TRUNCAT_B 19
115#define HNS3_RXD_HOI_B 20
116#define HNS3_RXD_DOI_B 21
117#define HNS3_RXD_OL3E_B 22
118#define HNS3_RXD_OL4E_B 23
119
120#define HNS3_RXD_ODMAC_S 0
121#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
122#define HNS3_RXD_OVLAN_S 2
123#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
124#define HNS3_RXD_OL3ID_S 4
125#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
126#define HNS3_RXD_OL4ID_S 8
127#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
128#define HNS3_RXD_FBHI_S 12
129#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
130#define HNS3_RXD_FBLI_S 14
131#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
132
133#define HNS3_RXD_BDTYPE_S 0
134#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
135#define HNS3_RXD_VLD_B 4
136#define HNS3_RXD_UDP0_B 5
137#define HNS3_RXD_EXTEND_B 7
138#define HNS3_RXD_FE_B 8
139#define HNS3_RXD_LUM_B 9
140#define HNS3_RXD_CRCP_B 10
141#define HNS3_RXD_L3L4P_B 11
142#define HNS3_RXD_TSIND_S 12
143#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
144#define HNS3_RXD_LKBK_B 15
145#define HNS3_RXD_HDL_S 16
146#define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S)
147#define HNS3_RXD_HSIND_B 31
148
149#define HNS3_TXD_L3T_S 0
150#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
151#define HNS3_TXD_L4T_S 2
152#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
153#define HNS3_TXD_L3CS_B 4
154#define HNS3_TXD_L4CS_B 5
155#define HNS3_TXD_VLAN_B 6
156#define HNS3_TXD_TSO_B 7
157
158#define HNS3_TXD_L2LEN_S 8
159#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
160#define HNS3_TXD_L3LEN_S 16
161#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
162#define HNS3_TXD_L4LEN_S 24
163#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
164
165#define HNS3_TXD_OL3T_S 0
166#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
167#define HNS3_TXD_OVLAN_B 2
168#define HNS3_TXD_MACSEC_B 3
169#define HNS3_TXD_TUNTYPE_S 4
170#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
171
172#define HNS3_TXD_BDTYPE_S 0
173#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
174#define HNS3_TXD_FE_B 4
175#define HNS3_TXD_SC_S 5
176#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
177#define HNS3_TXD_EXTEND_B 7
178#define HNS3_TXD_VLD_B 8
179#define HNS3_TXD_RI_B 9
180#define HNS3_TXD_RA_B 10
181#define HNS3_TXD_TSYN_B 11
182#define HNS3_TXD_DECTTL_S 12
183#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
184
185#define HNS3_TXD_MSS_S 0
186#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
187
188#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
189#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
190
191#define HNS3_VECTOR_NOT_INITED 0
192#define HNS3_VECTOR_INITED 1
193
194#define HNS3_MAX_BD_SIZE 65535
195#define HNS3_MAX_BD_PER_FRAG 8
196#define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
197
198#define HNS3_VECTOR_GL0_OFFSET 0x100
199#define HNS3_VECTOR_GL1_OFFSET 0x200
200#define HNS3_VECTOR_GL2_OFFSET 0x300
201#define HNS3_VECTOR_RL_OFFSET 0x900
202#define HNS3_VECTOR_RL_EN_B 6
203
204enum hns3_pkt_l3t_type {
205 HNS3_L3T_NONE,
206 HNS3_L3T_IPV6,
207 HNS3_L3T_IPV4,
208 HNS3_L3T_RESERVED
209};
210
211enum hns3_pkt_l4t_type {
212 HNS3_L4T_UNKNOWN,
213 HNS3_L4T_TCP,
214 HNS3_L4T_UDP,
215 HNS3_L4T_SCTP
216};
217
218enum hns3_pkt_ol3t_type {
219 HNS3_OL3T_NONE,
220 HNS3_OL3T_IPV6,
221 HNS3_OL3T_IPV4_NO_CSUM,
222 HNS3_OL3T_IPV4_CSUM
223};
224
225enum hns3_pkt_tun_type {
226 HNS3_TUN_NONE,
227 HNS3_TUN_MAC_IN_UDP,
228 HNS3_TUN_NVGRE,
229 HNS3_TUN_OTHER
230};
231
232
233struct __packed hns3_desc {
234 __le64 addr;
235 union {
236 struct {
237 __le16 vlan_tag;
238 __le16 send_size;
239 union {
240 __le32 type_cs_vlan_tso_len;
241 struct {
242 __u8 type_cs_vlan_tso;
243 __u8 l2_len;
244 __u8 l3_len;
245 __u8 l4_len;
246 };
247 };
248 __le16 outer_vlan_tag;
249 __le16 tv;
250
251 union {
252 __le32 ol_type_vlan_len_msec;
253 struct {
254 __u8 ol_type_vlan_msec;
255 __u8 ol2_len;
256 __u8 ol3_len;
257 __u8 ol4_len;
258 };
259 };
260
261 __le32 paylen;
262 __le16 bdtp_fe_sc_vld_ra_ri;
263 __le16 mss;
264 } tx;
265
266 struct {
267 __le32 l234_info;
268 __le16 pkt_len;
269 __le16 size;
270
271 __le32 rss_hash;
272 __le16 fd_id;
273 __le16 vlan_tag;
274
275 union {
276 __le32 ol_info;
277 struct {
278 __le16 o_dm_vlan_id_fb;
279 __le16 ot_vlan_tag;
280 };
281 };
282
283 __le32 bd_base_info;
284 } rx;
285 };
286};
287
288struct hns3_desc_cb {
289 dma_addr_t dma;
290 void *buf;
291
292
293 void *priv;
294 u32 page_offset;
295 u32 length;
296
297 u16 reuse_flag;
298
299
300 u16 type;
301};
302
303enum hns3_pkt_l3type {
304 HNS3_L3_TYPE_IPV4,
305 HNS3_L3_TYPE_IPV6,
306 HNS3_L3_TYPE_ARP,
307 HNS3_L3_TYPE_RARP,
308 HNS3_L3_TYPE_IPV4_OPT,
309 HNS3_L3_TYPE_IPV6_EXT,
310 HNS3_L3_TYPE_LLDP,
311 HNS3_L3_TYPE_BPDU,
312 HNS3_L3_TYPE_MAC_PAUSE,
313 HNS3_L3_TYPE_PFC_PAUSE,
314
315
316
317 HNS3_L3_TYPE_CNM = 0xc,
318
319
320
321 HNS3_L3_TYPE_PARSE_FAIL = 0xf
322};
323
324enum hns3_pkt_l4type {
325 HNS3_L4_TYPE_UDP,
326 HNS3_L4_TYPE_TCP,
327 HNS3_L4_TYPE_GRE,
328 HNS3_L4_TYPE_SCTP,
329 HNS3_L4_TYPE_IGMP,
330 HNS3_L4_TYPE_ICMP,
331
332
333
334 HNS3_L4_TYPE_PARSE_FAIL = 0xf
335};
336
337enum hns3_pkt_ol3type {
338 HNS3_OL3_TYPE_IPV4 = 0,
339 HNS3_OL3_TYPE_IPV6,
340
341 HNS3_OL3_TYPE_IPV4_OPT = 4,
342 HNS3_OL3_TYPE_IPV6_EXT,
343
344
345
346 HNS3_OL3_TYPE_PARSE_FAIL = 0xf
347};
348
349enum hns3_pkt_ol4type {
350 HNS3_OL4_TYPE_NO_TUN,
351 HNS3_OL4_TYPE_MAC_IN_UDP,
352 HNS3_OL4_TYPE_NVGRE,
353 HNS3_OL4_TYPE_UNKNOWN
354};
355
356struct ring_stats {
357 u64 io_err_cnt;
358 u64 sw_err_cnt;
359 u64 seg_pkt_cnt;
360 union {
361 struct {
362 u64 tx_pkts;
363 u64 tx_bytes;
364 u64 tx_err_cnt;
365 u64 restart_queue;
366 u64 tx_busy;
367 };
368 struct {
369 u64 rx_pkts;
370 u64 rx_bytes;
371 u64 rx_err_cnt;
372 u64 reuse_pg_cnt;
373 u64 err_pkt_len;
374 u64 non_vld_descs;
375 u64 err_bd_num;
376 u64 l2_err;
377 u64 l3l4_csum_err;
378 };
379 };
380};
381
382struct hns3_enet_ring {
383 u8 __iomem *io_base;
384 struct hns3_desc *desc;
385 struct hns3_desc_cb *desc_cb;
386 struct hns3_enet_ring *next;
387 struct hns3_enet_tqp_vector *tqp_vector;
388 struct hnae3_queue *tqp;
389 char ring_name[HNS3_RING_NAME_LEN];
390 struct device *dev;
391
392
393 struct ring_stats stats;
394 struct u64_stats_sync syncp;
395
396 dma_addr_t desc_dma_addr;
397 u32 buf_size;
398 u16 desc_num;
399 u16 max_desc_num_per_pkt;
400 u16 max_raw_data_sz_per_desc;
401 u16 max_pkt_size;
402 int next_to_use;
403
404
405
406
407 int next_to_clean;
408
409 u32 flag;
410 int irq_init_flag;
411
412 int numa_node;
413 cpumask_t affinity_mask;
414};
415
416struct hns_queue;
417
418struct hns3_nic_ring_data {
419 struct hns3_enet_ring *ring;
420 struct napi_struct napi;
421 int queue_index;
422 int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
423 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
424 void (*fini_process)(struct hns3_nic_ring_data *);
425};
426
427struct hns3_nic_ops {
428 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
429 int size, int frag_end, enum hns_desc_type type);
430 int (*maybe_stop_tx)(struct sk_buff **out_skb,
431 int *bnum, struct hns3_enet_ring *ring);
432 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
433};
434
435enum hns3_flow_level_range {
436 HNS3_FLOW_LOW = 0,
437 HNS3_FLOW_MID = 1,
438 HNS3_FLOW_HIGH = 2,
439 HNS3_FLOW_ULTRA = 3,
440};
441
442enum hns3_link_mode_bits {
443 HNS3_LM_FIBRE_BIT = BIT(0),
444 HNS3_LM_AUTONEG_BIT = BIT(1),
445 HNS3_LM_TP_BIT = BIT(2),
446 HNS3_LM_PAUSE_BIT = BIT(3),
447 HNS3_LM_BACKPLANE_BIT = BIT(4),
448 HNS3_LM_10BASET_HALF_BIT = BIT(5),
449 HNS3_LM_10BASET_FULL_BIT = BIT(6),
450 HNS3_LM_100BASET_HALF_BIT = BIT(7),
451 HNS3_LM_100BASET_FULL_BIT = BIT(8),
452 HNS3_LM_1000BASET_FULL_BIT = BIT(9),
453 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
454 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
455 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
456 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
457 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
458 HNS3_LM_COUNT = 15
459};
460
461#define HNS3_INT_GL_MAX 0x1FE0
462#define HNS3_INT_GL_50K 0x0014
463#define HNS3_INT_GL_20K 0x0032
464#define HNS3_INT_GL_18K 0x0036
465#define HNS3_INT_GL_8K 0x007C
466
467#define HNS3_INT_RL_MAX 0x00EC
468#define HNS3_INT_RL_ENABLE_MASK 0x40
469
470#define HNS3_INT_ADAPT_DOWN_START 100
471
472struct hns3_enet_coalesce {
473 u16 int_gl;
474 u8 gl_adapt_enable;
475 enum hns3_flow_level_range flow_level;
476};
477
478struct hns3_enet_ring_group {
479
480 struct hns3_enet_ring *ring;
481 u64 total_bytes;
482 u64 total_packets;
483 u16 count;
484 struct hns3_enet_coalesce coal;
485};
486
487struct hns3_enet_tqp_vector {
488 struct hnae3_handle *handle;
489 u8 __iomem *mask_addr;
490 int vector_irq;
491 int irq_init_flag;
492
493 u16 idx;
494
495 struct napi_struct napi;
496
497 struct hns3_enet_ring_group rx_group;
498 struct hns3_enet_ring_group tx_group;
499
500 u16 num_tqps;
501
502 cpumask_t affinity_mask;
503 char name[HNAE3_INT_NAME_LEN];
504
505
506 u8 int_adapt_down;
507 unsigned long last_jiffies;
508} ____cacheline_internodealigned_in_smp;
509
510enum hns3_udp_tnl_type {
511 HNS3_UDP_TNL_VXLAN,
512 HNS3_UDP_TNL_GENEVE,
513 HNS3_UDP_TNL_MAX,
514};
515
516struct hns3_udp_tunnel {
517 u16 dst_port;
518 int used;
519};
520
521struct hns3_nic_priv {
522 struct hnae3_handle *ae_handle;
523 u32 enet_ver;
524 u32 port_id;
525 struct net_device *netdev;
526 struct device *dev;
527 struct hns3_nic_ops ops;
528
529
530
531
532
533 struct hns3_nic_ring_data *ring_data;
534 struct hns3_enet_tqp_vector *tqp_vector;
535 u16 vector_num;
536
537
538 int link;
539 u64 tx_timeout_count;
540
541 unsigned long state;
542
543 struct timer_list service_timer;
544
545 struct work_struct service_task;
546
547 struct notifier_block notifier_block;
548
549 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
550 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
551 struct hns3_enet_coalesce tx_coal;
552 struct hns3_enet_coalesce rx_coal;
553};
554
555union l3_hdr_info {
556 struct iphdr *v4;
557 struct ipv6hdr *v6;
558 unsigned char *hdr;
559};
560
561union l4_hdr_info {
562 struct tcphdr *tcp;
563 struct udphdr *udp;
564 unsigned char *hdr;
565};
566
567
568
569
570static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
571{
572 return (end - begin + ring->desc_num) % ring->desc_num;
573}
574
575static inline int ring_space(struct hns3_enet_ring *ring)
576{
577 return ring->desc_num -
578 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
579}
580
581static inline int is_ring_empty(struct hns3_enet_ring *ring)
582{
583 return ring->next_to_use == ring->next_to_clean;
584}
585
586static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
587{
588 u8 __iomem *reg_addr = READ_ONCE(base);
589
590 writel(value, reg_addr + reg);
591}
592
593#define hns3_write_dev(a, reg, value) \
594 hns3_write_reg((a)->io_base, (reg), (value))
595
596#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
597 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
598
599#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
600
601#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
602 DMA_TO_DEVICE : DMA_FROM_DEVICE)
603
604#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
605
606#define hnae3_buf_size(_ring) ((_ring)->buf_size)
607#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
608#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
609
610
611#define hns3_for_each_ring(pos, head) \
612 for (pos = (head).ring; pos; pos = pos->next)
613
614#define hns3_get_handle(ndev) \
615 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
616
617#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
618#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
619
620#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
621#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
622
623void hns3_ethtool_set_ops(struct net_device *netdev);
624int hns3_set_channels(struct net_device *netdev,
625 struct ethtool_channels *ch);
626
627void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
628int hns3_init_all_ring(struct hns3_nic_priv *priv);
629int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
630int hns3_nic_reset_all_ring(struct hnae3_handle *h);
631netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
632int hns3_clean_rx_ring(
633 struct hns3_enet_ring *ring, int budget,
634 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
635
636void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
637 u32 gl_value);
638void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
639 u32 gl_value);
640void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
641 u32 rl_value);
642
643void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
644void hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
645
646#ifdef CONFIG_HNS3_DCB
647void hns3_dcbnl_setup(struct hnae3_handle *handle);
648#else
649static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
650#endif
651
652#endif
653