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2
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4#ifndef __HCLGEVF_CMD_H
5#define __HCLGEVF_CMD_H
6#include <linux/io.h>
7#include <linux/types.h>
8#include "hnae3.h"
9
10#define HCLGEVF_CMDQ_TX_TIMEOUT 30000
11#define HCLGEVF_CMDQ_RX_INVLD_B 0
12#define HCLGEVF_CMDQ_RX_OUTVLD_B 1
13
14struct hclgevf_hw;
15struct hclgevf_dev;
16
17struct hclgevf_desc {
18 __le16 opcode;
19 __le16 flag;
20 __le16 retval;
21 __le16 rsv;
22 __le32 data[6];
23};
24
25struct hclgevf_desc_cb {
26 dma_addr_t dma;
27 void *va;
28 u32 length;
29};
30
31struct hclgevf_cmq_ring {
32 dma_addr_t desc_dma_addr;
33 struct hclgevf_desc *desc;
34 struct hclgevf_desc_cb *desc_cb;
35 struct hclgevf_dev *dev;
36 u32 head;
37 u32 tail;
38
39 u16 buf_size;
40 u16 desc_num;
41 int next_to_use;
42 int next_to_clean;
43 u8 flag;
44 spinlock_t lock;
45};
46
47enum hclgevf_cmd_return_status {
48 HCLGEVF_CMD_EXEC_SUCCESS = 0,
49 HCLGEVF_CMD_NO_AUTH = 1,
50 HCLGEVF_CMD_NOT_EXEC = 2,
51 HCLGEVF_CMD_QUEUE_FULL = 3,
52};
53
54enum hclgevf_cmd_status {
55 HCLGEVF_STATUS_SUCCESS = 0,
56 HCLGEVF_ERR_CSQ_FULL = -1,
57 HCLGEVF_ERR_CSQ_TIMEOUT = -2,
58 HCLGEVF_ERR_CSQ_ERROR = -3
59};
60
61struct hclgevf_cmq {
62 struct hclgevf_cmq_ring csq;
63 struct hclgevf_cmq_ring crq;
64 u16 tx_timeout;
65 enum hclgevf_cmd_status last_status;
66};
67
68#define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0
69#define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1
70#define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2
71#define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3
72#define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4
73#define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5
74
75#define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
76#define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
77#define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
78#define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
79#define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
80#define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
81
82enum hclgevf_opcode_type {
83
84 HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
85 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
86
87 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
88 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
89 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
90
91 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
92 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07,
93 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
94
95 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
96};
97
98#define HCLGEVF_TQP_REG_OFFSET 0x80000
99#define HCLGEVF_TQP_REG_SIZE 0x200
100
101struct hclgevf_tqp_map {
102 __le16 tqp_id;
103 u8 tqp_vf;
104#define HCLGEVF_TQP_MAP_TYPE_PF 0
105#define HCLGEVF_TQP_MAP_TYPE_VF 1
106#define HCLGEVF_TQP_MAP_TYPE_B 0
107#define HCLGEVF_TQP_MAP_EN_B 1
108 u8 tqp_flag;
109 __le16 tqp_vid;
110 u8 rsv[18];
111};
112
113#define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
114
115enum hclgevf_int_type {
116 HCLGEVF_INT_TX = 0,
117 HCLGEVF_INT_RX,
118 HCLGEVF_INT_EVENT,
119};
120
121struct hclgevf_ctrl_vector_chain {
122 u8 int_vector_id;
123 u8 int_cause_num;
124#define HCLGEVF_INT_TYPE_S 0
125#define HCLGEVF_INT_TYPE_M 0x3
126#define HCLGEVF_TQP_ID_S 2
127#define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S)
128 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
129 u8 vfid;
130 u8 resv;
131};
132
133struct hclgevf_query_version_cmd {
134 __le32 firmware;
135 __le32 firmware_rsv[5];
136};
137
138#define HCLGEVF_MSIX_OFT_ROCEE_S 0
139#define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
140#define HCLGEVF_VEC_NUM_S 0
141#define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
142struct hclgevf_query_res_cmd {
143 __le16 tqp_num;
144 __le16 reserved;
145 __le16 msixcap_localid_ba_nic;
146 __le16 msixcap_localid_ba_rocee;
147 __le16 vf_intr_vector_number;
148 __le16 rsv[7];
149};
150
151#define HCLGEVF_RSS_HASH_KEY_OFFSET 4
152#define HCLGEVF_RSS_HASH_KEY_NUM 16
153struct hclgevf_rss_config_cmd {
154 u8 hash_config;
155 u8 rsv[7];
156 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
157};
158
159struct hclgevf_rss_input_tuple_cmd {
160 u8 ipv4_tcp_en;
161 u8 ipv4_udp_en;
162 u8 ipv4_stcp_en;
163 u8 ipv4_fragment_en;
164 u8 ipv6_tcp_en;
165 u8 ipv6_udp_en;
166 u8 ipv6_stcp_en;
167 u8 ipv6_fragment_en;
168 u8 rsv[16];
169};
170
171#define HCLGEVF_RSS_CFG_TBL_SIZE 16
172
173struct hclgevf_rss_indirection_table_cmd {
174 u16 start_table_index;
175 u16 rss_set_bitmap;
176 u8 rsv[4];
177 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
178};
179
180#define HCLGEVF_RSS_TC_OFFSET_S 0
181#define HCLGEVF_RSS_TC_OFFSET_M (0x3ff << HCLGEVF_RSS_TC_OFFSET_S)
182#define HCLGEVF_RSS_TC_SIZE_S 12
183#define HCLGEVF_RSS_TC_SIZE_M (0x7 << HCLGEVF_RSS_TC_SIZE_S)
184#define HCLGEVF_RSS_TC_VALID_B 15
185#define HCLGEVF_MAX_TC_NUM 8
186struct hclgevf_rss_tc_mode_cmd {
187 u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
188 u8 rsv[8];
189};
190
191#define HCLGEVF_LINK_STS_B 0
192#define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
193struct hclgevf_link_status_cmd {
194 u8 status;
195 u8 rsv[23];
196};
197
198#define HCLGEVF_RING_ID_MASK 0x3ff
199#define HCLGEVF_TQP_ENABLE_B 0
200
201struct hclgevf_cfg_com_tqp_queue_cmd {
202 __le16 tqp_id;
203 __le16 stream_id;
204 u8 enable;
205 u8 rsv[19];
206};
207
208struct hclgevf_cfg_tx_queue_pointer_cmd {
209 __le16 tqp_id;
210 __le16 tx_tail;
211 __le16 tx_head;
212 __le16 fbd_num;
213 __le16 ring_offset;
214 u8 rsv[14];
215};
216
217#define HCLGEVF_TYPE_CRQ 0
218#define HCLGEVF_TYPE_CSQ 1
219#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
220#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
221#define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
222#define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
223#define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
224#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
225#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c
226#define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
227#define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
228#define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
229#define HCLGEVF_NIC_CMQ_EN_B 16
230#define HCLGEVF_NIC_CMQ_ENABLE BIT(HCLGEVF_NIC_CMQ_EN_B)
231#define HCLGEVF_NIC_CMQ_DESC_NUM 1024
232#define HCLGEVF_NIC_CMQ_DESC_NUM_S 3
233#define HCLGEVF_NIC_CMDQ_INT_SRC_REG 0x27100
234
235static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
236{
237 writel(value, base + reg);
238}
239
240static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
241{
242 u8 __iomem *reg_addr = READ_ONCE(base);
243
244 return readl(reg_addr + reg);
245}
246
247#define hclgevf_write_dev(a, reg, value) \
248 hclgevf_write_reg((a)->io_base, (reg), (value))
249#define hclgevf_read_dev(a, reg) \
250 hclgevf_read_reg((a)->io_base, (reg))
251
252#define HCLGEVF_SEND_SYNC(flag) \
253 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
254
255int hclgevf_cmd_init(struct hclgevf_dev *hdev);
256void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
257
258int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
259void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
260 enum hclgevf_opcode_type opcode,
261 bool is_read);
262#endif
263
