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14#include <linux/stmmac.h>
15#include "common.h"
16#include "dwmac4.h"
17#include "dwmac4_descs.h"
18
19static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
20 struct dma_desc *p,
21 void __iomem *ioaddr)
22{
23 struct net_device_stats *stats = (struct net_device_stats *)data;
24 unsigned int tdes3;
25 int ret = tx_done;
26
27 tdes3 = le32_to_cpu(p->des3);
28
29
30 if (unlikely(tdes3 & TDES3_OWN))
31 return tx_dma_own;
32
33
34 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
35 return tx_not_ls;
36
37 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
38 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
39 x->tx_jabber++;
40 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
41 x->tx_frame_flushed++;
42 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
43 x->tx_losscarrier++;
44 stats->tx_carrier_errors++;
45 }
46 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
47 x->tx_carrier++;
48 stats->tx_carrier_errors++;
49 }
50 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
51 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
52 stats->collisions +=
53 (tdes3 & TDES3_COLLISION_COUNT_MASK)
54 >> TDES3_COLLISION_COUNT_SHIFT;
55
56 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
57 x->tx_deferred++;
58
59 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
60 x->tx_underflow++;
61
62 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
63 x->tx_ip_header_error++;
64
65 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
66 x->tx_payload_error++;
67
68 ret = tx_err;
69 }
70
71 if (unlikely(tdes3 & TDES3_DEFERRED))
72 x->tx_deferred++;
73
74 return ret;
75}
76
77static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
78 struct dma_desc *p)
79{
80 struct net_device_stats *stats = (struct net_device_stats *)data;
81 unsigned int rdes1 = le32_to_cpu(p->des1);
82 unsigned int rdes2 = le32_to_cpu(p->des2);
83 unsigned int rdes3 = le32_to_cpu(p->des3);
84 int message_type;
85 int ret = good_frame;
86
87 if (unlikely(rdes3 & RDES3_OWN))
88 return dma_own;
89
90 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
91 return discard_frame;
92 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
93 return rx_not_ls;
94
95 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
96 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
97 stats->rx_length_errors++;
98 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
99 x->rx_gmac_overflow++;
100
101 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
102 x->rx_watchdog++;
103
104 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
105 x->rx_mii++;
106
107 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
108 x->rx_crc_errors++;
109 stats->rx_crc_errors++;
110 }
111
112 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
113 x->dribbling_bit++;
114
115 ret = discard_frame;
116 }
117
118 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
119
120 if (rdes1 & RDES1_IP_HDR_ERROR)
121 x->ip_hdr_err++;
122 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
123 x->ip_csum_bypassed++;
124 if (rdes1 & RDES1_IPV4_HEADER)
125 x->ipv4_pkt_rcvd++;
126 if (rdes1 & RDES1_IPV6_HEADER)
127 x->ipv6_pkt_rcvd++;
128
129 if (message_type == RDES_EXT_NO_PTP)
130 x->no_ptp_rx_msg_type_ext++;
131 else if (message_type == RDES_EXT_SYNC)
132 x->ptp_rx_msg_type_sync++;
133 else if (message_type == RDES_EXT_FOLLOW_UP)
134 x->ptp_rx_msg_type_follow_up++;
135 else if (message_type == RDES_EXT_DELAY_REQ)
136 x->ptp_rx_msg_type_delay_req++;
137 else if (message_type == RDES_EXT_DELAY_RESP)
138 x->ptp_rx_msg_type_delay_resp++;
139 else if (message_type == RDES_EXT_PDELAY_REQ)
140 x->ptp_rx_msg_type_pdelay_req++;
141 else if (message_type == RDES_EXT_PDELAY_RESP)
142 x->ptp_rx_msg_type_pdelay_resp++;
143 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
144 x->ptp_rx_msg_type_pdelay_follow_up++;
145 else if (message_type == RDES_PTP_ANNOUNCE)
146 x->ptp_rx_msg_type_announce++;
147 else if (message_type == RDES_PTP_MANAGEMENT)
148 x->ptp_rx_msg_type_management++;
149 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
150 x->ptp_rx_msg_pkt_reserved_type++;
151
152 if (rdes1 & RDES1_PTP_PACKET_TYPE)
153 x->ptp_frame_type++;
154 if (rdes1 & RDES1_PTP_VER)
155 x->ptp_ver++;
156 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
157 x->timestamp_dropped++;
158
159 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
160 x->sa_rx_filter_fail++;
161 ret = discard_frame;
162 }
163 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
164 x->da_rx_filter_fail++;
165 ret = discard_frame;
166 }
167
168 if (rdes2 & RDES2_L3_FILTER_MATCH)
169 x->l3_filter_match++;
170 if (rdes2 & RDES2_L4_FILTER_MATCH)
171 x->l4_filter_match++;
172 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
173 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
174 x->l3_l4_filter_no_match++;
175
176 return ret;
177}
178
179static int dwmac4_rd_get_tx_len(struct dma_desc *p)
180{
181 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
182}
183
184static int dwmac4_get_tx_owner(struct dma_desc *p)
185{
186 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
187}
188
189static void dwmac4_set_tx_owner(struct dma_desc *p)
190{
191 p->des3 |= cpu_to_le32(TDES3_OWN);
192}
193
194static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
195{
196 p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
197
198 if (!disable_rx_ic)
199 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
200}
201
202static int dwmac4_get_tx_ls(struct dma_desc *p)
203{
204 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
205 >> TDES3_LAST_DESCRIPTOR_SHIFT;
206}
207
208static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
209{
210 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
211}
212
213static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
214{
215 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
216}
217
218static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
219{
220
221 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
222 return 0;
223
224
225 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
226 return 1;
227
228 return 0;
229}
230
231static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
232{
233 struct dma_desc *p = (struct dma_desc *)desc;
234 u64 ns;
235
236 ns = le32_to_cpu(p->des0);
237
238 ns += le32_to_cpu(p->des1) * 1000000000ULL;
239
240 *ts = ns;
241}
242
243static int dwmac4_rx_check_timestamp(void *desc)
244{
245 struct dma_desc *p = (struct dma_desc *)desc;
246 unsigned int rdes0 = le32_to_cpu(p->des0);
247 unsigned int rdes1 = le32_to_cpu(p->des1);
248 unsigned int rdes3 = le32_to_cpu(p->des3);
249 u32 own, ctxt;
250 int ret = 1;
251
252 own = rdes3 & RDES3_OWN;
253 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
254 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
255
256 if (likely(!own && ctxt)) {
257 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
258
259 ret = -EINVAL;
260 else
261
262 ret = 0;
263 }
264
265
266 return ret;
267}
268
269static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
270 u32 ats)
271{
272 struct dma_desc *p = (struct dma_desc *)desc;
273 int ret = -EINVAL;
274
275
276 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
277 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
278 int i = 0;
279
280
281 do {
282 ret = dwmac4_rx_check_timestamp(next_desc);
283 if (ret < 0)
284 goto exit;
285 i++;
286
287 } while ((ret == 1) && (i < 10));
288
289 if (i == 10)
290 ret = -EBUSY;
291 }
292 }
293exit:
294 if (likely(ret == 0))
295 return 1;
296
297 return 0;
298}
299
300static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
301 int mode, int end, int bfsize)
302{
303 dwmac4_set_rx_owner(p, disable_rx_ic);
304}
305
306static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
307{
308 p->des0 = 0;
309 p->des1 = 0;
310 p->des2 = 0;
311 p->des3 = 0;
312}
313
314static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
315 bool csum_flag, int mode, bool tx_own,
316 bool ls, unsigned int tot_pkt_len)
317{
318 unsigned int tdes3 = le32_to_cpu(p->des3);
319
320 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
321
322 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
323 if (is_fs)
324 tdes3 |= TDES3_FIRST_DESCRIPTOR;
325 else
326 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
327
328 if (likely(csum_flag))
329 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
330 else
331 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
332
333 if (ls)
334 tdes3 |= TDES3_LAST_DESCRIPTOR;
335 else
336 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
337
338
339 if (tx_own)
340 tdes3 |= TDES3_OWN;
341
342 if (is_fs && tx_own)
343
344
345
346
347 dma_wmb();
348
349 p->des3 = cpu_to_le32(tdes3);
350}
351
352static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
353 int len1, int len2, bool tx_own,
354 bool ls, unsigned int tcphdrlen,
355 unsigned int tcppayloadlen)
356{
357 unsigned int tdes3 = le32_to_cpu(p->des3);
358
359 if (len1)
360 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
361
362 if (len2)
363 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
364 & TDES2_BUFFER2_SIZE_MASK);
365
366 if (is_fs) {
367 tdes3 |= TDES3_FIRST_DESCRIPTOR |
368 TDES3_TCP_SEGMENTATION_ENABLE |
369 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
370 TDES3_SLOT_NUMBER_MASK) |
371 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
372 } else {
373 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
374 }
375
376 if (ls)
377 tdes3 |= TDES3_LAST_DESCRIPTOR;
378 else
379 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
380
381
382 if (tx_own)
383 tdes3 |= TDES3_OWN;
384
385 if (is_fs && tx_own)
386
387
388
389
390 dma_wmb();
391
392 p->des3 = cpu_to_le32(tdes3);
393}
394
395static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
396{
397 p->des0 = 0;
398 p->des1 = 0;
399 p->des2 = 0;
400 p->des3 = 0;
401}
402
403static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
404{
405 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
406}
407
408static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
409 dma_addr_t dma_rx_phy, unsigned int desc_size)
410{
411 dma_addr_t dma_addr;
412 int i;
413
414 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
415
416 if (desc_size == sizeof(struct dma_desc)) {
417 struct dma_desc *p = (struct dma_desc *)head;
418
419 for (i = 0; i < size; i++) {
420 dma_addr = dma_rx_phy + i * sizeof(*p);
421 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
422 i, &dma_addr,
423 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
424 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
425 p++;
426 }
427 } else if (desc_size == sizeof(struct dma_extended_desc)) {
428 struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
429
430 for (i = 0; i < size; i++) {
431 dma_addr = dma_rx_phy + i * sizeof(*extp);
432 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
433 i, &dma_addr,
434 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
435 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
436 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
437 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
438 extp++;
439 }
440 } else if (desc_size == sizeof(struct dma_edesc)) {
441 struct dma_edesc *ep = (struct dma_edesc *)head;
442
443 for (i = 0; i < size; i++) {
444 dma_addr = dma_rx_phy + i * sizeof(*ep);
445 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
446 i, &dma_addr,
447 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
448 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
449 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
450 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
451 ep++;
452 }
453 } else {
454 pr_err("unsupported descriptor!");
455 }
456}
457
458static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
459{
460 p->des0 = 0;
461 p->des1 = 0;
462 p->des2 = cpu_to_le32(mss);
463 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
464}
465
466static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
467{
468 *addr = le32_to_cpu(p->des0);
469}
470
471static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
472{
473 p->des0 = cpu_to_le32(lower_32_bits(addr));
474 p->des1 = cpu_to_le32(upper_32_bits(addr));
475}
476
477static void dwmac4_clear(struct dma_desc *p)
478{
479 p->des0 = 0;
480 p->des1 = 0;
481 p->des2 = 0;
482 p->des3 = 0;
483}
484
485static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
486{
487 sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
488
489 p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
490}
491
492static int set_16kib_bfsize(int mtu)
493{
494 int ret = 0;
495
496 if (unlikely(mtu >= BUF_SIZE_8KiB))
497 ret = BUF_SIZE_16KiB;
498 return ret;
499}
500
501static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
502 u32 inner_type)
503{
504 p->des0 = 0;
505 p->des1 = 0;
506 p->des2 = 0;
507 p->des3 = 0;
508
509
510 if (inner_type) {
511 u32 des = inner_tag << TDES2_IVT_SHIFT;
512
513 des &= TDES2_IVT_MASK;
514 p->des2 = cpu_to_le32(des);
515
516 des = inner_type << TDES3_IVTIR_SHIFT;
517 des &= TDES3_IVTIR_MASK;
518 p->des3 = cpu_to_le32(des | TDES3_IVLTV);
519 }
520
521
522 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
523 p->des3 |= cpu_to_le32(TDES3_VLTV);
524
525 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
526}
527
528static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
529{
530 type <<= TDES2_VLAN_TAG_SHIFT;
531 p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
532}
533
534static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
535{
536 *len = le32_to_cpu(p->des2) & RDES2_HL;
537}
538
539static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
540{
541 p->des2 = cpu_to_le32(lower_32_bits(addr));
542 p->des3 = cpu_to_le32(upper_32_bits(addr));
543
544 if (buf2_valid)
545 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
546 else
547 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
548}
549
550static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
551{
552 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
553 p->des5 = cpu_to_le32(nsec & TDES5_LT);
554 p->des6 = 0;
555 p->des7 = 0;
556}
557
558const struct stmmac_desc_ops dwmac4_desc_ops = {
559 .tx_status = dwmac4_wrback_get_tx_status,
560 .rx_status = dwmac4_wrback_get_rx_status,
561 .get_tx_len = dwmac4_rd_get_tx_len,
562 .get_tx_owner = dwmac4_get_tx_owner,
563 .set_tx_owner = dwmac4_set_tx_owner,
564 .set_rx_owner = dwmac4_set_rx_owner,
565 .get_tx_ls = dwmac4_get_tx_ls,
566 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
567 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
568 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
569 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
570 .get_timestamp = dwmac4_get_timestamp,
571 .set_tx_ic = dwmac4_rd_set_tx_ic,
572 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
573 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
574 .release_tx_desc = dwmac4_release_tx_desc,
575 .init_rx_desc = dwmac4_rd_init_rx_desc,
576 .init_tx_desc = dwmac4_rd_init_tx_desc,
577 .display_ring = dwmac4_display_ring,
578 .set_mss = dwmac4_set_mss_ctxt,
579 .get_addr = dwmac4_get_addr,
580 .set_addr = dwmac4_set_addr,
581 .clear = dwmac4_clear,
582 .set_sarc = dwmac4_set_sarc,
583 .set_vlan_tag = dwmac4_set_vlan_tag,
584 .set_vlan = dwmac4_set_vlan,
585 .get_rx_header_len = dwmac4_get_rx_header_len,
586 .set_sec_addr = dwmac4_set_sec_addr,
587 .set_tbs = dwmac4_set_tbs,
588};
589
590const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
591 .set_16kib_bfsize = set_16kib_bfsize,
592};
593
