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2
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4
5#include "main.h"
6#include "reg.h"
7#include "bf.h"
8#include "debug.h"
9
10void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11 struct ieee80211_bss_conf *bss_conf)
12{
13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14 struct rtw_bfee *bfee = &rtwvif->bfee;
15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16
17 if (bfee->role == RTW_BFEE_NONE)
18 return;
19
20 if (bfee->role == RTW_BFEE_MU)
21 bfinfo->bfer_mu_cnt--;
22 else if (bfee->role == RTW_BFEE_SU)
23 bfinfo->bfer_su_cnt--;
24
25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26
27 bfee->role = RTW_BFEE_NONE;
28}
29
30void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31 struct ieee80211_bss_conf *bss_conf)
32{
33 struct ieee80211_hw *hw = rtwdev->hw;
34 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
35 struct rtw_bfee *bfee = &rtwvif->bfee;
36 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
37 struct rtw_chip_info *chip = rtwdev->chip;
38 struct ieee80211_sta *sta;
39 struct ieee80211_sta_vht_cap *vht_cap;
40 struct ieee80211_sta_vht_cap *ic_vht_cap;
41 const u8 *bssid = bss_conf->bssid;
42 u32 sound_dim;
43 u8 i;
44
45 if (!(chip->band & RTW_BAND_5G))
46 return;
47
48 rcu_read_lock();
49
50 sta = ieee80211_find_sta(vif, bssid);
51 if (!sta) {
52 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
53 bssid);
54 goto out_unlock;
55 }
56
57 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
58 vht_cap = &sta->vht_cap;
59
60 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
61 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
62 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
63 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
64 goto out_unlock;
65 }
66
67 ether_addr_copy(bfee->mac_addr, bssid);
68 bfee->role = RTW_BFEE_MU;
69 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
70 bfee->aid = bss_conf->aid;
71 bfinfo->bfer_mu_cnt++;
72
73 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
74 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
75 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
76 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
77 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
78 goto out_unlock;
79 }
80
81 sound_dim = vht_cap->cap &
82 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
83 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
84
85 ether_addr_copy(bfee->mac_addr, bssid);
86 bfee->role = RTW_BFEE_SU;
87 bfee->sound_dim = (u8)sound_dim;
88 bfee->g_id = 0;
89 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
90 bfinfo->bfer_su_cnt++;
91 for (i = 0; i < chip->bfer_su_max_num; i++) {
92 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
93 set_bit(i, bfinfo->bfer_su_reg_maping);
94 bfee->su_reg_index = i;
95 break;
96 }
97 }
98
99 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
100 }
101
102out_unlock:
103 rcu_read_unlock();
104}
105
106void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
107 struct mu_bfer_init_para *param)
108{
109 u16 mu_bf_ctl = 0;
110 u8 *addr = param->bfer_address;
111 int i;
112
113 for (i = 0; i < ETH_ALEN; i++)
114 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
115 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
116 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
117
118 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
119 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
120 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
121}
122
123void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
124 enum rtw_trx_desc_rate rate)
125{
126 u32 psf_ctl = 0;
127 u8 csi_rsc = 0x1;
128
129 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
130 BIT_WMAC_USE_NDPARATE |
131 (csi_rsc << 13);
132
133 rtw_write8(rtwdev, REG_SND_PTCL_CTRL, RTW_SND_CTRL_SOUNDING);
134 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
135 rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
136 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
137
138 if (vif->net_type == RTW_NET_AP_MODE)
139 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
140 else
141 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
142}
143
144void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
145{
146 u8 mu_tbl_sel;
147 u8 mu_valid;
148
149 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
150 ~BIT_MASK_R_MU_TABLE_VALID;
151
152 rtw_write8(rtwdev, REG_MU_TX_CTL,
153 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
154
155 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
156
157 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
158 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
159 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
160 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
161 param->given_user_pos[1]);
162
163 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
164 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
165 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
166 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
167 param->given_user_pos[3]);
168}
169
170void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
171{
172 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
173 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
174 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
175 rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
176}
177
178void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
179{
180 rtw_write8(rtwdev, REG_SND_PTCL_CTRL, 0);
181}
182
183void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
184 struct rtw_bfee *bfee)
185{
186 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
187 u8 nr_index = bfee->sound_dim;
188 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
189 u32 addr_bfer_info, addr_csi_rpt, csi_param;
190 u8 i;
191
192 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
193
194 switch (bfee->su_reg_index) {
195 case 1:
196 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
197 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
198 break;
199 case 0:
200 default:
201 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
202 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
203 break;
204 }
205
206
207 rtw_write8(rtwdev, REG_SND_PTCL_CTRL, RTW_SND_CTRL_SOUNDING);
208
209
210 for (i = 0; i < ETH_ALEN; i++)
211 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
212
213 csi_param = (u16)((coefficientsize << 10) |
214 (codebookinfo << 8) |
215 (grouping << 6) |
216 (nr_index << 3) |
217 nc_index);
218 rtw_write16(rtwdev, addr_csi_rpt, csi_param);
219
220
221 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
222}
223EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
224
225
226
227
228
229void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
230 struct rtw_bfee *bfee)
231{
232 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
233 struct mu_bfer_init_para param;
234 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
235 u8 nr_index = 1;
236 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
237 u32 csi_param;
238
239 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
240
241 csi_param = (u16)((coefficientsize << 10) |
242 (codebookinfo << 8) |
243 (grouping << 6) |
244 (nr_index << 3) |
245 nc_index);
246
247 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
248 nc_index, nr_index, grouping, codebookinfo,
249 coefficientsize);
250
251 param.paid = bfee->p_aid;
252 param.csi_para = csi_param;
253 param.my_aid = bfee->aid & 0xfff;
254 param.csi_length_sel = HAL_CSI_SEG_4K;
255 ether_addr_copy(param.bfer_address, bfee->mac_addr);
256
257 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m);
258
259 bf_info->cur_csi_rpt_rate = DESC_RATE6M;
260 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
261
262
263 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
264
265
266 rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
267}
268EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
269
270void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
271 struct rtw_bfee *bfee)
272{
273 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
274
275 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
276 rtw_write8(rtwdev, REG_SND_PTCL_CTRL, RTW_SND_CTRL_REMOVE);
277
278 switch (bfee->su_reg_index) {
279 case 0:
280 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
281 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
282 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
283 break;
284 case 1:
285 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
286 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
287 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
288 break;
289 }
290
291 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
292 bfee->su_reg_index = 0xFF;
293}
294EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
295
296void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
297 struct rtw_bfee *bfee)
298{
299 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
300
301 rtw_write8(rtwdev, REG_SND_PTCL_CTRL, RTW_SND_CTRL_REMOVE);
302
303 rtw_bf_del_bfer_entry_mu(rtwdev);
304
305 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
306 rtw_bf_del_sounding(rtwdev);
307}
308EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
309
310void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
311 struct ieee80211_bss_conf *conf)
312{
313 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
314 struct rtw_bfee *bfee = &rtwvif->bfee;
315 struct cfg_mumimo_para param;
316
317 if (bfee->role != RTW_BFEE_MU) {
318 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
319 return;
320 }
321
322 param.grouping_bitmap = 0;
323 param.mu_tx_en = 0;
324 memset(param.sounding_sts, 0, 6);
325 memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
326 memcpy(param.given_user_pos, conf->mu_group.position, 16);
327 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
328 param.given_gid_tab[0], param.given_user_pos[0],
329 param.given_user_pos[1]);
330
331 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
332 param.given_gid_tab[1], param.given_user_pos[2],
333 param.given_user_pos[3]);
334
335 rtw_bf_cfg_mu_bfee(rtwdev, ¶m);
336}
337EXPORT_SYMBOL(rtw_bf_set_gid_table);
338
339void rtw_bf_phy_init(struct rtw_dev *rtwdev)
340{
341 u8 tmp8;
342 u32 tmp32;
343 u8 retry_limit = 0xA;
344 u8 ndpa_rate = 0x10;
345 u8 ack_policy = 3;
346
347 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
348
349 tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
350
351 tmp32 &= ~BIT_MASK_R_MU_RL;
352 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
353
354 tmp32 &= ~BIT_EN_MU_MIMO;
355
356 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
357 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
358
359
360 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
361 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
362 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
363
364
365 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
366
367 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
368
369 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
370
371 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
372 DESC_RATE6M);
373}
374EXPORT_SYMBOL(rtw_bf_phy_init);
375
376void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
377 u8 fixrate_en, u8 *new_rate)
378{
379 u32 csi_cfg;
380 u16 cur_rrsr;
381
382 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
383 cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
384
385 if (rssi >= 40) {
386 if (cur_rate != DESC_RATE54M) {
387 cur_rrsr |= BIT(DESC_RATE54M);
388 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
389 BIT_SHIFT_CSI_RATE;
390 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
391 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
392 }
393 *new_rate = DESC_RATE54M;
394 } else {
395 if (cur_rate != DESC_RATE24M) {
396 cur_rrsr &= ~BIT(DESC_RATE54M);
397 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
398 BIT_SHIFT_CSI_RATE;
399 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
400 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
401 }
402 *new_rate = DESC_RATE24M;
403 }
404}
405EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
406
