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50#include <linux/module.h>
51#include <linux/interrupt.h>
52
53#include "../comedi_pci.h"
54
55
56
57
58
59
60#define NI_65XX_ID_REG 0x00
61#define NI_65XX_CLR_REG 0x01
62#define NI_65XX_CLR_WDOG_INT BIT(6)
63#define NI_65XX_CLR_WDOG_PING BIT(5)
64#define NI_65XX_CLR_WDOG_EXP BIT(4)
65#define NI_65XX_CLR_EDGE_INT BIT(3)
66#define NI_65XX_CLR_OVERFLOW_INT BIT(2)
67#define NI_65XX_STATUS_REG 0x02
68#define NI_65XX_STATUS_WDOG_INT BIT(5)
69#define NI_65XX_STATUS_FALL_EDGE BIT(4)
70#define NI_65XX_STATUS_RISE_EDGE BIT(3)
71#define NI_65XX_STATUS_INT BIT(2)
72#define NI_65XX_STATUS_OVERFLOW_INT BIT(1)
73#define NI_65XX_STATUS_EDGE_INT BIT(0)
74#define NI_65XX_CTRL_REG 0x03
75#define NI_65XX_CTRL_WDOG_ENA BIT(5)
76#define NI_65XX_CTRL_FALL_EDGE_ENA BIT(4)
77#define NI_65XX_CTRL_RISE_EDGE_ENA BIT(3)
78#define NI_65XX_CTRL_INT_ENA BIT(2)
79#define NI_65XX_CTRL_OVERFLOW_ENA BIT(1)
80#define NI_65XX_CTRL_EDGE_ENA BIT(0)
81#define NI_65XX_REV_REG 0x04
82#define NI_65XX_FILTER_REG 0x08
83#define NI_65XX_RTSI_ROUTE_REG 0x0c
84#define NI_65XX_RTSI_EDGE_REG 0x0e
85#define NI_65XX_RTSI_WDOG_REG 0x10
86#define NI_65XX_RTSI_TRIG_REG 0x12
87#define NI_65XX_AUTO_CLK_SEL_REG 0x14
88#define NI_65XX_AUTO_CLK_SEL_STATUS BIT(1)
89#define NI_65XX_AUTO_CLK_SEL_DISABLE BIT(0)
90#define NI_65XX_WDOG_CTRL_REG 0x15
91#define NI_65XX_WDOG_CTRL_ENA BIT(0)
92#define NI_65XX_RTSI_CFG_REG 0x16
93#define NI_65XX_RTSI_CFG_RISE_SENSE BIT(2)
94#define NI_65XX_RTSI_CFG_FALL_SENSE BIT(1)
95#define NI_65XX_RTSI_CFG_SYNC_DETECT BIT(0)
96#define NI_65XX_WDOG_STATUS_REG 0x17
97#define NI_65XX_WDOG_STATUS_EXP BIT(0)
98#define NI_65XX_WDOG_INTERVAL_REG 0x18
99
100
101#define NI_65XX_PORT(x) ((x) * 0x10)
102#define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
103#define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
104#define NI_65XX_IO_SEL_OUTPUT 0
105#define NI_65XX_IO_SEL_INPUT BIT(0)
106#define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
107#define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
108#define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
109#define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
110#define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
111#define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
112#define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
113
114#define NI_65XX_PORT_TO_CHAN(x) ((x) * 8)
115#define NI_65XX_CHAN_TO_PORT(x) ((x) / 8)
116#define NI_65XX_CHAN_TO_MASK(x) (1 << ((x) % 8))
117
118enum ni_65xx_boardid {
119 BOARD_PCI6509,
120 BOARD_PXI6509,
121 BOARD_PCI6510,
122 BOARD_PCI6511,
123 BOARD_PXI6511,
124 BOARD_PCI6512,
125 BOARD_PXI6512,
126 BOARD_PCI6513,
127 BOARD_PXI6513,
128 BOARD_PCI6514,
129 BOARD_PXI6514,
130 BOARD_PCI6515,
131 BOARD_PXI6515,
132 BOARD_PCI6516,
133 BOARD_PCI6517,
134 BOARD_PCI6518,
135 BOARD_PCI6519,
136 BOARD_PCI6520,
137 BOARD_PCI6521,
138 BOARD_PXI6521,
139 BOARD_PCI6528,
140 BOARD_PXI6528,
141};
142
143struct ni_65xx_board {
144 const char *name;
145 unsigned int num_dio_ports;
146 unsigned int num_di_ports;
147 unsigned int num_do_ports;
148 unsigned int legacy_invert:1;
149};
150
151static const struct ni_65xx_board ni_65xx_boards[] = {
152 [BOARD_PCI6509] = {
153 .name = "pci-6509",
154 .num_dio_ports = 12,
155 },
156 [BOARD_PXI6509] = {
157 .name = "pxi-6509",
158 .num_dio_ports = 12,
159 },
160 [BOARD_PCI6510] = {
161 .name = "pci-6510",
162 .num_di_ports = 4,
163 },
164 [BOARD_PCI6511] = {
165 .name = "pci-6511",
166 .num_di_ports = 8,
167 },
168 [BOARD_PXI6511] = {
169 .name = "pxi-6511",
170 .num_di_ports = 8,
171 },
172 [BOARD_PCI6512] = {
173 .name = "pci-6512",
174 .num_do_ports = 8,
175 },
176 [BOARD_PXI6512] = {
177 .name = "pxi-6512",
178 .num_do_ports = 8,
179 },
180 [BOARD_PCI6513] = {
181 .name = "pci-6513",
182 .num_do_ports = 8,
183 .legacy_invert = 1,
184 },
185 [BOARD_PXI6513] = {
186 .name = "pxi-6513",
187 .num_do_ports = 8,
188 .legacy_invert = 1,
189 },
190 [BOARD_PCI6514] = {
191 .name = "pci-6514",
192 .num_di_ports = 4,
193 .num_do_ports = 4,
194 .legacy_invert = 1,
195 },
196 [BOARD_PXI6514] = {
197 .name = "pxi-6514",
198 .num_di_ports = 4,
199 .num_do_ports = 4,
200 .legacy_invert = 1,
201 },
202 [BOARD_PCI6515] = {
203 .name = "pci-6515",
204 .num_di_ports = 4,
205 .num_do_ports = 4,
206 .legacy_invert = 1,
207 },
208 [BOARD_PXI6515] = {
209 .name = "pxi-6515",
210 .num_di_ports = 4,
211 .num_do_ports = 4,
212 .legacy_invert = 1,
213 },
214 [BOARD_PCI6516] = {
215 .name = "pci-6516",
216 .num_do_ports = 4,
217 .legacy_invert = 1,
218 },
219 [BOARD_PCI6517] = {
220 .name = "pci-6517",
221 .num_do_ports = 4,
222 .legacy_invert = 1,
223 },
224 [BOARD_PCI6518] = {
225 .name = "pci-6518",
226 .num_di_ports = 2,
227 .num_do_ports = 2,
228 .legacy_invert = 1,
229 },
230 [BOARD_PCI6519] = {
231 .name = "pci-6519",
232 .num_di_ports = 2,
233 .num_do_ports = 2,
234 .legacy_invert = 1,
235 },
236 [BOARD_PCI6520] = {
237 .name = "pci-6520",
238 .num_di_ports = 1,
239 .num_do_ports = 1,
240 },
241 [BOARD_PCI6521] = {
242 .name = "pci-6521",
243 .num_di_ports = 1,
244 .num_do_ports = 1,
245 },
246 [BOARD_PXI6521] = {
247 .name = "pxi-6521",
248 .num_di_ports = 1,
249 .num_do_ports = 1,
250 },
251 [BOARD_PCI6528] = {
252 .name = "pci-6528",
253 .num_di_ports = 3,
254 .num_do_ports = 3,
255 },
256 [BOARD_PXI6528] = {
257 .name = "pxi-6528",
258 .num_di_ports = 3,
259 .num_do_ports = 3,
260 },
261};
262
263static bool ni_65xx_legacy_invert_outputs;
264module_param_named(legacy_invert_outputs, ni_65xx_legacy_invert_outputs,
265 bool, 0444);
266MODULE_PARM_DESC(legacy_invert_outputs,
267 "invert outputs of PCI/PXI-6513/6514/6515/6516/6517/6518/6519 for compatibility with old user code");
268
269static unsigned int ni_65xx_num_ports(struct comedi_device *dev)
270{
271 const struct ni_65xx_board *board = dev->board_ptr;
272
273 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
274}
275
276static void ni_65xx_disable_input_filters(struct comedi_device *dev)
277{
278 unsigned int num_ports = ni_65xx_num_ports(dev);
279 int i;
280
281
282 for (i = 0; i < num_ports; ++i)
283 writeb(0x00, dev->mmio + NI_65XX_FILTER_ENA(i));
284
285
286 writel(0x00000000, dev->mmio + NI_65XX_FILTER_REG);
287}
288
289
290static void ni_65xx_update_edge_detection(struct comedi_device *dev,
291 unsigned int base_chan,
292 unsigned int rising,
293 unsigned int falling)
294{
295 unsigned int num_ports = ni_65xx_num_ports(dev);
296 unsigned int port;
297
298 if (base_chan >= NI_65XX_PORT_TO_CHAN(num_ports))
299 return;
300
301 for (port = NI_65XX_CHAN_TO_PORT(base_chan); port < num_ports; port++) {
302 int bitshift = (int)(NI_65XX_PORT_TO_CHAN(port) - base_chan);
303 unsigned int port_mask, port_rising, port_falling;
304
305 if (bitshift >= 32)
306 break;
307
308 if (bitshift >= 0) {
309 port_mask = ~0U >> bitshift;
310 port_rising = rising >> bitshift;
311 port_falling = falling >> bitshift;
312 } else {
313 port_mask = ~0U << -bitshift;
314 port_rising = rising << -bitshift;
315 port_falling = falling << -bitshift;
316 }
317 if (port_mask & 0xff) {
318 if (~port_mask & 0xff) {
319 port_rising |=
320 readb(dev->mmio +
321 NI_65XX_RISE_EDGE_ENA_REG(port)) &
322 ~port_mask;
323 port_falling |=
324 readb(dev->mmio +
325 NI_65XX_FALL_EDGE_ENA_REG(port)) &
326 ~port_mask;
327 }
328 writeb(port_rising & 0xff,
329 dev->mmio + NI_65XX_RISE_EDGE_ENA_REG(port));
330 writeb(port_falling & 0xff,
331 dev->mmio + NI_65XX_FALL_EDGE_ENA_REG(port));
332 }
333 }
334}
335
336static void ni_65xx_disable_edge_detection(struct comedi_device *dev)
337{
338
339 ni_65xx_update_edge_detection(dev, 0, 0, 0);
340
341 ni_65xx_update_edge_detection(dev, 32, 0, 0);
342
343 ni_65xx_update_edge_detection(dev, 64, 0, 0);
344}
345
346static int ni_65xx_dio_insn_config(struct comedi_device *dev,
347 struct comedi_subdevice *s,
348 struct comedi_insn *insn,
349 unsigned int *data)
350{
351 unsigned long base_port = (unsigned long)s->private;
352 unsigned int chan = CR_CHAN(insn->chanspec);
353 unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
354 unsigned int port = base_port + NI_65XX_CHAN_TO_PORT(chan);
355 unsigned int interval;
356 unsigned int val;
357
358 switch (data[0]) {
359 case INSN_CONFIG_FILTER:
360
361
362
363
364
365 interval = (data[1] + 100) / 200;
366 if (interval > 0xfffff)
367 interval = 0xfffff;
368 data[1] = interval * 200;
369
370
371
372
373
374
375 val = readb(dev->mmio + NI_65XX_FILTER_ENA(port));
376 if (interval) {
377 writel(interval, dev->mmio + NI_65XX_FILTER_REG);
378 val |= chan_mask;
379 } else {
380 val &= ~chan_mask;
381 }
382 writeb(val, dev->mmio + NI_65XX_FILTER_ENA(port));
383 break;
384
385 case INSN_CONFIG_DIO_OUTPUT:
386 if (s->type != COMEDI_SUBD_DIO)
387 return -EINVAL;
388 writeb(NI_65XX_IO_SEL_OUTPUT,
389 dev->mmio + NI_65XX_IO_SEL_REG(port));
390 break;
391
392 case INSN_CONFIG_DIO_INPUT:
393 if (s->type != COMEDI_SUBD_DIO)
394 return -EINVAL;
395 writeb(NI_65XX_IO_SEL_INPUT,
396 dev->mmio + NI_65XX_IO_SEL_REG(port));
397 break;
398
399 case INSN_CONFIG_DIO_QUERY:
400 if (s->type != COMEDI_SUBD_DIO)
401 return -EINVAL;
402 val = readb(dev->mmio + NI_65XX_IO_SEL_REG(port));
403 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
404 : COMEDI_OUTPUT;
405 break;
406
407 default:
408 return -EINVAL;
409 }
410
411 return insn->n;
412}
413
414static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
415 struct comedi_subdevice *s,
416 struct comedi_insn *insn,
417 unsigned int *data)
418{
419 unsigned long base_port = (unsigned long)s->private;
420 unsigned int base_chan = CR_CHAN(insn->chanspec);
421 int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
422 unsigned int read_bits = 0;
423 int port_offset;
424
425 for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
426 port_offset <= last_port_offset; port_offset++) {
427 unsigned int port = base_port + port_offset;
428 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
429 unsigned int port_mask, port_data, bits;
430 int bitshift = base_port_channel - base_chan;
431
432 if (bitshift >= 32)
433 break;
434 port_mask = data[0];
435 port_data = data[1];
436 if (bitshift > 0) {
437 port_mask >>= bitshift;
438 port_data >>= bitshift;
439 } else {
440 port_mask <<= -bitshift;
441 port_data <<= -bitshift;
442 }
443 port_mask &= 0xff;
444 port_data &= 0xff;
445
446
447 if (port_mask) {
448 bits = readb(dev->mmio + NI_65XX_IO_DATA_REG(port));
449 bits ^= s->io_bits;
450 bits &= ~port_mask;
451 bits |= (port_data & port_mask);
452 bits ^= s->io_bits;
453 writeb(bits, dev->mmio + NI_65XX_IO_DATA_REG(port));
454 }
455
456
457 bits = readb(dev->mmio + NI_65XX_IO_DATA_REG(port));
458 bits ^= s->io_bits;
459 if (bitshift > 0)
460 bits <<= bitshift;
461 else
462 bits >>= -bitshift;
463
464 read_bits |= bits;
465 }
466 data[1] = read_bits;
467 return insn->n;
468}
469
470static irqreturn_t ni_65xx_interrupt(int irq, void *d)
471{
472 struct comedi_device *dev = d;
473 struct comedi_subdevice *s = dev->read_subdev;
474 unsigned int status;
475
476 status = readb(dev->mmio + NI_65XX_STATUS_REG);
477 if ((status & NI_65XX_STATUS_INT) == 0)
478 return IRQ_NONE;
479 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
480 return IRQ_NONE;
481
482 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
483 dev->mmio + NI_65XX_CLR_REG);
484
485 comedi_buf_write_samples(s, &s->state, 1);
486 comedi_handle_events(dev, s);
487
488 return IRQ_HANDLED;
489}
490
491static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
492 struct comedi_subdevice *s,
493 struct comedi_cmd *cmd)
494{
495 int err = 0;
496
497
498
499 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
500 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
501 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
502 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
503 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
504
505 if (err)
506 return 1;
507
508
509
510
511
512
513 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
514 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
515 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
516 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
517 cmd->chanlist_len);
518 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
519
520 if (err)
521 return 3;
522
523
524
525
526
527 return 0;
528}
529
530static int ni_65xx_intr_cmd(struct comedi_device *dev,
531 struct comedi_subdevice *s)
532{
533 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
534 dev->mmio + NI_65XX_CLR_REG);
535 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
536 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
537 dev->mmio + NI_65XX_CTRL_REG);
538
539 return 0;
540}
541
542static int ni_65xx_intr_cancel(struct comedi_device *dev,
543 struct comedi_subdevice *s)
544{
545 writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
546
547 return 0;
548}
549
550static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
551 struct comedi_subdevice *s,
552 struct comedi_insn *insn,
553 unsigned int *data)
554{
555 data[1] = 0;
556 return insn->n;
557}
558
559static int ni_65xx_intr_insn_config(struct comedi_device *dev,
560 struct comedi_subdevice *s,
561 struct comedi_insn *insn,
562 unsigned int *data)
563{
564 switch (data[0]) {
565 case INSN_CONFIG_CHANGE_NOTIFY:
566
567 if (insn->n != 3)
568 return -EINVAL;
569
570
571 ni_65xx_update_edge_detection(dev, 0, data[1], data[2]);
572
573 ni_65xx_update_edge_detection(dev, 32, 0, 0);
574
575 ni_65xx_update_edge_detection(dev, 64, 0, 0);
576 break;
577 case INSN_CONFIG_DIGITAL_TRIG:
578
579 if (data[1] != 0)
580 return -EINVAL;
581
582 switch (data[2]) {
583 case COMEDI_DIGITAL_TRIG_DISABLE:
584 ni_65xx_disable_edge_detection(dev);
585 break;
586 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
587
588
589
590
591 ni_65xx_update_edge_detection(dev, data[3],
592 data[4], data[5]);
593 break;
594 default:
595 return -EINVAL;
596 }
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 return insn->n;
603}
604
605
606#define MITE_IODWBSR 0xc0
607#define WENAB BIT(7)
608
609static int ni_65xx_mite_init(struct pci_dev *pcidev)
610{
611 void __iomem *mite_base;
612 u32 main_phys_addr;
613
614
615 mite_base = pci_ioremap_bar(pcidev, 0);
616 if (!mite_base)
617 return -ENOMEM;
618
619
620 main_phys_addr = pci_resource_start(pcidev, 1);
621 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
622
623
624 iounmap(mite_base);
625 return 0;
626}
627
628static int ni_65xx_auto_attach(struct comedi_device *dev,
629 unsigned long context)
630{
631 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
632 const struct ni_65xx_board *board = NULL;
633 struct comedi_subdevice *s;
634 unsigned int i;
635 int ret;
636
637 if (context < ARRAY_SIZE(ni_65xx_boards))
638 board = &ni_65xx_boards[context];
639 if (!board)
640 return -ENODEV;
641 dev->board_ptr = board;
642 dev->board_name = board->name;
643
644 ret = comedi_pci_enable(dev);
645 if (ret)
646 return ret;
647
648 ret = ni_65xx_mite_init(pcidev);
649 if (ret)
650 return ret;
651
652 dev->mmio = pci_ioremap_bar(pcidev, 1);
653 if (!dev->mmio)
654 return -ENOMEM;
655
656 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
657 dev->mmio + NI_65XX_CLR_REG);
658 writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
659
660 if (pcidev->irq) {
661 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
662 dev->board_name, dev);
663 if (ret == 0)
664 dev->irq = pcidev->irq;
665 }
666
667 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
668 readb(dev->mmio + NI_65XX_ID_REG));
669
670 ret = comedi_alloc_subdevices(dev, 4);
671 if (ret)
672 return ret;
673
674 s = &dev->subdevices[0];
675 if (board->num_di_ports) {
676 s->type = COMEDI_SUBD_DI;
677 s->subdev_flags = SDF_READABLE;
678 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
679 s->maxdata = 1;
680 s->range_table = &range_digital;
681 s->insn_bits = ni_65xx_dio_insn_bits;
682 s->insn_config = ni_65xx_dio_insn_config;
683
684
685 s->private = (void *)0;
686 } else {
687 s->type = COMEDI_SUBD_UNUSED;
688 }
689
690 s = &dev->subdevices[1];
691 if (board->num_do_ports) {
692 s->type = COMEDI_SUBD_DO;
693 s->subdev_flags = SDF_WRITABLE;
694 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
695 s->maxdata = 1;
696 s->range_table = &range_digital;
697 s->insn_bits = ni_65xx_dio_insn_bits;
698
699
700 s->private = (void *)(unsigned long)board->num_di_ports;
701
702
703
704
705
706
707 if (ni_65xx_legacy_invert_outputs && board->legacy_invert)
708 s->io_bits = 0xff;
709
710
711 for (i = 0; i < board->num_do_ports; ++i) {
712 writeb(s->io_bits,
713 dev->mmio +
714 NI_65XX_IO_DATA_REG(board->num_di_ports + i));
715 }
716 } else {
717 s->type = COMEDI_SUBD_UNUSED;
718 }
719
720 s = &dev->subdevices[2];
721 if (board->num_dio_ports) {
722 s->type = COMEDI_SUBD_DIO;
723 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
724 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
725 s->maxdata = 1;
726 s->range_table = &range_digital;
727 s->insn_bits = ni_65xx_dio_insn_bits;
728 s->insn_config = ni_65xx_dio_insn_config;
729
730
731 s->private = (void *)0;
732
733
734 for (i = 0; i < board->num_dio_ports; ++i) {
735 writeb(NI_65XX_IO_SEL_INPUT,
736 dev->mmio + NI_65XX_IO_SEL_REG(i));
737 }
738 } else {
739 s->type = COMEDI_SUBD_UNUSED;
740 }
741
742 s = &dev->subdevices[3];
743 s->type = COMEDI_SUBD_DI;
744 s->subdev_flags = SDF_READABLE;
745 s->n_chan = 1;
746 s->maxdata = 1;
747 s->range_table = &range_digital;
748 s->insn_bits = ni_65xx_intr_insn_bits;
749 if (dev->irq) {
750 dev->read_subdev = s;
751 s->subdev_flags |= SDF_CMD_READ;
752 s->len_chanlist = 1;
753 s->insn_config = ni_65xx_intr_insn_config;
754 s->do_cmdtest = ni_65xx_intr_cmdtest;
755 s->do_cmd = ni_65xx_intr_cmd;
756 s->cancel = ni_65xx_intr_cancel;
757 }
758
759 ni_65xx_disable_input_filters(dev);
760 ni_65xx_disable_edge_detection(dev);
761
762 return 0;
763}
764
765static void ni_65xx_detach(struct comedi_device *dev)
766{
767 if (dev->mmio)
768 writeb(0x00, dev->mmio + NI_65XX_CTRL_REG);
769 comedi_pci_detach(dev);
770}
771
772static struct comedi_driver ni_65xx_driver = {
773 .driver_name = "ni_65xx",
774 .module = THIS_MODULE,
775 .auto_attach = ni_65xx_auto_attach,
776 .detach = ni_65xx_detach,
777};
778
779static int ni_65xx_pci_probe(struct pci_dev *dev,
780 const struct pci_device_id *id)
781{
782 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
783}
784
785static const struct pci_device_id ni_65xx_pci_table[] = {
786 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
787 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
788 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
789 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
790 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
791 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
792 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
793 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
794 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
795 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
796 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
797 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
798 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
799 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
800 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
801 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
802 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
803 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
804 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
805 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
806 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
807 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
808 { 0 }
809};
810MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
811
812static struct pci_driver ni_65xx_pci_driver = {
813 .name = "ni_65xx",
814 .id_table = ni_65xx_pci_table,
815 .probe = ni_65xx_pci_probe,
816 .remove = comedi_pci_auto_unconfig,
817};
818module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
819
820MODULE_AUTHOR("Comedi http://www.comedi.org");
821MODULE_DESCRIPTION("Comedi driver for NI PCI-65xx static dio boards");
822MODULE_LICENSE("GPL");
823
