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7#ifndef __HAL_INTF_H__
8#define __HAL_INTF_H__
9
10
11enum RTL871X_HCI_TYPE {
12 RTW_PCIE = BIT0,
13 RTW_USB = BIT1,
14 RTW_SDIO = BIT2,
15 RTW_GSPI = BIT3,
16};
17
18enum HW_VARIABLES {
19 HW_VAR_MEDIA_STATUS,
20 HW_VAR_MEDIA_STATUS1,
21 HW_VAR_SET_OPMODE,
22 HW_VAR_MAC_ADDR,
23 HW_VAR_BSSID,
24 HW_VAR_INIT_RTS_RATE,
25 HW_VAR_BASIC_RATE,
26 HW_VAR_TXPAUSE,
27 HW_VAR_BCN_FUNC,
28 HW_VAR_CORRECT_TSF,
29 HW_VAR_CHECK_BSSID,
30 HW_VAR_MLME_DISCONNECT,
31 HW_VAR_MLME_SITESURVEY,
32 HW_VAR_MLME_JOIN,
33 HW_VAR_ON_RCR_AM,
34 HW_VAR_OFF_RCR_AM,
35 HW_VAR_BEACON_INTERVAL,
36 HW_VAR_SLOT_TIME,
37 HW_VAR_RESP_SIFS,
38 HW_VAR_ACK_PREAMBLE,
39 HW_VAR_SEC_CFG,
40 HW_VAR_SEC_DK_CFG,
41 HW_VAR_BCN_VALID,
42 HW_VAR_RF_TYPE,
43 HW_VAR_DM_FLAG,
44 HW_VAR_DM_FUNC_OP,
45 HW_VAR_DM_FUNC_SET,
46 HW_VAR_DM_FUNC_CLR,
47 HW_VAR_CAM_EMPTY_ENTRY,
48 HW_VAR_CAM_INVALID_ALL,
49 HW_VAR_CAM_WRITE,
50 HW_VAR_CAM_READ,
51 HW_VAR_AC_PARAM_VO,
52 HW_VAR_AC_PARAM_VI,
53 HW_VAR_AC_PARAM_BE,
54 HW_VAR_AC_PARAM_BK,
55 HW_VAR_ACM_CTRL,
56 HW_VAR_AMPDU_MIN_SPACE,
57 HW_VAR_AMPDU_FACTOR,
58 HW_VAR_RXDMA_AGG_PG_TH,
59 HW_VAR_SET_RPWM,
60 HW_VAR_CPWM,
61 HW_VAR_H2C_FW_PWRMODE,
62 HW_VAR_H2C_PS_TUNE_PARAM,
63 HW_VAR_H2C_FW_JOINBSSRPT,
64 HW_VAR_FWLPS_RF_ON,
65 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
66 HW_VAR_TDLS_WRCR,
67 HW_VAR_TDLS_INIT_CH_SEN,
68 HW_VAR_TDLS_RS_RCR,
69 HW_VAR_TDLS_DONE_CH_SEN,
70 HW_VAR_INITIAL_GAIN,
71 HW_VAR_TRIGGER_GPIO_0,
72 HW_VAR_BT_SET_COEXIST,
73 HW_VAR_BT_ISSUE_DELBA,
74 HW_VAR_CURRENT_ANTENNA,
75 HW_VAR_ANTENNA_DIVERSITY_LINK,
76 HW_VAR_ANTENNA_DIVERSITY_SELECT,
77 HW_VAR_SWITCH_EPHY_WoWLAN,
78 HW_VAR_EFUSE_USAGE,
79 HW_VAR_EFUSE_BYTES,
80 HW_VAR_EFUSE_BT_USAGE,
81 HW_VAR_EFUSE_BT_BYTES,
82 HW_VAR_FIFO_CLEARN_UP,
83 HW_VAR_CHECK_TXBUF,
84 HW_VAR_PCIE_STOP_TX_DMA,
85 HW_VAR_APFM_ON_MAC,
86
87
88#ifdef CONFIG_WOWLAN
89 HW_VAR_WOWLAN,
90 HW_VAR_WAKEUP_REASON,
91 HW_VAR_RPWM_TOG,
92#endif
93#ifdef CONFIG_AP_WOWLAN
94 HW_VAR_AP_WOWLAN,
95#endif
96 HW_VAR_SYS_CLKR,
97 HW_VAR_NAV_UPPER,
98 HW_VAR_C2H_HANDLE,
99 HW_VAR_RPT_TIMER_SETTING,
100 HW_VAR_TX_RPT_MAX_MACID,
101 HW_VAR_H2C_MEDIA_STATUS_RPT,
102 HW_VAR_CHK_HI_QUEUE_EMPTY,
103 HW_VAR_DL_BCN_SEL,
104 HW_VAR_AMPDU_MAX_TIME,
105 HW_VAR_WIRELESS_MODE,
106 HW_VAR_USB_MODE,
107 HW_VAR_PORT_SWITCH,
108 HW_VAR_DO_IQK,
109 HW_VAR_DM_IN_LPS,
110 HW_VAR_SET_REQ_FW_PS,
111 HW_VAR_FW_PS_STATE,
112 HW_VAR_SOUNDING_ENTER,
113 HW_VAR_SOUNDING_LEAVE,
114 HW_VAR_SOUNDING_RATE,
115 HW_VAR_SOUNDING_STATUS,
116 HW_VAR_SOUNDING_FW_NDPA,
117 HW_VAR_SOUNDING_CLK,
118 HW_VAR_DL_RSVD_PAGE,
119 HW_VAR_MACID_SLEEP,
120 HW_VAR_MACID_WAKEUP,
121};
122
123enum HAL_DEF_VARIABLE {
124 HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
125 HAL_DEF_IS_SUPPORT_ANT_DIV,
126 HAL_DEF_CURRENT_ANTENNA,
127 HAL_DEF_DRVINFO_SZ,
128 HAL_DEF_MAX_RECVBUF_SZ,
129 HAL_DEF_RX_PACKET_OFFSET,
130 HAL_DEF_DBG_DUMP_RXPKT,
131 HAL_DEF_DBG_DM_FUNC,
132 HAL_DEF_RA_DECISION_RATE,
133 HAL_DEF_RA_SGI,
134 HAL_DEF_PT_PWR_STATUS,
135 HAL_DEF_TX_LDPC,
136 HAL_DEF_RX_LDPC,
137 HAL_DEF_TX_STBC,
138 HAL_DEF_RX_STBC,
139 HAL_DEF_EXPLICIT_BEAMFORMER,
140 HAL_DEF_EXPLICIT_BEAMFORMEE,
141 HW_VAR_MAX_RX_AMPDU_FACTOR,
142 HW_DEF_RA_INFO_DUMP,
143 HAL_DEF_DBG_DUMP_TXPKT,
144 HW_DEF_FA_CNT_DUMP,
145 HW_DEF_ODM_DBG_FLAG,
146 HW_DEF_ODM_DBG_LEVEL,
147 HAL_DEF_TX_PAGE_SIZE,
148 HAL_DEF_TX_PAGE_BOUNDARY,
149 HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
150 HAL_DEF_ANT_DETECT,
151 HAL_DEF_PCI_SUUPORT_L1_BACKDOOR,
152 HAL_DEF_PCI_AMD_L1_SUPPORT,
153 HAL_DEF_PCI_ASPM_OSC,
154 HAL_DEF_MACID_SLEEP,
155 HAL_DEF_DBG_RX_INFO_DUMP,
156};
157
158enum HAL_ODM_VARIABLE {
159 HAL_ODM_STA_INFO,
160 HAL_ODM_P2P_STATE,
161 HAL_ODM_WIFI_DISPLAY_STATE,
162 HAL_ODM_NOISE_MONITOR,
163};
164
165enum HAL_INTF_PS_FUNC {
166 HAL_USB_SELECT_SUSPEND,
167 HAL_MAX_ID,
168};
169
170typedef s32 (*c2h_id_filter)(u8 *c2h_evt);
171
172struct hal_ops {
173 u32 (*hal_power_on)(struct adapter *padapter);
174 void (*hal_power_off)(struct adapter *padapter);
175 u32 (*hal_init)(struct adapter *padapter);
176 u32 (*hal_deinit)(struct adapter *padapter);
177
178 void (*free_hal_data)(struct adapter *padapter);
179
180 u32 (*inirp_init)(struct adapter *padapter);
181 u32 (*inirp_deinit)(struct adapter *padapter);
182 void (*irp_reset)(struct adapter *padapter);
183
184 s32 (*init_xmit_priv)(struct adapter *padapter);
185 void (*free_xmit_priv)(struct adapter *padapter);
186
187 s32 (*init_recv_priv)(struct adapter *padapter);
188 void (*free_recv_priv)(struct adapter *padapter);
189
190 void (*dm_init)(struct adapter *padapter);
191 void (*dm_deinit)(struct adapter *padapter);
192 void (*read_chip_version)(struct adapter *padapter);
193
194 void (*init_default_value)(struct adapter *padapter);
195
196 void (*intf_chip_configure)(struct adapter *padapter);
197
198 void (*read_adapter_info)(struct adapter *padapter);
199
200 void (*enable_interrupt)(struct adapter *padapter);
201 void (*disable_interrupt)(struct adapter *padapter);
202 u8 (*check_ips_status)(struct adapter *padapter);
203 s32 (*interrupt_handler)(struct adapter *padapter);
204 void (*clear_interrupt)(struct adapter *padapter);
205 void (*set_bwmode_handler)(struct adapter *padapter, enum CHANNEL_WIDTH Bandwidth, u8 Offset);
206 void (*set_channel_handler)(struct adapter *padapter, u8 channel);
207 void (*set_chnl_bw_handler)(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
208
209 void (*set_tx_power_level_handler)(struct adapter *padapter, u8 channel);
210 void (*get_tx_power_level_handler)(struct adapter *padapter, s32 *powerlevel);
211
212 void (*hal_dm_watchdog)(struct adapter *padapter);
213 void (*hal_dm_watchdog_in_lps)(struct adapter *padapter);
214
215
216 void (*SetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val);
217 void (*GetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val);
218
219 void (*SetHwRegHandlerWithBuf)(struct adapter *padapter, u8 variable, u8 *pbuf, int len);
220
221 u8 (*GetHalDefVarHandler)(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
222 u8 (*SetHalDefVarHandler)(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
223
224 void (*GetHalODMVarHandler)(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
225 void (*SetHalODMVarHandler)(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, bool bSet);
226
227 void (*UpdateRAMaskHandler)(struct adapter *padapter, u32 mac_id, u8 rssi_level);
228 void (*SetBeaconRelatedRegistersHandler)(struct adapter *padapter);
229
230 void (*Add_RateATid)(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
231
232 void (*run_thread)(struct adapter *padapter);
233 void (*cancel_thread)(struct adapter *padapter);
234
235 u8 (*interface_ps_func)(struct adapter *padapter, enum HAL_INTF_PS_FUNC efunc_id, u8 *val);
236
237 s32 (*hal_xmit)(struct adapter *padapter, struct xmit_frame *pxmitframe);
238
239
240
241 s32 (*mgnt_xmit)(struct adapter *padapter, struct xmit_frame *pmgntframe);
242 s32 (*hal_xmitframe_enqueue)(struct adapter *padapter, struct xmit_frame *pxmitframe);
243
244 u32 (*read_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask);
245 void (*write_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
246 u32 (*read_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask);
247 void (*write_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
248
249 void (*EfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState);
250 void (*BTEfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState);
251 void (*ReadEFuse)(struct adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest);
252 void (*EFUSEGetEfuseDefinition)(struct adapter *padapter, u8 efuseType, u8 type, void *pOut, bool bPseudoTest);
253 u16 (*EfuseGetCurrentSize)(struct adapter *padapter, u8 efuseType, bool bPseudoTest);
254 int (*Efuse_PgPacketRead)(struct adapter *padapter, u8 offset, u8 *data, bool bPseudoTest);
255 int (*Efuse_PgPacketWrite)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest);
256 u8 (*Efuse_WordEnableDataWrite)(struct adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest);
257 bool (*Efuse_PgPacketWrite_BT)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest);
258
259 s32 (*xmit_thread_handler)(struct adapter *padapter);
260 void (*hal_notch_filter)(struct adapter * adapter, bool enable);
261 void (*hal_reset_security_engine)(struct adapter * adapter);
262 s32 (*c2h_handler)(struct adapter *padapter, u8 *c2h_evt);
263 c2h_id_filter c2h_id_filter_ccx;
264
265 s32 (*fill_h2c_cmd)(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
266};
267
268enum RT_EEPROM_TYPE {
269 EEPROM_93C46,
270 EEPROM_93C56,
271 EEPROM_BOOT_EFUSE,
272};
273
274#define RF_CHANGE_BY_INIT 0
275#define RF_CHANGE_BY_IPS BIT28
276#define RF_CHANGE_BY_PS BIT29
277#define RF_CHANGE_BY_HW BIT30
278#define RF_CHANGE_BY_SW BIT31
279
280#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv)
281#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse)
282
283enum wowlan_subcode {
284 WOWLAN_PATTERN_MATCH = 1,
285 WOWLAN_MAGIC_PACKET = 2,
286 WOWLAN_UNICAST = 3,
287 WOWLAN_SET_PATTERN = 4,
288 WOWLAN_DUMP_REG = 5,
289 WOWLAN_ENABLE = 6,
290 WOWLAN_DISABLE = 7,
291 WOWLAN_STATUS = 8,
292 WOWLAN_DEBUG_RELOAD_FW = 9,
293 WOWLAN_DEBUG_1 = 10,
294 WOWLAN_DEBUG_2 = 11,
295 WOWLAN_AP_ENABLE = 12,
296 WOWLAN_AP_DISABLE = 13
297};
298
299struct wowlan_ioctl_param{
300 unsigned int subcode;
301 unsigned int subcode_value;
302 unsigned int wakeup_reason;
303 unsigned int len;
304 unsigned char pattern[0];
305};
306
307#define Rx_Pairwisekey 0x01
308#define Rx_GTK 0x02
309#define Rx_DisAssoc 0x04
310#define Rx_DeAuth 0x08
311#define Rx_ARPReq 0x09
312#define FWDecisionDisconnect 0x10
313#define Rx_MagicPkt 0x21
314#define Rx_UnicastPkt 0x22
315#define Rx_PatternPkt 0x23
316#define RX_PNOWakeUp 0x55
317#define AP_WakeUp 0x66
318
319void rtw_hal_def_value_init(struct adapter *padapter);
320
321void rtw_hal_free_data(struct adapter *padapter);
322
323void rtw_hal_dm_init(struct adapter *padapter);
324void rtw_hal_dm_deinit(struct adapter *padapter);
325
326uint rtw_hal_init(struct adapter *padapter);
327uint rtw_hal_deinit(struct adapter *padapter);
328void rtw_hal_stop(struct adapter *padapter);
329void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val);
330void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val);
331
332void rtw_hal_set_hwreg_with_buf(struct adapter *padapter, u8 variable, u8 *pbuf, int len);
333
334void rtw_hal_chip_configure(struct adapter *padapter);
335void rtw_hal_read_chip_info(struct adapter *padapter);
336void rtw_hal_read_chip_version(struct adapter *padapter);
337
338u8 rtw_hal_set_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
339u8 rtw_hal_get_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
340
341void rtw_hal_set_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, bool bSet);
342void rtw_hal_get_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
343
344void rtw_hal_enable_interrupt(struct adapter *padapter);
345void rtw_hal_disable_interrupt(struct adapter *padapter);
346
347u8 rtw_hal_check_ips_status(struct adapter *padapter);
348
349s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
350s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
351s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
352
353s32 rtw_hal_init_xmit_priv(struct adapter *padapter);
354void rtw_hal_free_xmit_priv(struct adapter *padapter);
355
356s32 rtw_hal_init_recv_priv(struct adapter *padapter);
357void rtw_hal_free_recv_priv(struct adapter *padapter);
358
359void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level);
360void rtw_hal_add_ra_tid(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
361
362void rtw_hal_start_thread(struct adapter *padapter);
363void rtw_hal_stop_thread(struct adapter *padapter);
364
365void rtw_hal_bcn_related_reg_setting(struct adapter *padapter);
366
367u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask);
368void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
369u32 rtw_hal_read_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
370void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
371
372#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
373#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
374#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
375#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
376
377#define PHY_SetMacReg PHY_SetBBReg
378#define PHY_QueryMacReg PHY_QueryBBReg
379
380void rtw_hal_set_chan(struct adapter *padapter, u8 channel);
381void rtw_hal_set_chnl_bw(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
382void rtw_hal_dm_watchdog(struct adapter *padapter);
383void rtw_hal_dm_watchdog_in_lps(struct adapter *padapter);
384
385s32 rtw_hal_xmit_thread_handler(struct adapter *padapter);
386
387void rtw_hal_notch_filter(struct adapter * adapter, bool enable);
388void rtw_hal_reset_security_engine(struct adapter * adapter);
389
390bool rtw_hal_c2h_valid(struct adapter *adapter, u8 *buf);
391s32 rtw_hal_c2h_evt_read(struct adapter *adapter, u8 *buf);
392s32 rtw_hal_c2h_handler(struct adapter *adapter, u8 *c2h_evt);
393c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter);
394
395s32 rtw_hal_is_disable_sw_channel_plan(struct adapter *padapter);
396
397s32 rtw_hal_macid_sleep(struct adapter *padapter, u32 macid);
398s32 rtw_hal_macid_wakeup(struct adapter *padapter, u32 macid);
399
400s32 rtw_hal_fill_h2c_cmd(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
401
402#endif
403
