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6
7
8#include <linux/spi/spi.h>
9#include <linux/of_gpio.h>
10
11#include "wilc_wfi_netdevice.h"
12
13struct wilc_spi {
14 int crc_off;
15 int nint;
16 int has_thrpt_enh;
17};
18
19static struct wilc_spi g_spi;
20static const struct wilc_hif_func wilc_hif_spi;
21
22
23
24
25
26
27
28static const u8 crc7_syndrome_table[256] = {
29 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
30 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
31 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
32 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
33 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
34 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
35 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
36 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
37 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
38 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
39 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
40 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
41 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
42 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
43 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
44 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
45 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
46 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
47 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
48 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
49 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
50 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
51 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
52 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
53 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
54 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
55 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
56 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
57 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
58 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
59 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
60 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
61};
62
63static u8 crc7_byte(u8 crc, u8 data)
64{
65 return crc7_syndrome_table[(crc << 1) ^ data];
66}
67
68static u8 crc7(u8 crc, const u8 *buffer, u32 len)
69{
70 while (len--)
71 crc = crc7_byte(crc, *buffer++);
72 return crc;
73}
74
75
76
77
78
79
80
81#define CMD_DMA_WRITE 0xc1
82#define CMD_DMA_READ 0xc2
83#define CMD_INTERNAL_WRITE 0xc3
84#define CMD_INTERNAL_READ 0xc4
85#define CMD_TERMINATE 0xc5
86#define CMD_REPEAT 0xc6
87#define CMD_DMA_EXT_WRITE 0xc7
88#define CMD_DMA_EXT_READ 0xc8
89#define CMD_SINGLE_WRITE 0xc9
90#define CMD_SINGLE_READ 0xca
91#define CMD_RESET 0xcf
92
93#define N_OK 1
94#define N_FAIL 0
95#define N_RESET -1
96#define N_RETRY -2
97
98#define DATA_PKT_SZ_256 256
99#define DATA_PKT_SZ_512 512
100#define DATA_PKT_SZ_1K 1024
101#define DATA_PKT_SZ_4K (4 * 1024)
102#define DATA_PKT_SZ_8K (8 * 1024)
103#define DATA_PKT_SZ DATA_PKT_SZ_8K
104
105#define USE_SPI_DMA 0
106
107static int wilc_bus_probe(struct spi_device *spi)
108{
109 int ret, gpio;
110 struct wilc *wilc;
111
112 gpio = of_get_gpio(spi->dev.of_node, 0);
113 if (gpio < 0)
114 gpio = GPIO_NUM;
115
116 ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
117 if (ret)
118 return ret;
119
120 spi_set_drvdata(spi, wilc);
121 wilc->dev = &spi->dev;
122
123 return 0;
124}
125
126static int wilc_bus_remove(struct spi_device *spi)
127{
128 wilc_netdev_cleanup(spi_get_drvdata(spi));
129 return 0;
130}
131
132static const struct of_device_id wilc1000_of_match[] = {
133 { .compatible = "atmel,wilc_spi", },
134 {}
135};
136MODULE_DEVICE_TABLE(of, wilc1000_of_match);
137
138static struct spi_driver wilc1000_spi_driver = {
139 .driver = {
140 .name = MODALIAS,
141 .of_match_table = wilc1000_of_match,
142 },
143 .probe = wilc_bus_probe,
144 .remove = wilc_bus_remove,
145};
146module_spi_driver(wilc1000_spi_driver);
147MODULE_LICENSE("GPL");
148
149static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
150{
151 struct spi_device *spi = to_spi_device(wilc->dev);
152 int ret;
153 struct spi_message msg;
154
155 if (len > 0 && b) {
156 struct spi_transfer tr = {
157 .tx_buf = b,
158 .len = len,
159 .delay_usecs = 0,
160 };
161 char *r_buffer = kzalloc(len, GFP_KERNEL);
162
163 if (!r_buffer)
164 return -ENOMEM;
165
166 tr.rx_buf = r_buffer;
167 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
168
169 memset(&msg, 0, sizeof(msg));
170 spi_message_init(&msg);
171 msg.spi = spi;
172 msg.is_dma_mapped = USE_SPI_DMA;
173 spi_message_add_tail(&tr, &msg);
174
175 ret = spi_sync(spi, &msg);
176 if (ret < 0)
177 dev_err(&spi->dev, "SPI transaction failed\n");
178
179 kfree(r_buffer);
180 } else {
181 dev_err(&spi->dev,
182 "can't write data with the following length: %d\n",
183 len);
184 ret = -EINVAL;
185 }
186
187 return ret;
188}
189
190static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
191{
192 struct spi_device *spi = to_spi_device(wilc->dev);
193 int ret;
194
195 if (rlen > 0) {
196 struct spi_message msg;
197 struct spi_transfer tr = {
198 .rx_buf = rb,
199 .len = rlen,
200 .delay_usecs = 0,
201
202 };
203 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
204
205 if (!t_buffer)
206 return -ENOMEM;
207
208 tr.tx_buf = t_buffer;
209
210 memset(&msg, 0, sizeof(msg));
211 spi_message_init(&msg);
212 msg.spi = spi;
213 msg.is_dma_mapped = USE_SPI_DMA;
214 spi_message_add_tail(&tr, &msg);
215
216 ret = spi_sync(spi, &msg);
217 if (ret < 0)
218 dev_err(&spi->dev, "SPI transaction failed\n");
219 kfree(t_buffer);
220 } else {
221 dev_err(&spi->dev,
222 "can't read data with the following length: %u\n",
223 rlen);
224 ret = -EINVAL;
225 }
226
227 return ret;
228}
229
230static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
231{
232 struct spi_device *spi = to_spi_device(wilc->dev);
233 int ret;
234
235 if (rlen > 0) {
236 struct spi_message msg;
237 struct spi_transfer tr = {
238 .rx_buf = rb,
239 .tx_buf = wb,
240 .len = rlen,
241 .bits_per_word = 8,
242 .delay_usecs = 0,
243
244 };
245
246 memset(&msg, 0, sizeof(msg));
247 spi_message_init(&msg);
248 msg.spi = spi;
249 msg.is_dma_mapped = USE_SPI_DMA;
250
251 spi_message_add_tail(&tr, &msg);
252 ret = spi_sync(spi, &msg);
253 if (ret < 0)
254 dev_err(&spi->dev, "SPI transaction failed\n");
255 } else {
256 dev_err(&spi->dev,
257 "can't read data with the following length: %u\n",
258 rlen);
259 ret = -EINVAL;
260 }
261
262 return ret;
263}
264
265static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
266 u8 clockless)
267{
268 struct spi_device *spi = to_spi_device(wilc->dev);
269 u8 wb[32], rb[32];
270 u8 wix, rix;
271 u32 len2;
272 u8 rsp;
273 int len = 0;
274 int result = N_OK;
275 int retry;
276 u8 crc[2];
277
278 wb[0] = cmd;
279 switch (cmd) {
280 case CMD_SINGLE_READ:
281 wb[1] = (u8)(adr >> 16);
282 wb[2] = (u8)(adr >> 8);
283 wb[3] = (u8)adr;
284 len = 5;
285 break;
286
287 case CMD_INTERNAL_READ:
288 wb[1] = (u8)(adr >> 8);
289 if (clockless == 1)
290 wb[1] |= BIT(7);
291 wb[2] = (u8)adr;
292 wb[3] = 0x00;
293 len = 5;
294 break;
295
296 case CMD_TERMINATE:
297 wb[1] = 0x00;
298 wb[2] = 0x00;
299 wb[3] = 0x00;
300 len = 5;
301 break;
302
303 case CMD_REPEAT:
304 wb[1] = 0x00;
305 wb[2] = 0x00;
306 wb[3] = 0x00;
307 len = 5;
308 break;
309
310 case CMD_RESET:
311 wb[1] = 0xff;
312 wb[2] = 0xff;
313 wb[3] = 0xff;
314 len = 5;
315 break;
316
317 case CMD_DMA_WRITE:
318 case CMD_DMA_READ:
319 wb[1] = (u8)(adr >> 16);
320 wb[2] = (u8)(adr >> 8);
321 wb[3] = (u8)adr;
322 wb[4] = (u8)(sz >> 8);
323 wb[5] = (u8)(sz);
324 len = 7;
325 break;
326
327 case CMD_DMA_EXT_WRITE:
328 case CMD_DMA_EXT_READ:
329 wb[1] = (u8)(adr >> 16);
330 wb[2] = (u8)(adr >> 8);
331 wb[3] = (u8)adr;
332 wb[4] = (u8)(sz >> 16);
333 wb[5] = (u8)(sz >> 8);
334 wb[6] = (u8)(sz);
335 len = 8;
336 break;
337
338 case CMD_INTERNAL_WRITE:
339 wb[1] = (u8)(adr >> 8);
340 if (clockless == 1)
341 wb[1] |= BIT(7);
342 wb[2] = (u8)(adr);
343 wb[3] = b[3];
344 wb[4] = b[2];
345 wb[5] = b[1];
346 wb[6] = b[0];
347 len = 8;
348 break;
349
350 case CMD_SINGLE_WRITE:
351 wb[1] = (u8)(adr >> 16);
352 wb[2] = (u8)(adr >> 8);
353 wb[3] = (u8)(adr);
354 wb[4] = b[3];
355 wb[5] = b[2];
356 wb[6] = b[1];
357 wb[7] = b[0];
358 len = 9;
359 break;
360
361 default:
362 result = N_FAIL;
363 break;
364 }
365
366 if (result != N_OK)
367 return result;
368
369 if (!g_spi.crc_off)
370 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
371 else
372 len -= 1;
373
374#define NUM_SKIP_BYTES (1)
375#define NUM_RSP_BYTES (2)
376#define NUM_DATA_HDR_BYTES (1)
377#define NUM_DATA_BYTES (4)
378#define NUM_CRC_BYTES (2)
379#define NUM_DUMMY_BYTES (3)
380 if (cmd == CMD_RESET ||
381 cmd == CMD_TERMINATE ||
382 cmd == CMD_REPEAT) {
383 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
384 } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
385 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
386 + NUM_DUMMY_BYTES;
387 if (!g_spi.crc_off)
388 len2 = len + tmp + NUM_CRC_BYTES;
389 else
390 len2 = len + tmp;
391 } else {
392 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
393 }
394#undef NUM_DUMMY_BYTES
395
396 if (len2 > ARRAY_SIZE(wb)) {
397 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
398 len2, ARRAY_SIZE(wb));
399 return N_FAIL;
400 }
401
402 for (wix = len; wix < len2; wix++)
403 wb[wix] = 0;
404 rix = len;
405
406 if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
407 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
408 return N_FAIL;
409 }
410
411
412
413
414 if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
415 rix++;
416
417 rsp = rb[rix++];
418
419 if (rsp != cmd) {
420 dev_err(&spi->dev,
421 "Failed cmd response, cmd (%02x), resp (%02x)\n",
422 cmd, rsp);
423 return N_FAIL;
424 }
425
426
427
428
429 rsp = rb[rix++];
430 if (rsp != 0x00) {
431 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
432 rsp);
433 return N_FAIL;
434 }
435
436 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
437 cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
438
439
440
441 retry = 100;
442 do {
443
444
445
446
447 if (rix < len2) {
448 rsp = rb[rix++];
449 } else {
450 retry = 0;
451 break;
452 }
453 if (((rsp >> 4) & 0xf) == 0xf)
454 break;
455 } while (retry--);
456
457 if (retry <= 0) {
458 dev_err(&spi->dev,
459 "Error, data read response (%02x)\n", rsp);
460 return N_RESET;
461 }
462 }
463
464 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
465
466
467
468 if ((rix + 3) < len2) {
469 b[0] = rb[rix++];
470 b[1] = rb[rix++];
471 b[2] = rb[rix++];
472 b[3] = rb[rix++];
473 } else {
474 dev_err(&spi->dev,
475 "buffer overrun when reading data.\n");
476 return N_FAIL;
477 }
478
479 if (!g_spi.crc_off) {
480
481
482
483 if ((rix + 1) < len2) {
484 crc[0] = rb[rix++];
485 crc[1] = rb[rix++];
486 } else {
487 dev_err(&spi->dev,
488 "buffer overrun when reading crc.\n");
489 return N_FAIL;
490 }
491 }
492 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
493 int ix;
494
495
496 for (ix = 0; (rix < len2) && (ix < sz); )
497 b[ix++] = rb[rix++];
498
499 sz -= ix;
500
501 if (sz > 0) {
502 int nbytes;
503
504 if (sz <= (DATA_PKT_SZ - ix))
505 nbytes = sz;
506 else
507 nbytes = DATA_PKT_SZ - ix;
508
509
510
511
512 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
513 dev_err(&spi->dev,
514 "Failed block read, bus err\n");
515 return N_FAIL;
516 }
517
518
519
520
521 if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
522 dev_err(&spi->dev,
523 "Failed block crc read, bus err\n");
524 return N_FAIL;
525 }
526
527 ix += nbytes;
528 sz -= nbytes;
529 }
530
531
532
533
534
535 while (sz > 0) {
536 int nbytes;
537
538 if (sz <= DATA_PKT_SZ)
539 nbytes = sz;
540 else
541 nbytes = DATA_PKT_SZ;
542
543
544
545
546
547
548
549
550
551 retry = 10;
552 do {
553 if (wilc_spi_rx(wilc, &rsp, 1)) {
554 dev_err(&spi->dev,
555 "Failed resp read, bus err\n");
556 result = N_FAIL;
557 break;
558 }
559 if (((rsp >> 4) & 0xf) == 0xf)
560 break;
561 } while (retry--);
562
563 if (result == N_FAIL)
564 break;
565
566
567
568
569 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
570 dev_err(&spi->dev,
571 "Failed block read, bus err\n");
572 result = N_FAIL;
573 break;
574 }
575
576
577
578
579 if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
580 dev_err(&spi->dev,
581 "Failed block crc read, bus err\n");
582 result = N_FAIL;
583 break;
584 }
585
586 ix += nbytes;
587 sz -= nbytes;
588 }
589 }
590 return result;
591}
592
593static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
594{
595 struct spi_device *spi = to_spi_device(wilc->dev);
596 int ix, nbytes;
597 int result = 1;
598 u8 cmd, order, crc[2] = {0};
599
600
601
602
603 ix = 0;
604 do {
605 if (sz <= DATA_PKT_SZ) {
606 nbytes = sz;
607 order = 0x3;
608 } else {
609 nbytes = DATA_PKT_SZ;
610 if (ix == 0)
611 order = 0x1;
612 else
613 order = 0x02;
614 }
615
616
617
618
619 cmd = 0xf0;
620 cmd |= order;
621
622 if (wilc_spi_tx(wilc, &cmd, 1)) {
623 dev_err(&spi->dev,
624 "Failed data block cmd write, bus error...\n");
625 result = N_FAIL;
626 break;
627 }
628
629
630
631
632 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
633 dev_err(&spi->dev,
634 "Failed data block write, bus error...\n");
635 result = N_FAIL;
636 break;
637 }
638
639
640
641
642 if (!g_spi.crc_off) {
643 if (wilc_spi_tx(wilc, crc, 2)) {
644 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
645 result = N_FAIL;
646 break;
647 }
648 }
649
650
651
652
653 ix += nbytes;
654 sz -= nbytes;
655 } while (sz);
656
657 return result;
658}
659
660
661
662
663
664
665
666static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
667{
668 struct spi_device *spi = to_spi_device(wilc->dev);
669 int result;
670
671 dat = cpu_to_le32(dat);
672 result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
673 0);
674 if (result != N_OK)
675 dev_err(&spi->dev, "Failed internal write cmd...\n");
676
677 return result;
678}
679
680static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
681{
682 struct spi_device *spi = to_spi_device(wilc->dev);
683 int result;
684
685 result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
686 0);
687 if (result != N_OK) {
688 dev_err(&spi->dev, "Failed internal read cmd...\n");
689 return 0;
690 }
691
692 *data = cpu_to_le32(*data);
693
694 return 1;
695}
696
697
698
699
700
701
702
703static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
704{
705 struct spi_device *spi = to_spi_device(wilc->dev);
706 int result = N_OK;
707 u8 cmd = CMD_SINGLE_WRITE;
708 u8 clockless = 0;
709
710 data = cpu_to_le32(data);
711 if (addr < 0x30) {
712
713 cmd = CMD_INTERNAL_WRITE;
714 clockless = 1;
715 }
716
717 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
718 if (result != N_OK)
719 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
720
721 return result;
722}
723
724static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
725{
726 struct spi_device *spi = to_spi_device(wilc->dev);
727 int result;
728
729
730
731
732 if (size <= 4)
733 return 0;
734
735 result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
736 if (result != N_OK) {
737 dev_err(&spi->dev,
738 "Failed cmd, write block (%08x)...\n", addr);
739 return 0;
740 }
741
742
743
744
745 result = spi_data_write(wilc, buf, size);
746 if (result != N_OK)
747 dev_err(&spi->dev, "Failed block data write...\n");
748
749 return 1;
750}
751
752static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
753{
754 struct spi_device *spi = to_spi_device(wilc->dev);
755 int result = N_OK;
756 u8 cmd = CMD_SINGLE_READ;
757 u8 clockless = 0;
758
759 if (addr < 0x30) {
760
761
762 cmd = CMD_INTERNAL_READ;
763 clockless = 1;
764 }
765
766 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
767 if (result != N_OK) {
768 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
769 return 0;
770 }
771
772 *data = cpu_to_le32(*data);
773
774 return 1;
775}
776
777static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
778{
779 struct spi_device *spi = to_spi_device(wilc->dev);
780 int result;
781
782 if (size <= 4)
783 return 0;
784
785 result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
786 if (result != N_OK) {
787 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
788 return 0;
789 }
790
791 return 1;
792}
793
794
795
796
797
798
799
800static int _wilc_spi_deinit(struct wilc *wilc)
801{
802
803
804
805 return 1;
806}
807
808static int wilc_spi_init(struct wilc *wilc, bool resume)
809{
810 struct spi_device *spi = to_spi_device(wilc->dev);
811 u32 reg;
812 u32 chipid;
813 static int isinit;
814
815 if (isinit) {
816 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
817 dev_err(&spi->dev, "Fail cmd read chip id...\n");
818 return 0;
819 }
820 return 1;
821 }
822
823 memset(&g_spi, 0, sizeof(struct wilc_spi));
824
825
826
827
828 g_spi.crc_off = 0;
829
830
831
832
833
834
835 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
836
837
838
839
840 g_spi.crc_off = 1;
841 dev_err(&spi->dev,
842 "Failed read with CRC on, retrying with CRC off\n");
843 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
844
845
846
847
848 dev_err(&spi->dev, "Failed internal read protocol\n");
849 return 0;
850 }
851 }
852 if (g_spi.crc_off == 0) {
853 reg &= ~0xc;
854 reg &= ~0x70;
855 reg |= (0x5 << 4);
856 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
857 dev_err(&spi->dev,
858 "[wilc spi %d]: Failed internal write reg\n",
859 __LINE__);
860 return 0;
861 }
862 g_spi.crc_off = 1;
863 }
864
865
866
867
868 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
869 dev_err(&spi->dev, "Fail cmd read chip id...\n");
870 return 0;
871 }
872
873 g_spi.has_thrpt_enh = 1;
874
875 isinit = 1;
876
877 return 1;
878}
879
880static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
881{
882 struct spi_device *spi = to_spi_device(wilc->dev);
883 int ret;
884
885 if (g_spi.has_thrpt_enh) {
886 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
887 size);
888 *size = *size & IRQ_DMA_WD_CNT_MASK;
889 } else {
890 u32 tmp;
891 u32 byte_cnt;
892
893 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
894 &byte_cnt);
895 if (!ret) {
896 dev_err(&spi->dev,
897 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
898 return ret;
899 }
900 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
901 *size = tmp;
902 }
903
904 return ret;
905}
906
907static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
908{
909 struct spi_device *spi = to_spi_device(wilc->dev);
910 int ret;
911 u32 tmp;
912 u32 byte_cnt;
913 int happened, j;
914 u32 unknown_mask;
915 u32 irq_flags;
916 int k = IRG_FLAGS_OFFSET + 5;
917
918 if (g_spi.has_thrpt_enh) {
919 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
920 int_status);
921 return ret;
922 }
923 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
924 if (!ret) {
925 dev_err(&spi->dev,
926 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
927 return ret;
928 }
929 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
930
931 j = 0;
932 do {
933 happened = 0;
934
935 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
936 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
937
938 if (g_spi.nint > 5) {
939 wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
940 tmp |= (((irq_flags >> 0) & 0x7) << k);
941 }
942
943 unknown_mask = ~((1ul << g_spi.nint) - 1);
944
945 if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
946 dev_err(&spi->dev,
947 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
948 j, tmp, unknown_mask);
949 happened = 1;
950 }
951
952 j++;
953 } while (happened);
954
955 *int_status = tmp;
956
957 return ret;
958}
959
960static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
961{
962 struct spi_device *spi = to_spi_device(wilc->dev);
963 int ret;
964 u32 flags;
965 u32 tbl_ctl;
966
967 if (g_spi.has_thrpt_enh) {
968 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
969 val);
970 return ret;
971 }
972
973 flags = val & (BIT(MAX_NUM_INT) - 1);
974 if (flags) {
975 int i;
976
977 ret = 1;
978 for (i = 0; i < g_spi.nint; i++) {
979
980
981
982
983 if (flags & 1)
984 ret = wilc_spi_write_reg(wilc,
985 0x10c8 + i * 4, 1);
986 if (!ret)
987 break;
988 flags >>= 1;
989 }
990 if (!ret) {
991 dev_err(&spi->dev,
992 "Failed wilc_spi_write_reg, set reg %x ...\n",
993 0x10c8 + i * 4);
994 return ret;
995 }
996 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
997 if (flags & 1)
998 dev_err(&spi->dev,
999 "Unexpected interrupt cleared %d...\n",
1000 i);
1001 flags >>= 1;
1002 }
1003 }
1004
1005 tbl_ctl = 0;
1006
1007 if (val & SEL_VMM_TBL0)
1008 tbl_ctl |= BIT(0);
1009
1010 if (val & SEL_VMM_TBL1)
1011 tbl_ctl |= BIT(1);
1012
1013 ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1014 if (!ret) {
1015 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1016 return ret;
1017 }
1018
1019 if (val & EN_VMM) {
1020
1021
1022
1023 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1024 if (!ret) {
1025 dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1026 return ret;
1027 }
1028 }
1029
1030 return ret;
1031}
1032
1033static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1034{
1035 struct spi_device *spi = to_spi_device(wilc->dev);
1036 u32 reg;
1037 int ret, i;
1038
1039 if (nint > MAX_NUM_INT) {
1040 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1041 return 0;
1042 }
1043
1044 g_spi.nint = nint;
1045
1046
1047
1048
1049 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1050 if (!ret) {
1051 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1052 WILC_PIN_MUX_0);
1053 return 0;
1054 }
1055 reg |= BIT(8);
1056 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1057 if (!ret) {
1058 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1059 WILC_PIN_MUX_0);
1060 return 0;
1061 }
1062
1063
1064
1065
1066 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1067 if (!ret) {
1068 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1069 WILC_INTR_ENABLE);
1070 return 0;
1071 }
1072
1073 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1074 reg |= (BIT((27 + i)));
1075
1076 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1077 if (!ret) {
1078 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1079 WILC_INTR_ENABLE);
1080 return 0;
1081 }
1082 if (nint) {
1083 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1084 if (!ret) {
1085 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1086 WILC_INTR2_ENABLE);
1087 return 0;
1088 }
1089
1090 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1091 reg |= BIT(i);
1092
1093 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1094 if (!ret) {
1095 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1096 WILC_INTR2_ENABLE);
1097 return 0;
1098 }
1099 }
1100
1101 return 1;
1102}
1103
1104
1105static const struct wilc_hif_func wilc_hif_spi = {
1106 .hif_init = wilc_spi_init,
1107 .hif_deinit = _wilc_spi_deinit,
1108 .hif_read_reg = wilc_spi_read_reg,
1109 .hif_write_reg = wilc_spi_write_reg,
1110 .hif_block_rx = wilc_spi_read,
1111 .hif_block_tx = wilc_spi_write,
1112 .hif_read_int = wilc_spi_read_int,
1113 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1114 .hif_read_size = wilc_spi_read_size,
1115 .hif_block_tx_ext = wilc_spi_write,
1116 .hif_block_rx_ext = wilc_spi_read,
1117 .hif_sync_ext = wilc_spi_sync_ext,
1118};
1119
