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14#include <linux/fb.h>
15#include <linux/delay.h>
16#include <asm/io.h>
17#include <asm/delay.h>
18#include <asm/msr.h>
19#include <linux/cs5535.h>
20
21#include "gxfb.h"
22
23
24
25
26
27struct gx_pll_entry {
28 long pixclock;
29 u32 sys_rstpll_bits;
30 u32 dotpll_value;
31};
32
33#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
34#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
35#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
36
37static const struct gx_pll_entry gx_pll_table_48MHz[] = {
38 { 40123, POSTDIV3, 0x00000BF2 },
39 { 39721, 0, 0x00000037 },
40 { 35308, POSTDIV3|PREMULT2, 0x00000B1A },
41 { 31746, POSTDIV3, 0x000002D2 },
42 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 },
43 { 26666, POSTDIV3, 0x0000057A },
44 { 25000, POSTDIV3, 0x0000030A },
45 { 22271, 0, 0x00000063 },
46 { 20202, 0, 0x0000054B },
47 { 20000, 0, 0x0000026E },
48 { 19860, PREMULT2, 0x00000037 },
49 { 18518, POSTDIV3|PREMULT2, 0x00000B0D },
50 { 17777, 0, 0x00000577 },
51 { 17733, 0, 0x000007F7 },
52 { 17653, 0, 0x0000057B },
53 { 16949, PREMULT2, 0x00000707 },
54 { 15873, POSTDIV3|PREMULT2, 0x00000B39 },
55 { 15384, POSTDIV3|PREMULT2, 0x00000B45 },
56 { 14814, POSTDIV3|PREMULT2, 0x00000FC1 },
57 { 14124, POSTDIV3, 0x00000561 },
58 { 13888, POSTDIV3, 0x000007E1 },
59 { 13426, PREMULT2, 0x00000F4A },
60 { 13333, 0, 0x00000052 },
61 { 12698, 0, 0x00000056 },
62 { 12500, POSTDIV3|PREMULT2, 0x00000709 },
63 { 11135, PREMULT2, 0x00000262 },
64 { 10582, 0, 0x000002D2 },
65 { 10101, PREMULT2, 0x00000B4A },
66 { 10000, PREMULT2, 0x00000036 },
67 { 9259, 0, 0x000007E2 },
68 { 8888, 0, 0x000007F6 },
69 { 7692, POSTDIV3|PREMULT2, 0x00000FB0 },
70 { 7407, POSTDIV3|PREMULT2, 0x00000B50 },
71 { 6349, 0, 0x00000055 },
72 { 6172, 0, 0x000009C1 },
73 { 5787, PREMULT2, 0x0000002D },
74 { 5698, 0, 0x000002C1 },
75 { 5291, 0, 0x000002D1 },
76 { 4938, 0, 0x00000551 },
77 { 4357, 0, 0x0000057D },
78};
79
80static const struct gx_pll_entry gx_pll_table_14MHz[] = {
81 { 39721, 0, 0x00000037 },
82 { 35308, 0, 0x00000B7B },
83 { 31746, 0, 0x000004D3 },
84 { 27777, 0, 0x00000BE3 },
85 { 26666, 0, 0x0000074F },
86 { 25000, 0, 0x0000050B },
87 { 22271, 0, 0x00000063 },
88 { 20202, 0, 0x0000054B },
89 { 20000, 0, 0x0000026E },
90 { 19860, 0, 0x000007C3 },
91 { 18518, 0, 0x000007E3 },
92 { 17777, 0, 0x00000577 },
93 { 17733, 0, 0x000002FB },
94 { 17653, 0, 0x0000057B },
95 { 16949, 0, 0x0000058B },
96 { 15873, 0, 0x0000095E },
97 { 15384, 0, 0x0000096A },
98 { 14814, 0, 0x00000BC2 },
99 { 14124, 0, 0x0000098A },
100 { 13888, 0, 0x00000BE2 },
101 { 13333, 0, 0x00000052 },
102 { 12698, 0, 0x00000056 },
103 { 12500, 0, 0x0000050A },
104 { 11135, 0, 0x0000078E },
105 { 10582, 0, 0x000002D2 },
106 { 10101, 0, 0x000011F6 },
107 { 10000, 0, 0x0000054E },
108 { 9259, 0, 0x000007E2 },
109 { 8888, 0, 0x000002FA },
110 { 7692, 0, 0x00000BB1 },
111 { 7407, 0, 0x00000975 },
112 { 6349, 0, 0x00000055 },
113 { 6172, 0, 0x000009C1 },
114 { 5698, 0, 0x000002C1 },
115 { 5291, 0, 0x00000539 },
116 { 4938, 0, 0x00000551 },
117 { 4357, 0, 0x0000057D },
118};
119
120void gx_set_dclk_frequency(struct fb_info *info)
121{
122 const struct gx_pll_entry *pll_table;
123 int pll_table_len;
124 int i, best_i;
125 long min, diff;
126 u64 dotpll, sys_rstpll;
127 int timeout = 1000;
128
129
130 if (cpu_data(0).x86_stepping == 1) {
131 pll_table = gx_pll_table_14MHz;
132 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
133 } else {
134 pll_table = gx_pll_table_48MHz;
135 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
136 }
137
138
139 best_i = 0;
140 min = abs(pll_table[0].pixclock - info->var.pixclock);
141 for (i = 1; i < pll_table_len; i++) {
142 diff = abs(pll_table[i].pixclock - info->var.pixclock);
143 if (diff < min) {
144 min = diff;
145 best_i = i;
146 }
147 }
148
149 rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
150 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
151
152
153 dotpll &= 0x00000000ffffffffull;
154 dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
155 dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
156 dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
157
158 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
159
160
161 sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
162 | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
163 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
164 sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
165
166 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
167
168
169 dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
170 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
171
172
173 do {
174 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
175 } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
176}
177
178static void
179gx_configure_tft(struct fb_info *info)
180{
181 struct gxfb_par *par = info->par;
182 unsigned long val;
183 unsigned long fp;
184
185
186
187 rdmsrl(MSR_GX_MSR_PADSEL, val);
188 val &= ~MSR_GX_MSR_PADSEL_MASK;
189 val |= MSR_GX_MSR_PADSEL_TFT;
190 wrmsrl(MSR_GX_MSR_PADSEL, val);
191
192
193
194 fp = read_fp(par, FP_PM);
195 fp &= ~FP_PM_P;
196 write_fp(par, FP_PM, fp);
197
198
199
200 fp = read_fp(par, FP_PT1);
201 fp &= FP_PT1_VSIZE_MASK;
202 fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
203 write_fp(par, FP_PT1, fp);
204
205
206
207
208 fp = 0x0F100000;
209
210
211
212 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
213 fp |= FP_PT2_VSP;
214
215 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
216 fp |= FP_PT2_HSP;
217
218 write_fp(par, FP_PT2, fp);
219
220
221 write_fp(par, FP_DFC, FP_DFC_NFI);
222
223
224
225 fp = read_vp(par, VP_DCFG);
226 fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
227 write_vp(par, VP_DCFG, fp);
228
229
230
231 fp = read_fp(par, FP_PM);
232 fp |= FP_PM_P;
233 write_fp(par, FP_PM, fp);
234}
235
236void gx_configure_display(struct fb_info *info)
237{
238 struct gxfb_par *par = info->par;
239 u32 dcfg, misc;
240
241
242 dcfg = read_vp(par, VP_DCFG);
243
244
245 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
246 write_vp(par, VP_DCFG, dcfg);
247
248
249 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
250 | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
251 | VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
252
253
254 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
255
256
257 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
258
259 misc = read_vp(par, VP_MISC);
260
261
262 misc |= VP_MISC_GAM_EN;
263
264 if (par->enable_crt) {
265
266
267 misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
268 write_vp(par, VP_MISC, misc);
269
270
271
272
273 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
274 dcfg |= VP_DCFG_CRT_HSYNC_POL;
275 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
276 dcfg |= VP_DCFG_CRT_VSYNC_POL;
277 } else {
278
279 misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
280 write_vp(par, VP_MISC, misc);
281 }
282
283
284
285
286 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
287
288
289
290 write_vp(par, VP_DCFG, dcfg);
291
292
293
294 if (par->enable_crt == 0)
295 gx_configure_tft(info);
296}
297
298int gx_blank_display(struct fb_info *info, int blank_mode)
299{
300 struct gxfb_par *par = info->par;
301 u32 dcfg, fp_pm;
302 int blank, hsync, vsync, crt;
303
304
305 switch (blank_mode) {
306 case FB_BLANK_UNBLANK:
307 blank = 0; hsync = 1; vsync = 1; crt = 1;
308 break;
309 case FB_BLANK_NORMAL:
310 blank = 1; hsync = 1; vsync = 1; crt = 1;
311 break;
312 case FB_BLANK_VSYNC_SUSPEND:
313 blank = 1; hsync = 1; vsync = 0; crt = 1;
314 break;
315 case FB_BLANK_HSYNC_SUSPEND:
316 blank = 1; hsync = 0; vsync = 1; crt = 1;
317 break;
318 case FB_BLANK_POWERDOWN:
319 blank = 1; hsync = 0; vsync = 0; crt = 0;
320 break;
321 default:
322 return -EINVAL;
323 }
324 dcfg = read_vp(par, VP_DCFG);
325 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
326 VP_DCFG_CRT_EN);
327 if (!blank)
328 dcfg |= VP_DCFG_DAC_BL_EN;
329 if (hsync)
330 dcfg |= VP_DCFG_HSYNC_EN;
331 if (vsync)
332 dcfg |= VP_DCFG_VSYNC_EN;
333 if (crt)
334 dcfg |= VP_DCFG_CRT_EN;
335 write_vp(par, VP_DCFG, dcfg);
336
337
338
339 if (par->enable_crt == 0) {
340 fp_pm = read_fp(par, FP_PM);
341 if (blank_mode == FB_BLANK_POWERDOWN)
342 fp_pm &= ~FP_PM_P;
343 else
344 fp_pm |= FP_PM_P;
345 write_fp(par, FP_PM, fp_pm);
346 }
347
348 return 0;
349}
350