LXR linux/include/linux/lightnvm.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef NVM_H
   3#define NVM_H
   4
   5#include <linux/blkdev.h>
   6#include <linux/types.h>
   7#include <uapi/linux/lightnvm.h>
   8
   9enum {
  10        NVM_IO_OK = 0,
  11        NVM_IO_REQUEUE = 1,
  12        NVM_IO_DONE = 2,
  13        NVM_IO_ERR = 3,
  14
  15        NVM_IOTYPE_NONE = 0,
  16        NVM_IOTYPE_GC = 1,
  17};
  18
  19/* common format */
  20#define NVM_GEN_CH_BITS  (8)
  21#define NVM_GEN_LUN_BITS (8)
  22#define NVM_GEN_BLK_BITS (16)
  23#define NVM_GEN_RESERVED (32)
  24
  25/* 1.2 format */
  26#define NVM_12_PG_BITS  (16)
  27#define NVM_12_PL_BITS  (4)
  28#define NVM_12_SEC_BITS (4)
  29#define NVM_12_RESERVED (8)
  30
  31/* 2.0 format */
  32#define NVM_20_SEC_BITS (24)
  33#define NVM_20_RESERVED (8)
  34
  35enum {
  36        NVM_OCSSD_SPEC_12 = 12,
  37        NVM_OCSSD_SPEC_20 = 20,
  38};
  39
  40struct ppa_addr {
  41        /* Generic structure for all addresses */
  42        union {
  43                /* generic device format */
  44                struct {
  45                        u64 ch          : NVM_GEN_CH_BITS;
  46                        u64 lun         : NVM_GEN_LUN_BITS;
  47                        u64 blk         : NVM_GEN_BLK_BITS;
  48                        u64 reserved    : NVM_GEN_RESERVED;
  49                } a;
  50
  51                /* 1.2 device format */
  52                struct {
  53                        u64 ch          : NVM_GEN_CH_BITS;
  54                        u64 lun         : NVM_GEN_LUN_BITS;
  55                        u64 blk         : NVM_GEN_BLK_BITS;
  56                        u64 pg          : NVM_12_PG_BITS;
  57                        u64 pl          : NVM_12_PL_BITS;
  58                        u64 sec         : NVM_12_SEC_BITS;
  59                        u64 reserved    : NVM_12_RESERVED;
  60                } g;
  61
  62                /* 2.0 device format */
  63                struct {
  64                        u64 grp         : NVM_GEN_CH_BITS;
  65                        u64 pu          : NVM_GEN_LUN_BITS;
  66                        u64 chk         : NVM_GEN_BLK_BITS;
  67                        u64 sec         : NVM_20_SEC_BITS;
  68                        u64 reserved    : NVM_20_RESERVED;
  69                } m;
  70
  71                struct {
  72                        u64 line        : 63;
  73                        u64 is_cached   : 1;
  74                } c;
  75
  76                u64 ppa;
  77        };
  78};
  79
  80struct nvm_rq;
  81struct nvm_id;
  82struct nvm_dev;
  83struct nvm_tgt_dev;
  84struct nvm_chk_meta;
  85
  86typedef int (nvm_id_fn)(struct nvm_dev *);
  87typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
  88typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
  89typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, struct nvm_chk_meta *,
  90                                                                sector_t, int);
  91typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
  92typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *);
  93typedef void (nvm_destroy_dma_pool_fn)(void *);
  94typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
  95                                                                dma_addr_t *);
  96typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);
  97
  98struct nvm_dev_ops {
  99        nvm_id_fn               *identity;
 100        nvm_op_bb_tbl_fn        *get_bb_tbl;
 101        nvm_op_set_bb_fn        *set_bb_tbl;
 102
 103        nvm_get_chk_meta_fn     *get_chk_meta;
 104
 105        nvm_submit_io_fn        *submit_io;
 106
 107        nvm_create_dma_pool_fn  *create_dma_pool;
 108        nvm_destroy_dma_pool_fn *destroy_dma_pool;
 109        nvm_dev_dma_alloc_fn    *dev_dma_alloc;
 110        nvm_dev_dma_free_fn     *dev_dma_free;
 111};
 112
 113#ifdef CONFIG_NVM
 114
 115#include <linux/blkdev.h>
 116#include <linux/file.h>
 117#include <linux/dmapool.h>
 118#include <uapi/linux/lightnvm.h>
 119
 120enum {
 121        /* HW Responsibilities */
 122        NVM_RSP_L2P     = 1 << 0,
 123        NVM_RSP_ECC     = 1 << 1,
 124
 125        /* Physical Adressing Mode */
 126        NVM_ADDRMODE_LINEAR     = 0,
 127        NVM_ADDRMODE_CHANNEL    = 1,
 128
 129        /* Plane programming mode for LUN */
 130        NVM_PLANE_SINGLE        = 1,
 131        NVM_PLANE_DOUBLE        = 2,
 132        NVM_PLANE_QUAD          = 4,
 133
 134        /* Status codes */
 135        NVM_RSP_SUCCESS         = 0x0,
 136        NVM_RSP_NOT_CHANGEABLE  = 0x1,
 137        NVM_RSP_ERR_FAILWRITE   = 0x40ff,
 138        NVM_RSP_ERR_EMPTYPAGE   = 0x42ff,
 139        NVM_RSP_ERR_FAILECC     = 0x4281,
 140        NVM_RSP_ERR_FAILCRC     = 0x4004,
 141        NVM_RSP_WARN_HIGHECC    = 0x4700,
 142
 143        /* Device opcodes */
 144        NVM_OP_PWRITE           = 0x91,
 145        NVM_OP_PREAD            = 0x92,
 146        NVM_OP_ERASE            = 0x90,
 147
 148        /* PPA Command Flags */
 149        NVM_IO_SNGL_ACCESS      = 0x0,
 150        NVM_IO_DUAL_ACCESS      = 0x1,
 151        NVM_IO_QUAD_ACCESS      = 0x2,
 152
 153        /* NAND Access Modes */
 154        NVM_IO_SUSPEND          = 0x80,
 155        NVM_IO_SLC_MODE         = 0x100,
 156        NVM_IO_SCRAMBLE_ENABLE  = 0x200,
 157
 158        /* Block Types */
 159        NVM_BLK_T_FREE          = 0x0,
 160        NVM_BLK_T_BAD           = 0x1,
 161        NVM_BLK_T_GRWN_BAD      = 0x2,
 162        NVM_BLK_T_DEV           = 0x4,
 163        NVM_BLK_T_HOST          = 0x8,
 164
 165        /* Memory capabilities */
 166        NVM_ID_CAP_SLC          = 0x1,
 167        NVM_ID_CAP_CMD_SUSPEND  = 0x2,
 168        NVM_ID_CAP_SCRAMBLE     = 0x4,
 169        NVM_ID_CAP_ENCRYPT      = 0x8,
 170
 171        /* Memory types */
 172        NVM_ID_FMTYPE_SLC       = 0,
 173        NVM_ID_FMTYPE_MLC       = 1,
 174
 175        /* Device capabilities */
 176        NVM_ID_DCAP_BBLKMGMT    = 0x1,
 177        NVM_UD_DCAP_ECC         = 0x2,
 178};
 179
 180struct nvm_id_lp_mlc {
 181        u16     num_pairs;
 182        u8      pairs[886];
 183};
 184
 185struct nvm_id_lp_tbl {
 186        __u8    id[8];
 187        struct nvm_id_lp_mlc mlc;
 188};
 189
 190struct nvm_addrf_12 {
 191        u8      ch_len;
 192        u8      lun_len;
 193        u8      blk_len;
 194        u8      pg_len;
 195        u8      pln_len;
 196        u8      sec_len;
 197
 198        u8      ch_offset;
 199        u8      lun_offset;
 200        u8      blk_offset;
 201        u8      pg_offset;
 202        u8      pln_offset;
 203        u8      sec_offset;
 204
 205        u64     ch_mask;
 206        u64     lun_mask;
 207        u64     blk_mask;
 208        u64     pg_mask;
 209        u64     pln_mask;
 210        u64     sec_mask;
 211};
 212
 213struct nvm_addrf {
 214        u8      ch_len;
 215        u8      lun_len;
 216        u8      chk_len;
 217        u8      sec_len;
 218        u8      rsv_len[2];
 219
 220        u8      ch_offset;
 221        u8      lun_offset;
 222        u8      chk_offset;
 223        u8      sec_offset;
 224        u8      rsv_off[2];
 225
 226        u64     ch_mask;
 227        u64     lun_mask;
 228        u64     chk_mask;
 229        u64     sec_mask;
 230        u64     rsv_mask[2];
 231};
 232
 233enum {
 234        /* Chunk states */
 235        NVM_CHK_ST_FREE =       1 << 0,
 236        NVM_CHK_ST_CLOSED =     1 << 1,
 237        NVM_CHK_ST_OPEN =       1 << 2,
 238        NVM_CHK_ST_OFFLINE =    1 << 3,
 239
 240        /* Chunk types */
 241        NVM_CHK_TP_W_SEQ =      1 << 0,
 242        NVM_CHK_TP_W_RAN =      1 << 1,
 243        NVM_CHK_TP_SZ_SPEC =    1 << 4,
 244};
 245
 246/*
 247 * Note: The structure size is linked to nvme_nvm_chk_meta such that the same
 248 * buffer can be used when converting from little endian to cpu addressing.
 249 */
 250struct nvm_chk_meta {
 251        u8      state;
 252        u8      type;
 253        u8      wi;
 254        u8      rsvd[5];
 255        u64     slba;
 256        u64     cnlb;
 257        u64     wp;
 258};
 259
 260struct nvm_target {
 261        struct list_head list;
 262        struct nvm_tgt_dev *dev;
 263        struct nvm_tgt_type *type;
 264        struct gendisk *disk;
 265};
 266
 267#define ADDR_EMPTY (~0ULL)
 268
 269#define NVM_TARGET_DEFAULT_OP (101)
 270#define NVM_TARGET_MIN_OP (3)
 271#define NVM_TARGET_MAX_OP (80)
 272
 273#define NVM_VERSION_MAJOR 1
 274#define NVM_VERSION_MINOR 0
 275#define NVM_VERSION_PATCH 0
 276
 277#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
 278
 279struct nvm_rq;
 280typedef void (nvm_end_io_fn)(struct nvm_rq *);
 281
 282struct nvm_rq {
 283        struct nvm_tgt_dev *dev;
 284
 285        struct bio *bio;
 286
 287        union {
 288                struct ppa_addr ppa_addr;
 289                dma_addr_t dma_ppa_list;
 290        };
 291
 292        struct ppa_addr *ppa_list;
 293
 294        void *meta_list;
 295        dma_addr_t dma_meta_list;
 296
 297        nvm_end_io_fn *end_io;
 298
 299        uint8_t opcode;
 300        uint16_t nr_ppas;
 301        uint16_t flags;
 302
 303        u64 ppa_status; /* ppa media status */
 304        int error;
 305
 306        void *private;
 307};
 308
 309static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
 310{
 311        return pdu - sizeof(struct nvm_rq);
 312}
 313
 314static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
 315{
 316        return rqdata + 1;
 317}
 318
 319enum {
 320        NVM_BLK_ST_FREE =       0x1,    /* Free block */
 321        NVM_BLK_ST_TGT =        0x2,    /* Block in use by target */
 322        NVM_BLK_ST_BAD =        0x8,    /* Bad block */
 323};
 324
 325/* Instance geometry */
 326struct nvm_geo {
 327        /* device reported version */
 328        u8      major_ver_id;
 329        u8      minor_ver_id;
 330
 331        /* kernel short version */
 332        u8      version;
 333
 334        /* instance specific geometry */
 335        int num_ch;
 336        int num_lun;            /* per channel */
 337
 338        /* calculated values */
 339        int all_luns;           /* across channels */
 340        int all_chunks;         /* across channels */
 341
 342        int op;                 /* over-provision in instance */
 343
 344        sector_t total_secs;    /* across channels */
 345
 346        /* chunk geometry */
 347        u32     num_chk;        /* chunks per lun */
 348        u32     clba;           /* sectors per chunk */
 349        u16     csecs;          /* sector size */
 350        u16     sos;            /* out-of-band area size */
 351        bool    ext;            /* metadata in extended data buffer */
 352
 353        /* device write constrains */
 354        u32     ws_min;         /* minimum write size */
 355        u32     ws_opt;         /* optimal write size */
 356        u32     mw_cunits;      /* distance required for successful read */
 357        u32     maxoc;          /* maximum open chunks */
 358        u32     maxocpu;        /* maximum open chunks per parallel unit */
 359
 360        /* device capabilities */
 361        u32     mccap;
 362
 363        /* device timings */
 364        u32     trdt;           /* Avg. Tread (ns) */
 365        u32     trdm;           /* Max Tread (ns) */
 366        u32     tprt;           /* Avg. Tprog (ns) */
 367        u32     tprm;           /* Max Tprog (ns) */
 368        u32     tbet;           /* Avg. Terase (ns) */
 369        u32     tbem;           /* Max Terase (ns) */
 370
 371        /* generic address format */
 372        struct nvm_addrf addrf;
 373
 374        /* 1.2 compatibility */
 375        u8      vmnt;
 376        u32     cap;
 377        u32     dom;
 378
 379        u8      mtype;
 380        u8      fmtype;
 381
 382        u16     cpar;
 383        u32     mpos;
 384
 385        u8      num_pln;
 386        u8      pln_mode;
 387        u16     num_pg;
 388        u16     fpg_sz;
 389};
 390
 391/* sub-device structure */
 392struct nvm_tgt_dev {
 393        /* Device information */
 394        struct nvm_geo geo;
 395
 396        /* Base ppas for target LUNs */
 397        struct ppa_addr *luns;
 398
 399        struct request_queue *q;
 400
 401        struct nvm_dev *parent;
 402        void *map;
 403};
 404
 405struct nvm_dev {
 406        struct nvm_dev_ops *ops;
 407
 408        struct list_head devices;
 409
 410        /* Device information */
 411        struct nvm_geo geo;
 412
 413        unsigned long *lun_map;
 414        void *dma_pool;
 415
 416        /* Backend device */
 417        struct request_queue *q;
 418        char name[DISK_NAME_LEN];
 419        void *private_data;
 420
 421        void *rmap;
 422
 423        struct mutex mlock;
 424        spinlock_t lock;
 425
 426        /* target management */
 427        struct list_head area_list;
 428        struct list_head targets;
 429};
 430
 431static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
 432                                                  struct ppa_addr r)
 433{
 434        struct nvm_geo *geo = &dev->geo;
 435        struct ppa_addr l;
 436
 437        if (geo->version == NVM_OCSSD_SPEC_12) {
 438                struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
 439
 440                l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
 441                l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
 442                l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
 443                l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
 444                l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
 445                l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
 446        } else {
 447                struct nvm_addrf *lbaf = &geo->addrf;
 448
 449                l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
 450                l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
 451                l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
 452                l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
 453        }
 454
 455        return l;
 456}
 457
 458static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
 459                                                  struct ppa_addr r)
 460{
 461        struct nvm_geo *geo = &dev->geo;
 462        struct ppa_addr l;
 463
 464        l.ppa = 0;
 465
 466        if (geo->version == NVM_OCSSD_SPEC_12) {
 467                struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
 468
 469                l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
 470                l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
 471                l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
 472                l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
 473                l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
 474                l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
 475        } else {
 476                struct nvm_addrf *lbaf = &geo->addrf;
 477
 478                l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
 479                l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
 480                l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
 481                l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
 482        }
 483
 484        return l;
 485}
 486
 487typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
 488typedef sector_t (nvm_tgt_capacity_fn)(void *);
 489typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
 490                                int flags);
 491typedef void (nvm_tgt_exit_fn)(void *, bool);
 492typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
 493typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
 494
 495struct nvm_tgt_type {
 496        const char *name;
 497        unsigned int version[3];
 498
 499        /* target entry points */
 500        nvm_tgt_make_rq_fn *make_rq;
 501        nvm_tgt_capacity_fn *capacity;
 502
 503        /* module-specific init/teardown */
 504        nvm_tgt_init_fn *init;
 505        nvm_tgt_exit_fn *exit;
 506
 507        /* sysfs */
 508        nvm_tgt_sysfs_init_fn *sysfs_init;
 509        nvm_tgt_sysfs_exit_fn *sysfs_exit;
 510
 511        /* For internal use */
 512        struct list_head list;
 513        struct module *owner;
 514};
 515
 516extern int nvm_register_tgt_type(struct nvm_tgt_type *);
 517extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
 518
 519extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
 520extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);
 521
 522extern struct nvm_dev *nvm_alloc_dev(int);
 523extern int nvm_register(struct nvm_dev *);
 524extern void nvm_unregister(struct nvm_dev *);
 525
 526
 527extern int nvm_get_chunk_meta(struct nvm_tgt_dev *tgt_dev,
 528                              struct nvm_chk_meta *meta, struct ppa_addr ppa,
 529                              int nchks);
 530
 531extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *,
 532                              int, int);
 533extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
 534extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
 535extern void nvm_end_io(struct nvm_rq *);
 536extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int);
 537extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *);
 538
 539#else /* CONFIG_NVM */
 540struct nvm_dev_ops;
 541
 542static inline struct nvm_dev *nvm_alloc_dev(int node)
 543{
 544        return ERR_PTR(-EINVAL);
 545}
 546static inline int nvm_register(struct nvm_dev *dev)
 547{
 548        return -EINVAL;
 549}
 550static inline void nvm_unregister(struct nvm_dev *dev) {}
 551#endif /* CONFIG_NVM */
 552#endif /* LIGHTNVM.H */
 553