LXR linux/include/linux/stmmac.h

   1/*******************************************************************************
   2
   3  Header file for stmmac platform data
   4
   5  Copyright (C) 2009  STMicroelectronics Ltd
   6
   7  This program is free software; you can redistribute it and/or modify it
   8  under the terms and conditions of the GNU General Public License,
   9  version 2, as published by the Free Software Foundation.
  10
  11  This program is distributed in the hope it will be useful, but WITHOUT
  12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  more details.
  15
  16  You should have received a copy of the GNU General Public License along with
  17  this program; if not, write to the Free Software Foundation, Inc.,
  18  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20  The full GNU General Public License is included in this distribution in
  21  the file called "COPYING".
  22
  23  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24*******************************************************************************/
  25
  26#ifndef __STMMAC_PLATFORM_DATA
  27#define __STMMAC_PLATFORM_DATA
  28
  29#include <linux/platform_device.h>
  30
  31#define MTL_MAX_RX_QUEUES       8
  32#define MTL_MAX_TX_QUEUES       8
  33#define STMMAC_CH_MAX           8
  34
  35#define STMMAC_RX_COE_NONE      0
  36#define STMMAC_RX_COE_TYPE1     1
  37#define STMMAC_RX_COE_TYPE2     2
  38
  39/* Define the macros for CSR clock range parameters to be passed by
  40 * platform code.
  41 * This could also be configured at run time using CPU freq framework. */
  42
  43/* MDC Clock Selection define*/
  44#define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
  45#define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
  46#define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
  47#define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
  48#define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
  49#define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
  50
  51/* MTL algorithms identifiers */
  52#define MTL_TX_ALGORITHM_WRR    0x0
  53#define MTL_TX_ALGORITHM_WFQ    0x1
  54#define MTL_TX_ALGORITHM_DWRR   0x2
  55#define MTL_TX_ALGORITHM_SP     0x3
  56#define MTL_RX_ALGORITHM_SP     0x4
  57#define MTL_RX_ALGORITHM_WSP    0x5
  58
  59/* RX/TX Queue Mode */
  60#define MTL_QUEUE_AVB           0x0
  61#define MTL_QUEUE_DCB           0x1
  62
  63/* The MDC clock could be set higher than the IEEE 802.3
  64 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  65 * of value different than the above defined values. The resultant MDIO
  66 * clock frequency of 12.5 MHz is applicable for the interfacing chips
  67 * supporting higher MDC clocks.
  68 * The MDC clock selection macros need to be defined for MDC clock rate
  69 * of 12.5 MHz, corresponding to the following selection.
  70 */
  71#define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
  72#define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
  73#define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
  74#define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
  75#define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
  76#define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
  77#define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
  78#define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
  79
  80/* AXI DMA Burst length supported */
  81#define DMA_AXI_BLEN_4          (1 << 1)
  82#define DMA_AXI_BLEN_8          (1 << 2)
  83#define DMA_AXI_BLEN_16         (1 << 3)
  84#define DMA_AXI_BLEN_32         (1 << 4)
  85#define DMA_AXI_BLEN_64         (1 << 5)
  86#define DMA_AXI_BLEN_128        (1 << 6)
  87#define DMA_AXI_BLEN_256        (1 << 7)
  88#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  89                        | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  90                        | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  91
  92/* Platfrom data for platform device structure's platform_data field */
  93
  94struct stmmac_mdio_bus_data {
  95        unsigned int phy_mask;
  96        unsigned int has_xpcs;
  97        unsigned int xpcs_an_inband;
  98        int *irqs;
  99        int probed_phy_irq;
 100        bool needs_reset;
 101};
 102
 103struct stmmac_dma_cfg {
 104        int pbl;
 105        int txpbl;
 106        int rxpbl;
 107        bool pblx8;
 108        int fixed_burst;
 109        int mixed_burst;
 110        bool aal;
 111        bool eame;
 112        bool multi_msi_en;
 113        bool dche;
 114};
 115
 116#define AXI_BLEN        7
 117struct stmmac_axi {
 118        bool axi_lpi_en;
 119        bool axi_xit_frm;
 120        u32 axi_wr_osr_lmt;
 121        u32 axi_rd_osr_lmt;
 122        bool axi_kbbe;
 123        u32 axi_blen[AXI_BLEN];
 124        bool axi_fb;
 125        bool axi_mb;
 126        bool axi_rb;
 127};
 128
 129#define EST_GCL         1024
 130struct stmmac_est {
 131        int enable;
 132        u32 btr_offset[2];
 133        u32 btr[2];
 134        u32 ctr[2];
 135        u32 ter;
 136        u32 gcl_unaligned[EST_GCL];
 137        u32 gcl[EST_GCL];
 138        u32 gcl_size;
 139};
 140
 141struct stmmac_rxq_cfg {
 142        u8 mode_to_use;
 143        u32 chan;
 144        u8 pkt_route;
 145        bool use_prio;
 146        u32 prio;
 147};
 148
 149struct stmmac_txq_cfg {
 150        u32 weight;
 151        u8 mode_to_use;
 152        /* Credit Base Shaper parameters */
 153        u32 send_slope;
 154        u32 idle_slope;
 155        u32 high_credit;
 156        u32 low_credit;
 157        bool use_prio;
 158        u32 prio;
 159        int tbs_en;
 160};
 161
 162/* FPE link state */
 163enum stmmac_fpe_state {
 164        FPE_STATE_OFF = 0,
 165        FPE_STATE_CAPABLE = 1,
 166        FPE_STATE_ENTERING_ON = 2,
 167        FPE_STATE_ON = 3,
 168};
 169
 170/* FPE link-partner hand-shaking mPacket type */
 171enum stmmac_mpacket_type {
 172        MPACKET_VERIFY = 0,
 173        MPACKET_RESPONSE = 1,
 174};
 175
 176enum stmmac_fpe_task_state_t {
 177        __FPE_REMOVING,
 178        __FPE_TASK_SCHED,
 179};
 180
 181struct stmmac_fpe_cfg {
 182        bool enable;                            /* FPE enable */
 183        bool hs_enable;                         /* FPE handshake enable */
 184        enum stmmac_fpe_state lp_fpe_state;     /* Link Partner FPE state */
 185        enum stmmac_fpe_state lo_fpe_state;     /* Local station FPE state */
 186};
 187
 188struct plat_stmmacenet_data {
 189        int bus_id;
 190        int phy_addr;
 191        int interface;
 192        int phy_interface;
 193        struct stmmac_mdio_bus_data *mdio_bus_data;
 194        struct device_node *phy_node;
 195        struct device_node *phylink_node;
 196        struct device_node *mdio_node;
 197        struct stmmac_dma_cfg *dma_cfg;
 198        struct stmmac_est *est;
 199        struct stmmac_fpe_cfg *fpe_cfg;
 200        int clk_csr;
 201        int has_gmac;
 202        int enh_desc;
 203        int tx_coe;
 204        int rx_coe;
 205        int bugged_jumbo;
 206        int pmt;
 207        int force_sf_dma_mode;
 208        int force_thresh_dma_mode;
 209        int riwt_off;
 210        int max_speed;
 211        int maxmtu;
 212        int multicast_filter_bins;
 213        int unicast_filter_entries;
 214        int tx_fifo_size;
 215        int rx_fifo_size;
 216        u32 addr64;
 217        u32 rx_queues_to_use;
 218        u32 tx_queues_to_use;
 219        u8 rx_sched_algorithm;
 220        u8 tx_sched_algorithm;
 221        struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 222        struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 223        void (*fix_mac_speed)(void *priv, unsigned int speed);
 224        int (*serdes_powerup)(struct net_device *ndev, void *priv);
 225        void (*serdes_powerdown)(struct net_device *ndev, void *priv);
 226        void (*ptp_clk_freq_config)(void *priv);
 227        int (*init)(struct platform_device *pdev, void *priv);
 228        void (*exit)(struct platform_device *pdev, void *priv);
 229        struct mac_device_info *(*setup)(void *priv);
 230        int (*clks_config)(void *priv, bool enabled);
 231        int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
 232                           void *ctx);
 233        void *bsp_priv;
 234        struct clk *stmmac_clk;
 235        struct clk *pclk;
 236        struct clk *clk_ptp_ref;
 237        unsigned int clk_ptp_rate;
 238        unsigned int clk_ref_rate;
 239        s32 ptp_max_adj;
 240        struct reset_control *stmmac_rst;
 241        struct stmmac_axi *axi;
 242        int has_gmac4;
 243        bool has_sun8i;
 244        bool tso_en;
 245        int rss_en;
 246        int mac_port_sel_speed;
 247        bool en_tx_lpi_clockgating;
 248        int has_xgmac;
 249        bool vlan_fail_q_en;
 250        u8 vlan_fail_q;
 251        unsigned int eee_usecs_rate;
 252        struct pci_dev *pdev;
 253        bool has_crossts;
 254        int int_snapshot_num;
 255        int ext_snapshot_num;
 256        bool ext_snapshot_en;
 257        bool multi_msi_en;
 258        int msi_mac_vec;
 259        int msi_wol_vec;
 260        int msi_lpi_vec;
 261        int msi_sfty_ce_vec;
 262        int msi_sfty_ue_vec;
 263        int msi_rx_base_vec;
 264        int msi_tx_base_vec;
 265};
 266#endif
 267