1/* 2 * Copyright (C) 2009 Texas Instruments Inc 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * vpss - video processing subsystem module header file. 15 * 16 * Include this header file if a driver needs to configure vpss system 17 * module. It exports a set of library functions for video drivers to 18 * configure vpss system module functions such as clock enable/disable, 19 * vpss interrupt mux to arm, and other common vpss system module 20 * functions. 21 */ 22#ifndef _VPSS_H 23#define _VPSS_H 24 25/* selector for ccdc input selection on DM355 */ 26enum vpss_ccdc_source_sel { 27 VPSS_CCDCIN, 28 VPSS_HSSIIN, 29 VPSS_PGLPBK, /* for DM365 only */ 30 VPSS_CCDCPG /* for DM365 only */ 31}; 32 33struct vpss_sync_pol { 34 unsigned int ccdpg_hdpol:1; 35 unsigned int ccdpg_vdpol:1; 36}; 37 38struct vpss_pg_frame_size { 39 short hlpfr; 40 short pplen; 41}; 42 43/* Used for enable/disable VPSS Clock */ 44enum vpss_clock_sel { 45 /* DM355/DM365 */ 46 VPSS_CCDC_CLOCK, 47 VPSS_IPIPE_CLOCK, 48 VPSS_H3A_CLOCK, 49 VPSS_CFALD_CLOCK, 50 /* 51 * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api 52 * following applies:- 53 * en = 0 selects ENC_CLK 54 * en = 1 selects ENC_CLK/2 55 */ 56 VPSS_VENC_CLOCK_SEL, 57 VPSS_VPBE_CLOCK, 58 /* DM365 only clocks */ 59 VPSS_IPIPEIF_CLOCK, 60 VPSS_RSZ_CLOCK, 61 VPSS_BL_CLOCK, 62 /* 63 * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api 64 * following applies:- 65 * en = 0 disable internal PCLK 66 * en = 1 enables internal PCLK 67 */ 68 VPSS_PCLK_INTERNAL, 69 /* 70 * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api 71 * following applies:- 72 * en = 0 enables MMR clock 73 * en = 1 enables VPSS clock 74 */ 75 VPSS_PSYNC_CLOCK_SEL, 76 VPSS_LDC_CLOCK_SEL, 77 VPSS_OSD_CLOCK_SEL, 78 VPSS_FDIF_CLOCK, 79 VPSS_LDC_CLOCK 80}; 81 82/* select input to ccdc on dm355 */ 83int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel); 84/* enable/disable a vpss clock, 0 - success, -1 - failure */ 85int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en); 86/* set sync polarity, only for DM365*/ 87void dm365_vpss_set_sync_pol(struct vpss_sync_pol); 88/* set the PG_FRAME_SIZE register, only for DM365 */ 89void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size); 90 91/* wbl reset for dm644x */ 92enum vpss_wbl_sel { 93 VPSS_PCR_AEW_WBL_0 = 16, 94 VPSS_PCR_AF_WBL_0, 95 VPSS_PCR_RSZ4_WBL_0, 96 VPSS_PCR_RSZ3_WBL_0, 97 VPSS_PCR_RSZ2_WBL_0, 98 VPSS_PCR_RSZ1_WBL_0, 99 VPSS_PCR_PREV_WBL_0, 100 VPSS_PCR_CCDC_WBL_O, 101}; 102/* clear wbl overflow flag for DM6446 */ 103int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel); 104 105/* set sync polarity*/ 106void vpss_set_sync_pol(struct vpss_sync_pol sync); 107/* set the PG_FRAME_SIZE register */ 108void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size); 109/* 110 * vpss_check_and_clear_interrupt - check and clear interrupt 111 * @irq - common enumerator for IRQ 112 * 113 * Following return values used:- 114 * 0 - interrupt occurred and cleared 115 * 1 - interrupt not occurred 116 * 2 - interrupt status not available 117 */ 118int vpss_dma_complete_interrupt(void); 119 120#endif 121