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9#include <linux/module.h>
10#include <linux/delay.h>
11#include <linux/dmi.h>
12#include <linux/init.h>
13#include <linux/i2c.h>
14#include <linux/regmap.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/acpi.h>
18#include <linux/math64.h>
19#include <linux/semaphore.h>
20
21#include <sound/initval.h>
22#include <sound/tlv.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28
29#include "nau8824.h"
30
31#define NAU8824_JD_ACTIVE_HIGH BIT(0)
32#define NAU8824_MONO_SPEAKER BIT(1)
33
34static int nau8824_quirk;
35static int quirk_override = -1;
36module_param_named(quirk, quirk_override, uint, 0444);
37MODULE_PARM_DESC(quirk, "Board-specific quirk override");
38
39static int nau8824_config_sysclk(struct nau8824 *nau8824,
40 int clk_id, unsigned int freq);
41static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
42
43
44#define DMIC_CLK 3072000
45
46
47#define HEADSET_SARADC_THD 0x80
48
49
50#define NAU_FREF_MAX 13500000
51#define NAU_FVCO_MAX 100000000
52#define NAU_FVCO_MIN 90000000
53
54
55static const struct nau8824_fll_attr mclk_src_scaling[] = {
56 { 1, 0x0 },
57 { 2, 0x2 },
58 { 4, 0x3 },
59 { 8, 0x4 },
60 { 16, 0x5 },
61 { 32, 0x6 },
62 { 3, 0x7 },
63 { 6, 0xa },
64 { 12, 0xb },
65 { 24, 0xc },
66};
67
68
69static const struct nau8824_fll_attr fll_ratio[] = {
70 { 512000, 0x01 },
71 { 256000, 0x02 },
72 { 128000, 0x04 },
73 { 64000, 0x08 },
74 { 32000, 0x10 },
75 { 8000, 0x20 },
76 { 4000, 0x40 },
77};
78
79static const struct nau8824_fll_attr fll_pre_scalar[] = {
80 { 1, 0x0 },
81 { 2, 0x1 },
82 { 4, 0x2 },
83 { 8, 0x3 },
84};
85
86
87#define CLK_DA_AD_MAX 6144000
88
89
90static const struct nau8824_osr_attr osr_dac_sel[] = {
91 { 64, 2 },
92 { 256, 0 },
93 { 128, 1 },
94 { 0, 0 },
95 { 32, 3 },
96};
97
98static const struct nau8824_osr_attr osr_adc_sel[] = {
99 { 32, 3 },
100 { 64, 2 },
101 { 128, 1 },
102 { 256, 0 },
103};
104
105static const struct reg_default nau8824_reg_defaults[] = {
106 { NAU8824_REG_ENA_CTRL, 0x0000 },
107 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
108 { NAU8824_REG_CLK_DIVIDER, 0x0000 },
109 { NAU8824_REG_FLL1, 0x0000 },
110 { NAU8824_REG_FLL2, 0x3126 },
111 { NAU8824_REG_FLL3, 0x0008 },
112 { NAU8824_REG_FLL4, 0x0010 },
113 { NAU8824_REG_FLL5, 0xC000 },
114 { NAU8824_REG_FLL6, 0x6000 },
115 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
116 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
117 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
118 { NAU8824_REG_IRQ, 0x0000 },
119 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
120 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
121 { NAU8824_REG_SAR_ADC, 0x0015 },
122 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
123 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
124 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
125 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
126 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
127 { NAU8824_REG_GPIO_SEL, 0x0000 },
128 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
129 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
130 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
131 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
132 { NAU8824_REG_TDM_CTRL, 0x0000 },
133 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
134 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
135 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
136 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
137 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
138 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
139 { NAU8824_REG_EQ1_LOW, 0x112C },
140 { NAU8824_REG_EQ2_EQ3, 0x2C2C },
141 { NAU8824_REG_EQ4_EQ5, 0x2C2C },
142 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
143 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
144 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
145 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
146 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
147 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
148 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
149 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
150 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
151 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
152 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
153 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
154 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
155 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
156 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
157 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
158 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
159 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
160 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
161 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
162 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
163 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
164 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
165 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
166 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
167 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
168 { NAU8824_REG_MODE, 0x0000 },
169 { NAU8824_REG_MODE1, 0x0000 },
170 { NAU8824_REG_MODE2, 0x0000 },
171 { NAU8824_REG_CLASSG, 0x0000 },
172 { NAU8824_REG_OTP_EFUSE, 0x0000 },
173 { NAU8824_REG_OTPDOUT_1, 0x0000 },
174 { NAU8824_REG_OTPDOUT_2, 0x0000 },
175 { NAU8824_REG_MISC_CTRL, 0x0000 },
176 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
177 { NAU8824_REG_TEST_MODE, 0x0000 },
178 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
179 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
180 { NAU8824_REG_BIAS_ADJ, 0x0000 },
181 { NAU8824_REG_PGA_GAIN, 0x0000 },
182 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
183 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
184 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
185 { NAU8824_REG_ENABLE_LO, 0x0000 },
186 { NAU8824_REG_GAIN_LO, 0x0000 },
187 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
188 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
189 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
190 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
191 { NAU8824_REG_RDAC, 0x0008 },
192 { NAU8824_REG_MIC_BIAS, 0x0006 },
193 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
194 { NAU8824_REG_BOOST, 0x0000 },
195 { NAU8824_REG_FEPGA, 0x0000 },
196 { NAU8824_REG_FEPGA_II, 0x0000 },
197 { NAU8824_REG_FEPGA_SE, 0x0000 },
198 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
199 { NAU8824_REG_ATT_PORT0, 0x0000 },
200 { NAU8824_REG_ATT_PORT1, 0x0000 },
201 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
202 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
203 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
204};
205
206static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
207{
208 int ret;
209
210 if (timeout) {
211 ret = down_timeout(&nau8824->jd_sem, timeout);
212 if (ret < 0)
213 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
214 } else {
215 ret = down_interruptible(&nau8824->jd_sem);
216 if (ret < 0)
217 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
218 }
219
220 return ret;
221}
222
223static inline void nau8824_sema_release(struct nau8824 *nau8824)
224{
225 up(&nau8824->jd_sem);
226}
227
228static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
229{
230 switch (reg) {
231 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
232 case NAU8824_REG_JACK_DET_CTRL:
233 case NAU8824_REG_INTERRUPT_SETTING_1:
234 case NAU8824_REG_IRQ:
235 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
236 case NAU8824_REG_GPIO_SEL:
237 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
238 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
239 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
240 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
241 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
242 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
243 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
244 case NAU8824_REG_I2C_TIMEOUT:
245 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
246 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
247 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
248 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
249 return true;
250 default:
251 return false;
252 }
253
254}
255
256static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
257{
258 switch (reg) {
259 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
260 case NAU8824_REG_JACK_DET_CTRL:
261 case NAU8824_REG_INTERRUPT_SETTING_1:
262 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
263 case NAU8824_REG_GPIO_SEL:
264 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
265 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
266 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
267 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
268 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
269 case NAU8824_REG_DRC_SLOPE_ADC_CH01:
270 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
271 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
272 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
273 case NAU8824_REG_DRC_SLOPE_ADC_CH23:
274 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
275 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
276 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
277 case NAU8824_REG_I2C_TIMEOUT:
278 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
279 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
280 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
281 return true;
282 default:
283 return false;
284 }
285}
286
287static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
288{
289 switch (reg) {
290 case NAU8824_REG_RESET:
291 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
292 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
293 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
294 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
295 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
296 case NAU8824_REG_CHARGE_PUMP_INPUT:
297 return true;
298 default:
299 return false;
300 }
301}
302
303static const char * const nau8824_companding[] = {
304 "Off", "NC", "u-law", "A-law" };
305
306static const struct soc_enum nau8824_companding_adc_enum =
307 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
308 ARRAY_SIZE(nau8824_companding), nau8824_companding);
309
310static const struct soc_enum nau8824_companding_dac_enum =
311 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
312 ARRAY_SIZE(nau8824_companding), nau8824_companding);
313
314static const char * const nau8824_adc_decimation[] = {
315 "32", "64", "128", "256" };
316
317static const struct soc_enum nau8824_adc_decimation_enum =
318 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
319 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
320
321static const char * const nau8824_dac_oversampl[] = {
322 "64", "256", "128", "", "32" };
323
324static const struct soc_enum nau8824_dac_oversampl_enum =
325 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
326 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
327
328static const char * const nau8824_input_channel[] = {
329 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
330
331static const struct soc_enum nau8824_adc_ch0_enum =
332 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
333 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
334
335static const struct soc_enum nau8824_adc_ch1_enum =
336 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
337 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
338
339static const struct soc_enum nau8824_adc_ch2_enum =
340 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
341 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
342
343static const struct soc_enum nau8824_adc_ch3_enum =
344 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
345 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
346
347static const char * const nau8824_tdm_slot[] = {
348 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
349
350static const struct soc_enum nau8824_dac_left_sel_enum =
351 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
352 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
353
354static const struct soc_enum nau8824_dac_right_sel_enum =
355 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
356 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
357
358static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
359static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
360static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
361static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
362
363static const struct snd_kcontrol_new nau8824_snd_controls[] = {
364 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
365 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
366
367 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
368 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
369
370 SOC_SINGLE_TLV("Speaker Right DACR Volume",
371 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
372 SOC_SINGLE_TLV("Speaker Left DACL Volume",
373 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
374 SOC_SINGLE_TLV("Speaker Left DACR Volume",
375 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
376 SOC_SINGLE_TLV("Speaker Right DACL Volume",
377 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
378
379 SOC_SINGLE_TLV("Headphone Right DACR Volume",
380 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
381 SOC_SINGLE_TLV("Headphone Left DACL Volume",
382 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
383 SOC_SINGLE_TLV("Headphone Right DACL Volume",
384 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
385 SOC_SINGLE_TLV("Headphone Left DACR Volume",
386 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
387
388 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
389 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
390 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
391 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
392
393 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
394 0, 0x164, 0, dmic_vol_tlv),
395 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
396 0, 0x164, 0, dmic_vol_tlv),
397 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
398 0, 0x164, 0, dmic_vol_tlv),
399 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
400 0, 0x164, 0, dmic_vol_tlv),
401
402 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
403 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
404 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
405 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
406
407 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
408 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
409 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
410 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
411
412 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
413 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
414
415 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
416 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
417
418 SOC_SINGLE("THD for key media",
419 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
420 SOC_SINGLE("THD for key voice command",
421 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
422 SOC_SINGLE("THD for key volume up",
423 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
424 SOC_SINGLE("THD for key volume down",
425 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
426};
427
428static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
429 struct snd_kcontrol *kcontrol, int event)
430{
431 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
432 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
433
434 switch (event) {
435 case SND_SOC_DAPM_PRE_PMU:
436
437 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
438 NAU8824_TEST_DAC_EN, 0);
439 break;
440 case SND_SOC_DAPM_POST_PMD:
441 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
442 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
443 break;
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449}
450
451static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
452 struct snd_kcontrol *kcontrol, int event)
453{
454 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
455 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
456
457 switch (event) {
458 case SND_SOC_DAPM_PRE_PMU:
459 regmap_update_bits(nau8824->regmap,
460 NAU8824_REG_ANALOG_CONTROL_2,
461 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
462 break;
463 case SND_SOC_DAPM_POST_PMD:
464 regmap_update_bits(nau8824->regmap,
465 NAU8824_REG_ANALOG_CONTROL_2,
466 NAU8824_CLASSD_CLAMP_DIS, 0);
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 return 0;
473}
474
475static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event)
477{
478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
479 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
480
481 switch (event) {
482 case SND_SOC_DAPM_POST_PMU:
483
484 msleep(10);
485 regmap_update_bits(nau8824->regmap,
486 NAU8824_REG_CHARGE_PUMP_CONTROL,
487 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
488 break;
489 case SND_SOC_DAPM_PRE_PMD:
490 regmap_update_bits(nau8824->regmap,
491 NAU8824_REG_CHARGE_PUMP_CONTROL,
492 NAU8824_JAMNODCLOW, 0);
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499}
500
501static int system_clock_control(struct snd_soc_dapm_widget *w,
502 struct snd_kcontrol *k, int event)
503{
504 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
505 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
506 struct regmap *regmap = nau8824->regmap;
507 unsigned int value;
508 bool clk_fll, error;
509
510 if (SND_SOC_DAPM_EVENT_OFF(event)) {
511 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
512
513
514
515
516
517 if (nau8824_is_jack_inserted(nau8824)) {
518 nau8824_config_sysclk(nau8824,
519 NAU8824_CLK_INTERNAL, 0);
520 } else {
521 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
522 }
523 } else {
524 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
525
526
527
528 regmap_read(regmap, NAU8824_REG_FLL1, &value);
529 clk_fll = value & NAU8824_FLL_RATIO_MASK;
530
531 regmap_read(regmap, NAU8824_REG_FLL6, &value);
532 error = value & NAU8824_DCO_EN;
533 if (!error) {
534
535 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
536 if (clk_fll)
537 error = !(value & NAU8824_CLK_SRC_VCO);
538 else
539 error = value & NAU8824_CLK_SRC_VCO;
540 }
541
542 if (error) {
543 if (clk_fll) {
544 regmap_update_bits(regmap,
545 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
546 regmap_update_bits(regmap,
547 NAU8824_REG_CLK_DIVIDER,
548 NAU8824_CLK_SRC_MASK,
549 NAU8824_CLK_SRC_VCO);
550 } else {
551 nau8824_config_sysclk(nau8824,
552 NAU8824_CLK_MCLK, 0);
553 }
554 }
555 }
556
557 return 0;
558}
559
560static int dmic_clock_control(struct snd_soc_dapm_widget *w,
561 struct snd_kcontrol *k, int event)
562{
563 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
564 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
565 int src;
566
567
568
569
570
571 for (src = 0; src < 5; src++) {
572 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
573 break;
574 }
575 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
576 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
577 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
578
579 return 0;
580}
581
582static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
583 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
584 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
585
586static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
587 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
588 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
589
590static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
591 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
592 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
593
594static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
595 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
596 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
597
598static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
599 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
600 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
601 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
602 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
603};
604
605static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
606 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
607 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
608 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
609 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
610};
611
612static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
613 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
614 NAU8824_DACR_HPL_EN_SFT, 1, 0),
615 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
616 NAU8824_DACL_HPL_EN_SFT, 1, 0),
617};
618
619static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
620 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
621 NAU8824_DACL_HPR_EN_SFT, 1, 0),
622 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
623 NAU8824_DACR_HPR_EN_SFT, 1, 0),
624};
625
626static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
627
628static SOC_ENUM_SINGLE_DECL(
629 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
630 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
631
632static SOC_ENUM_SINGLE_DECL(
633 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
634 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
635
636static const struct snd_kcontrol_new nau8824_dacl_mux =
637 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
638
639static const struct snd_kcontrol_new nau8824_dacr_mux =
640 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
641
642
643static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
644 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
645 system_clock_control, SND_SOC_DAPM_POST_PMD |
646 SND_SOC_DAPM_POST_PMU),
647
648 SND_SOC_DAPM_INPUT("HSMIC1"),
649 SND_SOC_DAPM_INPUT("HSMIC2"),
650 SND_SOC_DAPM_INPUT("MIC1"),
651 SND_SOC_DAPM_INPUT("MIC2"),
652 SND_SOC_DAPM_INPUT("DMIC1"),
653 SND_SOC_DAPM_INPUT("DMIC2"),
654 SND_SOC_DAPM_INPUT("DMIC3"),
655 SND_SOC_DAPM_INPUT("DMIC4"),
656
657 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
658 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
659 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
660 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
661 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
662 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
663 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
664 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
665 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
666 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
667
668 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
669 0, 0, &nau8824_adc_ch0_dmic),
670 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
671 0, 0, &nau8824_adc_ch1_dmic),
672 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
673 0, 0, &nau8824_adc_ch2_dmic),
674 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
675 0, 0, &nau8824_adc_ch3_dmic),
676
677 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
678 12, 0, nau8824_adc_left_mixer,
679 ARRAY_SIZE(nau8824_adc_left_mixer)),
680 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
681 13, 0, nau8824_adc_right_mixer,
682 ARRAY_SIZE(nau8824_adc_right_mixer)),
683
684 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
685 NAU8824_ADCL_EN_SFT, 0),
686 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
687 NAU8824_ADCR_EN_SFT, 0),
688
689 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
690 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
691
692 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
693 NAU8824_DACL_EN_SFT, 0),
694 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
695 NAU8824_DACL_CLK_SFT, 0, NULL, 0),
696 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
697 NAU8824_DACR_EN_SFT, 0),
698 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
699 NAU8824_DACR_CLK_SFT, 0, NULL, 0),
700
701 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
702 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
703
704 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
705 8, 1, nau8824_output_dac_event,
706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
707 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
708 9, 1, nau8824_output_dac_event,
709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
710
711 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
712 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
714
715 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
716 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
717 ARRAY_SIZE(nau8824_hp_left_mixer)),
718 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
719 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
720 ARRAY_SIZE(nau8824_hp_right_mixer)),
721 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
722 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
723 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
724 SND_SOC_DAPM_PGA("Output Driver L",
725 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
726 SND_SOC_DAPM_PGA("Output Driver R",
727 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
728 SND_SOC_DAPM_PGA("Main Driver L",
729 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
730 SND_SOC_DAPM_PGA("Main Driver R",
731 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
732 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
733 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
734 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
735 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
736
737 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
738 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
739 SND_SOC_DAPM_OUTPUT("HPOL"),
740 SND_SOC_DAPM_OUTPUT("HPOR"),
741};
742
743static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
744 {"DMIC1 Enable", "Switch", "DMIC1"},
745 {"DMIC2 Enable", "Switch", "DMIC2"},
746 {"DMIC3 Enable", "Switch", "DMIC3"},
747 {"DMIC4 Enable", "Switch", "DMIC4"},
748
749 {"DMIC1", NULL, "DMIC12 Power"},
750 {"DMIC2", NULL, "DMIC12 Power"},
751 {"DMIC3", NULL, "DMIC34 Power"},
752 {"DMIC4", NULL, "DMIC34 Power"},
753 {"DMIC12 Power", NULL, "DMIC Clock"},
754 {"DMIC34 Power", NULL, "DMIC Clock"},
755
756 {"Left ADC", "MIC Switch", "MIC1"},
757 {"Left ADC", "HSMIC Switch", "HSMIC1"},
758 {"Right ADC", "MIC Switch", "MIC2"},
759 {"Right ADC", "HSMIC Switch", "HSMIC2"},
760
761 {"ADCL", NULL, "Left ADC"},
762 {"ADCR", NULL, "Right ADC"},
763
764 {"AIFTX", NULL, "MICBIAS"},
765 {"AIFTX", NULL, "ADCL"},
766 {"AIFTX", NULL, "ADCR"},
767 {"AIFTX", NULL, "DMIC1 Enable"},
768 {"AIFTX", NULL, "DMIC2 Enable"},
769 {"AIFTX", NULL, "DMIC3 Enable"},
770 {"AIFTX", NULL, "DMIC4 Enable"},
771
772 {"AIFTX", NULL, "System Clock"},
773 {"AIFRX", NULL, "System Clock"},
774
775 {"DACL", NULL, "AIFRX"},
776 {"DACL", NULL, "DACL Clock"},
777 {"DACR", NULL, "AIFRX"},
778 {"DACR", NULL, "DACR Clock"},
779
780 {"DACL Mux", "DACL", "DACL"},
781 {"DACL Mux", "DACR", "DACR"},
782 {"DACR Mux", "DACL", "DACL"},
783 {"DACR Mux", "DACR", "DACR"},
784
785 {"Output DACL", NULL, "DACL Mux"},
786 {"Output DACR", NULL, "DACR Mux"},
787
788 {"ClassD", NULL, "Output DACL"},
789 {"ClassD", NULL, "Output DACR"},
790
791 {"Left Headphone", "DAC Left Switch", "Output DACL"},
792 {"Left Headphone", "DAC Right Switch", "Output DACR"},
793 {"Right Headphone", "DAC Left Switch", "Output DACL"},
794 {"Right Headphone", "DAC Right Switch", "Output DACR"},
795
796 {"Charge Pump", NULL, "Left Headphone"},
797 {"Charge Pump", NULL, "Right Headphone"},
798 {"Output Driver L", NULL, "Charge Pump"},
799 {"Output Driver R", NULL, "Charge Pump"},
800 {"Main Driver L", NULL, "Output Driver L"},
801 {"Main Driver R", NULL, "Output Driver R"},
802 {"Class G", NULL, "Main Driver L"},
803 {"Class G", NULL, "Main Driver R"},
804 {"HP Boost Driver", NULL, "Class G"},
805
806 {"SPKOUTL", NULL, "ClassD"},
807 {"SPKOUTR", NULL, "ClassD"},
808 {"HPOL", NULL, "HP Boost Driver"},
809 {"HPOR", NULL, "HP Boost Driver"},
810};
811
812static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
813{
814 struct snd_soc_jack *jack = nau8824->jack;
815 bool insert = false;
816
817 if (nau8824->irq && jack)
818 insert = jack->status & SND_JACK_HEADPHONE;
819
820 return insert;
821}
822
823static void nau8824_int_status_clear_all(struct regmap *regmap)
824{
825 int active_irq, clear_irq, i;
826
827
828
829
830 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
831 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
832 clear_irq = (0x1 << i);
833 if (active_irq & clear_irq)
834 regmap_write(regmap,
835 NAU8824_REG_CLEAR_INT_REG, clear_irq);
836 }
837}
838
839static void nau8824_eject_jack(struct nau8824 *nau8824)
840{
841 struct snd_soc_dapm_context *dapm = nau8824->dapm;
842 struct regmap *regmap = nau8824->regmap;
843
844
845 nau8824_int_status_clear_all(regmap);
846
847 snd_soc_dapm_disable_pin(dapm, "SAR");
848 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
849 snd_soc_dapm_sync(dapm);
850
851
852
853
854 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
855 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
856 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
857 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
858 NAU8824_IRQ_EJECT_DIS);
859 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
860 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
861 NAU8824_IRQ_INSERT_EN);
862 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
863 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
864
865
866 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
867 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
868}
869
870static void nau8824_jdet_work(struct work_struct *work)
871{
872 struct nau8824 *nau8824 = container_of(
873 work, struct nau8824, jdet_work);
874 struct snd_soc_dapm_context *dapm = nau8824->dapm;
875 struct regmap *regmap = nau8824->regmap;
876 int adc_value, event = 0, event_mask = 0;
877
878 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
879 snd_soc_dapm_force_enable_pin(dapm, "SAR");
880 snd_soc_dapm_sync(dapm);
881
882 msleep(100);
883
884 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
885 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
886 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
887 if (adc_value < HEADSET_SARADC_THD) {
888 event |= SND_JACK_HEADPHONE;
889
890 snd_soc_dapm_disable_pin(dapm, "SAR");
891 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
892 snd_soc_dapm_sync(dapm);
893 } else {
894 event |= SND_JACK_HEADSET;
895 }
896 event_mask |= SND_JACK_HEADSET;
897 snd_soc_jack_report(nau8824->jack, event, event_mask);
898
899
900 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
901 NAU8824_IRQ_KEY_RELEASE_DIS |
902 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
903
904 nau8824_sema_release(nau8824);
905}
906
907static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
908{
909 struct regmap *regmap = nau8824->regmap;
910
911
912 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
913 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
914 NAU8824_IRQ_EJECT_EN);
915 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
916 NAU8824_IRQ_EJECT_DIS, 0);
917
918 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
919 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
920 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
921 NAU8824_JD_SLEEP_MODE, 0);
922}
923
924static int nau8824_button_decode(int value)
925{
926 int buttons = 0;
927
928
929
930
931 if (value & BIT(0))
932 buttons |= SND_JACK_BTN_0;
933 if (value & BIT(1))
934 buttons |= SND_JACK_BTN_1;
935 if (value & BIT(2))
936 buttons |= SND_JACK_BTN_2;
937 if (value & BIT(3))
938 buttons |= SND_JACK_BTN_3;
939 if (value & BIT(4))
940 buttons |= SND_JACK_BTN_4;
941 if (value & BIT(5))
942 buttons |= SND_JACK_BTN_5;
943
944 return buttons;
945}
946
947#define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
948 SND_JACK_BTN_2 | SND_JACK_BTN_3)
949
950static irqreturn_t nau8824_interrupt(int irq, void *data)
951{
952 struct nau8824 *nau8824 = (struct nau8824 *)data;
953 struct regmap *regmap = nau8824->regmap;
954 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
955
956 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
957 dev_err(nau8824->dev, "failed to read irq status\n");
958 return IRQ_NONE;
959 }
960 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
961
962 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
963 nau8824_eject_jack(nau8824);
964 event_mask |= SND_JACK_HEADSET;
965 clear_irq = NAU8824_JACK_EJECTION_DETECTED;
966
967
968
969 nau8824_sema_release(nau8824);
970 cancel_work_sync(&nau8824->jdet_work);
971 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
972 int key_status, button_pressed;
973
974 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
975 &key_status);
976
977
978 button_pressed = nau8824_button_decode(key_status);
979
980 event |= button_pressed;
981 dev_dbg(nau8824->dev, "button %x pressed\n", event);
982 event_mask |= NAU8824_BUTTONS;
983 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
984 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
985 event_mask = NAU8824_BUTTONS;
986 clear_irq = NAU8824_KEY_RELEASE_IRQ;
987 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
988
989 regmap_update_bits(regmap,
990 NAU8824_REG_INTERRUPT_SETTING,
991 NAU8824_IRQ_INSERT_DIS,
992 NAU8824_IRQ_INSERT_DIS);
993 regmap_update_bits(regmap,
994 NAU8824_REG_INTERRUPT_SETTING_1,
995 NAU8824_IRQ_INSERT_EN, 0);
996
997 cancel_work_sync(&nau8824->jdet_work);
998 schedule_work(&nau8824->jdet_work);
999
1000
1001
1002
1003 nau8824_setup_auto_irq(nau8824);
1004 }
1005
1006 if (!clear_irq)
1007 clear_irq = active_irq;
1008
1009 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
1010
1011 if (event_mask)
1012 snd_soc_jack_report(nau8824->jack, event, event_mask);
1013
1014 return IRQ_HANDLED;
1015}
1016
1017static int nau8824_clock_check(struct nau8824 *nau8824,
1018 int stream, int rate, int osr)
1019{
1020 int osrate;
1021
1022 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1023 if (osr >= ARRAY_SIZE(osr_dac_sel))
1024 return -EINVAL;
1025 osrate = osr_dac_sel[osr].osr;
1026 } else {
1027 if (osr >= ARRAY_SIZE(osr_adc_sel))
1028 return -EINVAL;
1029 osrate = osr_adc_sel[osr].osr;
1030 }
1031
1032 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1033 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1034 return -EINVAL;
1035 }
1036
1037 return 0;
1038}
1039
1040static int nau8824_hw_params(struct snd_pcm_substream *substream,
1041 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1042{
1043 struct snd_soc_component *component = dai->component;
1044 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1045 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1046
1047 nau8824_sema_acquire(nau8824, HZ);
1048
1049
1050
1051
1052
1053
1054
1055 nau8824->fs = params_rate(params);
1056 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1057 regmap_read(nau8824->regmap,
1058 NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
1059 osr &= NAU8824_DAC_OVERSAMPLE_MASK;
1060 if (nau8824_clock_check(nau8824, substream->stream,
1061 nau8824->fs, osr))
1062 return -EINVAL;
1063 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1064 NAU8824_CLK_DAC_SRC_MASK,
1065 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT);
1066 } else {
1067 regmap_read(nau8824->regmap,
1068 NAU8824_REG_ADC_FILTER_CTRL, &osr);
1069 osr &= NAU8824_ADC_SYNC_DOWN_MASK;
1070 if (nau8824_clock_check(nau8824, substream->stream,
1071 nau8824->fs, osr))
1072 return -EINVAL;
1073 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1074 NAU8824_CLK_ADC_SRC_MASK,
1075 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT);
1076 }
1077
1078
1079 regmap_read(nau8824->regmap,
1080 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
1081 if (ctrl_val & NAU8824_I2S_MS_MASTER) {
1082
1083 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
1084 if (bclk_fs <= 32)
1085 bclk_div = 0x3;
1086 else if (bclk_fs <= 64)
1087 bclk_div = 0x2;
1088 else if (bclk_fs <= 128)
1089 bclk_div = 0x1;
1090 else if (bclk_fs <= 256)
1091 bclk_div = 0;
1092 else
1093 return -EINVAL;
1094 regmap_update_bits(nau8824->regmap,
1095 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1096 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
1097 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
1098 }
1099
1100 switch (params_width(params)) {
1101 case 16:
1102 val_len |= NAU8824_I2S_DL_16;
1103 break;
1104 case 20:
1105 val_len |= NAU8824_I2S_DL_20;
1106 break;
1107 case 24:
1108 val_len |= NAU8824_I2S_DL_24;
1109 break;
1110 case 32:
1111 val_len |= NAU8824_I2S_DL_32;
1112 break;
1113 default:
1114 return -EINVAL;
1115 }
1116
1117 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1118 NAU8824_I2S_DL_MASK, val_len);
1119
1120 nau8824_sema_release(nau8824);
1121
1122 return 0;
1123}
1124
1125static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1126{
1127 struct snd_soc_component *component = dai->component;
1128 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1129 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1130
1131 nau8824_sema_acquire(nau8824, HZ);
1132
1133 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1134 case SND_SOC_DAIFMT_CBM_CFM:
1135 ctrl2_val |= NAU8824_I2S_MS_MASTER;
1136 break;
1137 case SND_SOC_DAIFMT_CBS_CFS:
1138 break;
1139 default:
1140 return -EINVAL;
1141 }
1142
1143 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1144 case SND_SOC_DAIFMT_NB_NF:
1145 break;
1146 case SND_SOC_DAIFMT_IB_NF:
1147 ctrl1_val |= NAU8824_I2S_BP_INV;
1148 break;
1149 default:
1150 return -EINVAL;
1151 }
1152
1153 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1154 case SND_SOC_DAIFMT_I2S:
1155 ctrl1_val |= NAU8824_I2S_DF_I2S;
1156 break;
1157 case SND_SOC_DAIFMT_LEFT_J:
1158 ctrl1_val |= NAU8824_I2S_DF_LEFT;
1159 break;
1160 case SND_SOC_DAIFMT_RIGHT_J:
1161 ctrl1_val |= NAU8824_I2S_DF_RIGTH;
1162 break;
1163 case SND_SOC_DAIFMT_DSP_A:
1164 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1165 break;
1166 case SND_SOC_DAIFMT_DSP_B:
1167 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1168 ctrl1_val |= NAU8824_I2S_PCMB_EN;
1169 break;
1170 default:
1171 return -EINVAL;
1172 }
1173
1174 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1175 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
1176 NAU8824_I2S_PCMB_EN, ctrl1_val);
1177 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1178 NAU8824_I2S_MS_MASK, ctrl2_val);
1179
1180 nau8824_sema_release(nau8824);
1181
1182 return 0;
1183}
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
1202 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1203{
1204 struct snd_soc_component *component = dai->component;
1205 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1206 unsigned int tslot_l = 0, ctrl_val = 0;
1207
1208 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
1209 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
1210 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
1211 ((rx_mask & 0xf) && (tx_mask & 0xf0)))
1212 return -EINVAL;
1213
1214 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
1215 if (tx_mask & 0xf0) {
1216 tslot_l = 4 * slot_width;
1217 ctrl_val |= (tx_mask >> 4);
1218 } else {
1219 ctrl_val |= tx_mask;
1220 }
1221 if (rx_mask & 0xf0)
1222 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
1223 else
1224 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
1225
1226 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
1227 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
1228 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
1229 NAU8824_TDM_TX_MASK, ctrl_val);
1230 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1231 NAU8824_TSLOT_L_MASK, tslot_l);
1232
1233 return 0;
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246static int nau8824_calc_fll_param(unsigned int fll_in,
1247 unsigned int fs, struct nau8824_fll *fll_param)
1248{
1249 u64 fvco, fvco_max;
1250 unsigned int fref, i, fvco_sel;
1251
1252
1253
1254
1255
1256 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1257 fref = fll_in / fll_pre_scalar[i].param;
1258 if (fref <= NAU_FREF_MAX)
1259 break;
1260 }
1261 if (i == ARRAY_SIZE(fll_pre_scalar))
1262 return -EINVAL;
1263 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1264
1265
1266 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1267 if (fref >= fll_ratio[i].param)
1268 break;
1269 }
1270 if (i == ARRAY_SIZE(fll_ratio))
1271 return -EINVAL;
1272 fll_param->ratio = fll_ratio[i].val;
1273
1274
1275
1276
1277
1278
1279 fvco_max = 0;
1280 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1281 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1282 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1283 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1284 fvco_max < fvco) {
1285 fvco_max = fvco;
1286 fvco_sel = i;
1287 }
1288 }
1289 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1290 return -EINVAL;
1291 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1292
1293
1294
1295
1296 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1297 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1298 fll_param->fll_frac = fvco & 0xFFFF;
1299 return 0;
1300}
1301
1302static void nau8824_fll_apply(struct regmap *regmap,
1303 struct nau8824_fll *fll_param)
1304{
1305 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1306 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
1307 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1308 regmap_update_bits(regmap, NAU8824_REG_FLL1,
1309 NAU8824_FLL_RATIO_MASK, fll_param->ratio);
1310
1311 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
1312
1313 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1314 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
1315
1316 regmap_update_bits(regmap, NAU8824_REG_FLL4,
1317 NAU8824_FLL_REF_DIV_MASK,
1318 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1319
1320 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1321 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
1322
1323 regmap_update_bits(regmap,
1324 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
1325 if (fll_param->fll_frac) {
1326 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1327 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1328 NAU8824_FLL_FTR_SW_MASK,
1329 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1330 NAU8824_FLL_FTR_SW_FILTER);
1331 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1332 NAU8824_SDM_EN, NAU8824_SDM_EN);
1333 } else {
1334 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1335 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1336 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
1337 regmap_update_bits(regmap,
1338 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
1339 }
1340}
1341
1342
1343static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
1344 unsigned int freq_in, unsigned int freq_out)
1345{
1346 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1347 struct nau8824_fll fll_param;
1348 int ret, fs;
1349
1350 fs = freq_out / 256;
1351 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
1352 if (ret < 0) {
1353 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1354 return ret;
1355 }
1356 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1357 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1358 fll_param.fll_int, fll_param.clk_ref_div);
1359
1360 nau8824_fll_apply(nau8824->regmap, &fll_param);
1361 mdelay(2);
1362 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1363 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1364
1365 return 0;
1366}
1367
1368static int nau8824_config_sysclk(struct nau8824 *nau8824,
1369 int clk_id, unsigned int freq)
1370{
1371 struct regmap *regmap = nau8824->regmap;
1372
1373 switch (clk_id) {
1374 case NAU8824_CLK_DIS:
1375 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1376 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1377 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1378 NAU8824_DCO_EN, 0);
1379 break;
1380
1381 case NAU8824_CLK_MCLK:
1382 nau8824_sema_acquire(nau8824, HZ);
1383 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1384 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1385 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1386 NAU8824_DCO_EN, 0);
1387 nau8824_sema_release(nau8824);
1388 break;
1389
1390 case NAU8824_CLK_INTERNAL:
1391 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1392 NAU8824_DCO_EN, NAU8824_DCO_EN);
1393 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1394 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1395 break;
1396
1397 case NAU8824_CLK_FLL_MCLK:
1398 nau8824_sema_acquire(nau8824, HZ);
1399 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1400 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
1401 nau8824_sema_release(nau8824);
1402 break;
1403
1404 case NAU8824_CLK_FLL_BLK:
1405 nau8824_sema_acquire(nau8824, HZ);
1406 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1407 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
1408 nau8824_sema_release(nau8824);
1409 break;
1410
1411 case NAU8824_CLK_FLL_FS:
1412 nau8824_sema_acquire(nau8824, HZ);
1413 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1414 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
1415 nau8824_sema_release(nau8824);
1416 break;
1417
1418 default:
1419 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1420 return -EINVAL;
1421 }
1422
1423 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1424 clk_id);
1425
1426 return 0;
1427}
1428
1429static int nau8824_set_sysclk(struct snd_soc_component *component,
1430 int clk_id, int source, unsigned int freq, int dir)
1431{
1432 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1433
1434 return nau8824_config_sysclk(nau8824, clk_id, freq);
1435}
1436
1437static void nau8824_resume_setup(struct nau8824 *nau8824)
1438{
1439 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
1440 if (nau8824->irq) {
1441
1442 nau8824_int_status_clear_all(nau8824->regmap);
1443
1444
1445
1446 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1447 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1448 regmap_update_bits(nau8824->regmap,
1449 NAU8824_REG_INTERRUPT_SETTING_1,
1450 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
1451 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
1452 regmap_update_bits(nau8824->regmap,
1453 NAU8824_REG_INTERRUPT_SETTING,
1454 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
1455 }
1456}
1457
1458static int nau8824_set_bias_level(struct snd_soc_component *component,
1459 enum snd_soc_bias_level level)
1460{
1461 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1462
1463 switch (level) {
1464 case SND_SOC_BIAS_ON:
1465 break;
1466
1467 case SND_SOC_BIAS_PREPARE:
1468 break;
1469
1470 case SND_SOC_BIAS_STANDBY:
1471 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1472
1473 nau8824_resume_setup(nau8824);
1474 }
1475 break;
1476
1477 case SND_SOC_BIAS_OFF:
1478 regmap_update_bits(nau8824->regmap,
1479 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1480 regmap_update_bits(nau8824->regmap,
1481 NAU8824_REG_INTERRUPT_SETTING_1,
1482 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1483 break;
1484 }
1485
1486 return 0;
1487}
1488
1489static int nau8824_component_probe(struct snd_soc_component *component)
1490{
1491 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1492 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1493
1494 nau8824->dapm = dapm;
1495
1496 return 0;
1497}
1498
1499static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
1500{
1501 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1502
1503 if (nau8824->irq) {
1504 disable_irq(nau8824->irq);
1505 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1506 }
1507 regcache_cache_only(nau8824->regmap, true);
1508 regcache_mark_dirty(nau8824->regmap);
1509
1510 return 0;
1511}
1512
1513static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
1514{
1515 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1516
1517 regcache_cache_only(nau8824->regmap, false);
1518 regcache_sync(nau8824->regmap);
1519 if (nau8824->irq) {
1520
1521
1522
1523 nau8824_sema_acquire(nau8824, 0);
1524 enable_irq(nau8824->irq);
1525 }
1526
1527 return 0;
1528}
1529
1530static const struct snd_soc_component_driver nau8824_component_driver = {
1531 .probe = nau8824_component_probe,
1532 .set_sysclk = nau8824_set_sysclk,
1533 .set_pll = nau8824_set_pll,
1534 .set_bias_level = nau8824_set_bias_level,
1535 .suspend = nau8824_suspend,
1536 .resume = nau8824_resume,
1537 .controls = nau8824_snd_controls,
1538 .num_controls = ARRAY_SIZE(nau8824_snd_controls),
1539 .dapm_widgets = nau8824_dapm_widgets,
1540 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
1541 .dapm_routes = nau8824_dapm_routes,
1542 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
1543 .suspend_bias_off = 1,
1544 .idle_bias_on = 1,
1545 .use_pmdown_time = 1,
1546 .endianness = 1,
1547 .non_legacy_dai_naming = 1,
1548};
1549
1550static const struct snd_soc_dai_ops nau8824_dai_ops = {
1551 .hw_params = nau8824_hw_params,
1552 .set_fmt = nau8824_set_fmt,
1553 .set_tdm_slot = nau8824_set_tdm_slot,
1554};
1555
1556#define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
1557#define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1558 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1559
1560static struct snd_soc_dai_driver nau8824_dai = {
1561 .name = NAU8824_CODEC_DAI,
1562 .playback = {
1563 .stream_name = "Playback",
1564 .channels_min = 1,
1565 .channels_max = 2,
1566 .rates = NAU8824_RATES,
1567 .formats = NAU8824_FORMATS,
1568 },
1569 .capture = {
1570 .stream_name = "Capture",
1571 .channels_min = 1,
1572 .channels_max = 2,
1573 .rates = NAU8824_RATES,
1574 .formats = NAU8824_FORMATS,
1575 },
1576 .ops = &nau8824_dai_ops,
1577};
1578
1579static const struct regmap_config nau8824_regmap_config = {
1580 .val_bits = NAU8824_REG_ADDR_LEN,
1581 .reg_bits = NAU8824_REG_DATA_LEN,
1582
1583 .max_register = NAU8824_REG_MAX,
1584 .readable_reg = nau8824_readable_reg,
1585 .writeable_reg = nau8824_writeable_reg,
1586 .volatile_reg = nau8824_volatile_reg,
1587
1588 .cache_type = REGCACHE_RBTREE,
1589 .reg_defaults = nau8824_reg_defaults,
1590 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
1591};
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603int nau8824_enable_jack_detect(struct snd_soc_component *component,
1604 struct snd_soc_jack *jack)
1605{
1606 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1607 int ret;
1608
1609 nau8824->jack = jack;
1610
1611 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1612 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
1613 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1614 "nau8824", nau8824);
1615 if (ret) {
1616 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1617 nau8824->irq, ret);
1618 }
1619
1620 return ret;
1621}
1622EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
1623
1624static void nau8824_reset_chip(struct regmap *regmap)
1625{
1626 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1627 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1628}
1629
1630static void nau8824_setup_buttons(struct nau8824 *nau8824)
1631{
1632 struct regmap *regmap = nau8824->regmap;
1633
1634 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1635 NAU8824_SAR_TRACKING_GAIN_MASK,
1636 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1637 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1638 NAU8824_SAR_COMPARE_TIME_MASK,
1639 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1640 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1641 NAU8824_SAR_SAMPLING_TIME_MASK,
1642 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1643
1644 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1645 NAU8824_LEVELS_NR_MASK,
1646 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1647 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1648 NAU8824_HYSTERESIS_MASK,
1649 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1650 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1651 NAU8824_SHORTKEY_DEBOUNCE_MASK,
1652 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1653
1654 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
1655 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1656 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
1657 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1658 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
1659 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1660 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
1661 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1662}
1663
1664static void nau8824_init_regs(struct nau8824 *nau8824)
1665{
1666 struct regmap *regmap = nau8824->regmap;
1667
1668
1669 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
1670 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
1671 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1672 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1673 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
1674 mdelay(2);
1675 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
1676 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
1677
1678 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1679 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1680 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
1681 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1682 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
1683
1684 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1685 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
1686 (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
1687 (0x1 << NAU8824_CLK_DAC_SRC_SFT));
1688 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
1689 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
1690 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
1691 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1692 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1693 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
1694 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1695 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1696 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
1697 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
1698 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1699 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1700 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1701 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
1702 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1703 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1704 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1705 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
1706
1707 regmap_update_bits(regmap, NAU8824_REG_CLASSG,
1708 NAU8824_CLASSG_TIMER_MASK,
1709 0x20 << NAU8824_CLASSG_TIMER_SFT);
1710 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
1711 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
1712
1713 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
1714 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1715 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
1716 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1717 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
1718
1719
1720
1721
1722 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1723 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
1724
1725 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
1726 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
1727 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
1728 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
1729 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1730 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
1731 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
1732
1733
1734
1735 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
1736 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
1737 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
1738 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
1739 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
1740
1741 regmap_update_bits(regmap, NAU8824_REG_RDAC,
1742 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
1743 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
1744 (0x3 << NAU8824_RDAC_VREF_SFT));
1745
1746 regmap_update_bits(regmap, NAU8824_REG_FEPGA,
1747 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
1748 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
1749
1750 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
1751 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
1752 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
1753 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
1754 NAU8824_JACK_LOGIC,
1755
1756 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1757 regmap_update_bits(regmap,
1758 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
1759 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1760 if (nau8824->sar_threshold_num)
1761 nau8824_setup_buttons(nau8824);
1762}
1763
1764static int nau8824_setup_irq(struct nau8824 *nau8824)
1765{
1766
1767 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1768 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1769 regmap_update_bits(nau8824->regmap,
1770 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1771 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1772 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1773
1774 return 0;
1775}
1776
1777static void nau8824_print_device_properties(struct nau8824 *nau8824)
1778{
1779 struct device *dev = nau8824->dev;
1780 int i;
1781
1782 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1783 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1784 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1785
1786 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1787 for (i = 0; i < nau8824->sar_threshold_num; i++)
1788 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1789 nau8824->sar_threshold[i]);
1790
1791 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1792 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1793 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1794 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1795 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1796 dev_dbg(dev, "jack-eject-debounce: %d\n",
1797 nau8824->jack_eject_debounce);
1798}
1799
1800static int nau8824_read_device_properties(struct device *dev,
1801 struct nau8824 *nau8824) {
1802 int ret;
1803
1804 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1805 &nau8824->jkdet_polarity);
1806 if (ret)
1807 nau8824->jkdet_polarity = 1;
1808 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1809 &nau8824->micbias_voltage);
1810 if (ret)
1811 nau8824->micbias_voltage = 6;
1812 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1813 &nau8824->vref_impedance);
1814 if (ret)
1815 nau8824->vref_impedance = 2;
1816 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1817 &nau8824->sar_threshold_num);
1818 if (ret)
1819 nau8824->sar_threshold_num = 4;
1820 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1821 nau8824->sar_threshold, nau8824->sar_threshold_num);
1822 if (ret) {
1823 nau8824->sar_threshold[0] = 0x0a;
1824 nau8824->sar_threshold[1] = 0x14;
1825 nau8824->sar_threshold[2] = 0x26;
1826 nau8824->sar_threshold[3] = 0x73;
1827 }
1828 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1829 &nau8824->sar_hysteresis);
1830 if (ret)
1831 nau8824->sar_hysteresis = 0;
1832 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
1833 &nau8824->sar_voltage);
1834 if (ret)
1835 nau8824->sar_voltage = 6;
1836 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
1837 &nau8824->sar_compare_time);
1838 if (ret)
1839 nau8824->sar_compare_time = 1;
1840 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1841 &nau8824->sar_sampling_time);
1842 if (ret)
1843 nau8824->sar_sampling_time = 1;
1844 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
1845 &nau8824->key_debounce);
1846 if (ret)
1847 nau8824->key_debounce = 0;
1848 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1849 &nau8824->jack_eject_debounce);
1850 if (ret)
1851 nau8824->jack_eject_debounce = 1;
1852
1853 return 0;
1854}
1855
1856
1857static const struct dmi_system_id nau8824_quirk_table[] = {
1858 {
1859
1860 .matches = {
1861 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
1862 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1863 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
1864 },
1865 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH |
1866 NAU8824_MONO_SPEAKER),
1867 },
1868 {
1869
1870 .matches = {
1871 DMI_MATCH(DMI_SYS_VENDOR, "cube"),
1872 DMI_MATCH(DMI_PRODUCT_NAME, "i1-TF"),
1873 DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1874 },
1875 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1876 },
1877 {
1878
1879 .matches = {
1880 DMI_MATCH(DMI_SYS_VENDOR, "PIPO"),
1881 DMI_MATCH(DMI_PRODUCT_NAME, "W2S"),
1882 },
1883 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1884 },
1885 {}
1886};
1887
1888static void nau8824_check_quirks(void)
1889{
1890 const struct dmi_system_id *dmi_id;
1891
1892 if (quirk_override != -1) {
1893 nau8824_quirk = quirk_override;
1894 return;
1895 }
1896
1897 dmi_id = dmi_first_match(nau8824_quirk_table);
1898 if (dmi_id)
1899 nau8824_quirk = (unsigned long)dmi_id->driver_data;
1900}
1901
1902const char *nau8824_components(void)
1903{
1904 nau8824_check_quirks();
1905
1906 if (nau8824_quirk & NAU8824_MONO_SPEAKER)
1907 return "cfg-spk:1";
1908 else
1909 return "cfg-spk:2";
1910}
1911EXPORT_SYMBOL_GPL(nau8824_components);
1912
1913static int nau8824_i2c_probe(struct i2c_client *i2c,
1914 const struct i2c_device_id *id)
1915{
1916 struct device *dev = &i2c->dev;
1917 struct nau8824 *nau8824 = dev_get_platdata(dev);
1918 int ret, value;
1919
1920 if (!nau8824) {
1921 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
1922 if (!nau8824)
1923 return -ENOMEM;
1924 ret = nau8824_read_device_properties(dev, nau8824);
1925 if (ret)
1926 return ret;
1927 }
1928 i2c_set_clientdata(i2c, nau8824);
1929
1930 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1931 if (IS_ERR(nau8824->regmap))
1932 return PTR_ERR(nau8824->regmap);
1933 nau8824->dev = dev;
1934 nau8824->irq = i2c->irq;
1935 sema_init(&nau8824->jd_sem, 1);
1936
1937 nau8824_check_quirks();
1938
1939 if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
1940 nau8824->jkdet_polarity = 0;
1941
1942 nau8824_print_device_properties(nau8824);
1943
1944 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
1945 if (ret < 0) {
1946 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
1947 ret);
1948 return ret;
1949 }
1950 nau8824_reset_chip(nau8824->regmap);
1951 nau8824_init_regs(nau8824);
1952
1953 if (i2c->irq)
1954 nau8824_setup_irq(nau8824);
1955
1956 return devm_snd_soc_register_component(dev,
1957 &nau8824_component_driver, &nau8824_dai, 1);
1958}
1959
1960static const struct i2c_device_id nau8824_i2c_ids[] = {
1961 { "nau8824", 0 },
1962 { }
1963};
1964MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
1965
1966#ifdef CONFIG_OF
1967static const struct of_device_id nau8824_of_ids[] = {
1968 { .compatible = "nuvoton,nau8824", },
1969 {}
1970};
1971MODULE_DEVICE_TABLE(of, nau8824_of_ids);
1972#endif
1973
1974#ifdef CONFIG_ACPI
1975static const struct acpi_device_id nau8824_acpi_match[] = {
1976 { "10508824", 0 },
1977 {},
1978};
1979MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
1980#endif
1981
1982static struct i2c_driver nau8824_i2c_driver = {
1983 .driver = {
1984 .name = "nau8824",
1985 .of_match_table = of_match_ptr(nau8824_of_ids),
1986 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
1987 },
1988 .probe = nau8824_i2c_probe,
1989 .id_table = nau8824_i2c_ids,
1990};
1991module_i2c_driver(nau8824_i2c_driver);
1992
1993
1994MODULE_DESCRIPTION("ASoC NAU88L24 driver");
1995MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
1996MODULE_LICENSE("GPL v2");
1997