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9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/acpi.h>
15#include <linux/gpio.h>
16#include <linux/of_gpio.h>
17#include <linux/pm_runtime.h>
18#include <linux/regulator/consumer.h>
19#include <linux/mutex.h>
20#include <linux/soundwire/sdw.h>
21#include <linux/soundwire/sdw_type.h>
22#include <linux/soundwire/sdw_registers.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/jack.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "rt5682.h"
33
34#define RT5682_SDW_ADDR_L 0x3000
35#define RT5682_SDW_ADDR_H 0x3001
36#define RT5682_SDW_DATA_L 0x3004
37#define RT5682_SDW_DATA_H 0x3005
38#define RT5682_SDW_CMD 0x3008
39
40static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
41{
42 struct device *dev = context;
43 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
44 unsigned int data_l, data_h;
45
46 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
47 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
48 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
49 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
50 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
51
52 *val = (data_h << 8) | data_l;
53
54 dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
55
56 return 0;
57}
58
59static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
60{
61 struct device *dev = context;
62 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
63
64 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
65 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
66 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
67 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
68 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
69
70 dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
71
72 return 0;
73}
74
75static const struct regmap_config rt5682_sdw_indirect_regmap = {
76 .reg_bits = 16,
77 .val_bits = 16,
78 .max_register = RT5682_I2C_MODE,
79 .volatile_reg = rt5682_volatile_register,
80 .readable_reg = rt5682_readable_register,
81 .cache_type = REGCACHE_RBTREE,
82 .reg_defaults = rt5682_reg,
83 .num_reg_defaults = RT5682_REG_NUM,
84 .use_single_read = true,
85 .use_single_write = true,
86 .reg_read = rt5682_sdw_read,
87 .reg_write = rt5682_sdw_write,
88};
89
90struct sdw_stream_data {
91 struct sdw_stream_runtime *sdw_stream;
92};
93
94static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
95 int direction)
96{
97 struct sdw_stream_data *stream;
98
99 if (!sdw_stream)
100 return 0;
101
102 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
103 if (!stream)
104 return -ENOMEM;
105
106 stream->sdw_stream = sdw_stream;
107
108
109 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
110 dai->playback_dma_data = stream;
111 else
112 dai->capture_dma_data = stream;
113
114 return 0;
115}
116
117static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
118 struct snd_soc_dai *dai)
119{
120 struct sdw_stream_data *stream;
121
122 stream = snd_soc_dai_get_dma_data(dai, substream);
123 snd_soc_dai_set_dma_data(dai, substream, NULL);
124 kfree(stream);
125}
126
127static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
128 struct snd_pcm_hw_params *params,
129 struct snd_soc_dai *dai)
130{
131 struct snd_soc_component *component = dai->component;
132 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
133 struct sdw_stream_config stream_config;
134 struct sdw_port_config port_config;
135 enum sdw_data_direction direction;
136 struct sdw_stream_data *stream;
137 int retval, port, num_channels;
138 unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
139
140 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
141
142 stream = snd_soc_dai_get_dma_data(dai, substream);
143 if (!stream)
144 return -ENOMEM;
145
146 if (!rt5682->slave)
147 return -EINVAL;
148
149
150 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
151 direction = SDW_DATA_DIR_RX;
152 port = 1;
153 } else {
154 direction = SDW_DATA_DIR_TX;
155 port = 2;
156 }
157
158 stream_config.frame_rate = params_rate(params);
159 stream_config.ch_count = params_channels(params);
160 stream_config.bps = snd_pcm_format_width(params_format(params));
161 stream_config.direction = direction;
162
163 num_channels = params_channels(params);
164 port_config.ch_mask = (1 << (num_channels)) - 1;
165 port_config.num = port;
166
167 retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
168 &port_config, 1, stream->sdw_stream);
169 if (retval) {
170 dev_err(dai->dev, "Unable to configure port\n");
171 return retval;
172 }
173
174 switch (params_rate(params)) {
175 case 48000:
176 val_p = RT5682_SDW_REF_1_48K;
177 val_c = RT5682_SDW_REF_2_48K;
178 break;
179 case 96000:
180 val_p = RT5682_SDW_REF_1_96K;
181 val_c = RT5682_SDW_REF_2_96K;
182 break;
183 case 192000:
184 val_p = RT5682_SDW_REF_1_192K;
185 val_c = RT5682_SDW_REF_2_192K;
186 break;
187 case 32000:
188 val_p = RT5682_SDW_REF_1_32K;
189 val_c = RT5682_SDW_REF_2_32K;
190 break;
191 case 24000:
192 val_p = RT5682_SDW_REF_1_24K;
193 val_c = RT5682_SDW_REF_2_24K;
194 break;
195 case 16000:
196 val_p = RT5682_SDW_REF_1_16K;
197 val_c = RT5682_SDW_REF_2_16K;
198 break;
199 case 12000:
200 val_p = RT5682_SDW_REF_1_12K;
201 val_c = RT5682_SDW_REF_2_12K;
202 break;
203 case 8000:
204 val_p = RT5682_SDW_REF_1_8K;
205 val_c = RT5682_SDW_REF_2_8K;
206 break;
207 case 44100:
208 val_p = RT5682_SDW_REF_1_44K;
209 val_c = RT5682_SDW_REF_2_44K;
210 break;
211 case 88200:
212 val_p = RT5682_SDW_REF_1_88K;
213 val_c = RT5682_SDW_REF_2_88K;
214 break;
215 case 176400:
216 val_p = RT5682_SDW_REF_1_176K;
217 val_c = RT5682_SDW_REF_2_176K;
218 break;
219 case 22050:
220 val_p = RT5682_SDW_REF_1_22K;
221 val_c = RT5682_SDW_REF_2_22K;
222 break;
223 case 11025:
224 val_p = RT5682_SDW_REF_1_11K;
225 val_c = RT5682_SDW_REF_2_11K;
226 break;
227 default:
228 return -EINVAL;
229 }
230
231 if (params_rate(params) <= 48000) {
232 osr_p = RT5682_DAC_OSR_D_8;
233 osr_c = RT5682_ADC_OSR_D_8;
234 } else if (params_rate(params) <= 96000) {
235 osr_p = RT5682_DAC_OSR_D_4;
236 osr_c = RT5682_ADC_OSR_D_4;
237 } else {
238 osr_p = RT5682_DAC_OSR_D_2;
239 osr_c = RT5682_ADC_OSR_D_2;
240 }
241
242 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
243 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
244 RT5682_SDW_REF_1_MASK, val_p);
245 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
246 RT5682_DAC_OSR_MASK, osr_p);
247 } else {
248 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
249 RT5682_SDW_REF_2_MASK, val_c);
250 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
251 RT5682_ADC_OSR_MASK, osr_c);
252 }
253
254 return retval;
255}
256
257static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
258 struct snd_soc_dai *dai)
259{
260 struct snd_soc_component *component = dai->component;
261 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
262 struct sdw_stream_data *stream =
263 snd_soc_dai_get_dma_data(dai, substream);
264
265 if (!rt5682->slave)
266 return -EINVAL;
267
268 sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream);
269 return 0;
270}
271
272static const struct snd_soc_dai_ops rt5682_sdw_ops = {
273 .hw_params = rt5682_sdw_hw_params,
274 .hw_free = rt5682_sdw_hw_free,
275 .set_sdw_stream = rt5682_set_sdw_stream,
276 .shutdown = rt5682_sdw_shutdown,
277};
278
279static struct snd_soc_dai_driver rt5682_dai[] = {
280 {
281 .name = "rt5682-aif1",
282 .id = RT5682_AIF1,
283 .playback = {
284 .stream_name = "AIF1 Playback",
285 .channels_min = 1,
286 .channels_max = 2,
287 .rates = RT5682_STEREO_RATES,
288 .formats = RT5682_FORMATS,
289 },
290 .capture = {
291 .stream_name = "AIF1 Capture",
292 .channels_min = 1,
293 .channels_max = 2,
294 .rates = RT5682_STEREO_RATES,
295 .formats = RT5682_FORMATS,
296 },
297 .ops = &rt5682_aif1_dai_ops,
298 },
299 {
300 .name = "rt5682-aif2",
301 .id = RT5682_AIF2,
302 .capture = {
303 .stream_name = "AIF2 Capture",
304 .channels_min = 1,
305 .channels_max = 2,
306 .rates = RT5682_STEREO_RATES,
307 .formats = RT5682_FORMATS,
308 },
309 .ops = &rt5682_aif2_dai_ops,
310 },
311 {
312 .name = "rt5682-sdw",
313 .id = RT5682_SDW,
314 .playback = {
315 .stream_name = "SDW Playback",
316 .channels_min = 1,
317 .channels_max = 2,
318 .rates = RT5682_STEREO_RATES,
319 .formats = RT5682_FORMATS,
320 },
321 .capture = {
322 .stream_name = "SDW Capture",
323 .channels_min = 1,
324 .channels_max = 2,
325 .rates = RT5682_STEREO_RATES,
326 .formats = RT5682_FORMATS,
327 },
328 .ops = &rt5682_sdw_ops,
329 },
330};
331
332static int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
333 struct sdw_slave *slave)
334{
335 struct rt5682_priv *rt5682;
336 int ret;
337
338 rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
339 if (!rt5682)
340 return -ENOMEM;
341
342 dev_set_drvdata(dev, rt5682);
343 rt5682->slave = slave;
344 rt5682->sdw_regmap = regmap;
345 rt5682->is_sdw = true;
346
347 mutex_init(&rt5682->disable_irq_lock);
348
349 rt5682->regmap = devm_regmap_init(dev, NULL, dev,
350 &rt5682_sdw_indirect_regmap);
351 if (IS_ERR(rt5682->regmap)) {
352 ret = PTR_ERR(rt5682->regmap);
353 dev_err(dev, "Failed to allocate register map: %d\n",
354 ret);
355 return ret;
356 }
357
358
359
360
361
362 rt5682->hw_init = false;
363 rt5682->first_hw_init = false;
364
365 mutex_init(&rt5682->calibrate_mutex);
366 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
367 rt5682_jack_detect_handler);
368
369 ret = devm_snd_soc_register_component(dev,
370 &rt5682_soc_component_dev,
371 rt5682_dai, ARRAY_SIZE(rt5682_dai));
372 dev_dbg(&slave->dev, "%s\n", __func__);
373
374 return ret;
375}
376
377static int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
378{
379 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
380 int ret = 0, loop = 10;
381 unsigned int val;
382
383 rt5682->disable_irq = false;
384
385 if (rt5682->hw_init)
386 return 0;
387
388
389
390
391 if (!rt5682->first_hw_init) {
392
393 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
394 pm_runtime_use_autosuspend(&slave->dev);
395
396
397 pm_runtime_set_active(&slave->dev);
398
399
400 pm_runtime_mark_last_busy(&slave->dev);
401
402 pm_runtime_enable(&slave->dev);
403 }
404
405 pm_runtime_get_noresume(&slave->dev);
406
407 if (rt5682->first_hw_init) {
408 regcache_cache_only(rt5682->regmap, false);
409 regcache_cache_bypass(rt5682->regmap, true);
410 }
411
412 while (loop > 0) {
413 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
414 if (val == DEVICE_ID)
415 break;
416 dev_warn(dev, "Device with ID register %x is not rt5682\n", val);
417 usleep_range(30000, 30005);
418 loop--;
419 }
420
421 if (val != DEVICE_ID) {
422 dev_err(dev, "Device with ID register %x is not rt5682\n", val);
423 ret = -ENODEV;
424 goto err_nodev;
425 }
426
427 rt5682_calibrate(rt5682);
428
429 if (rt5682->first_hw_init) {
430 regcache_cache_bypass(rt5682->regmap, false);
431 regcache_mark_dirty(rt5682->regmap);
432 regcache_sync(rt5682->regmap);
433
434
435 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
436 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
437
438 goto reinit;
439 }
440
441 rt5682_apply_patch_list(rt5682, dev);
442
443 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
444
445 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
446 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
447 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
448 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
449 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
450 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
451 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
452 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
453 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
454 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
455 RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
456
457
458 regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
459 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
460 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
461 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
462 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
463 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
464 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
465 regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
466 RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
467 RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
468
469 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
470 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
471 regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd142);
472 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
473 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
474 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
475 regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
476 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
477 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
478 RT5682_POW_IRQ | RT5682_POW_JDH |
479 RT5682_POW_ANA, RT5682_POW_IRQ |
480 RT5682_POW_JDH | RT5682_POW_ANA);
481 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
482 RT5682_PWR_JDH, RT5682_PWR_JDH);
483 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
484 RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
485 RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
486
487reinit:
488 mod_delayed_work(system_power_efficient_wq,
489 &rt5682->jack_detect_work, msecs_to_jiffies(250));
490
491
492 rt5682->hw_init = true;
493 rt5682->first_hw_init = true;
494
495err_nodev:
496 pm_runtime_mark_last_busy(&slave->dev);
497 pm_runtime_put_autosuspend(&slave->dev);
498
499 dev_dbg(&slave->dev, "%s hw_init complete: %d\n", __func__, ret);
500
501 return ret;
502}
503
504static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
505{
506 switch (reg) {
507 case 0x00e0:
508 case 0x00f0:
509 case 0x3000:
510 case 0x3001:
511 case 0x3004:
512 case 0x3005:
513 case 0x3008:
514 return true;
515 default:
516 return false;
517 }
518}
519
520static const struct regmap_config rt5682_sdw_regmap = {
521 .name = "sdw",
522 .reg_bits = 32,
523 .val_bits = 8,
524 .max_register = RT5682_I2C_MODE,
525 .readable_reg = rt5682_sdw_readable_register,
526 .cache_type = REGCACHE_NONE,
527 .use_single_read = true,
528 .use_single_write = true,
529};
530
531static int rt5682_update_status(struct sdw_slave *slave,
532 enum sdw_slave_status status)
533{
534 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
535
536
537 rt5682->status = status;
538
539 if (status == SDW_SLAVE_UNATTACHED)
540 rt5682->hw_init = false;
541
542
543
544
545
546 if (rt5682->hw_init || rt5682->status != SDW_SLAVE_ATTACHED)
547 return 0;
548
549
550 return rt5682_io_init(&slave->dev, slave);
551}
552
553static int rt5682_read_prop(struct sdw_slave *slave)
554{
555 struct sdw_slave_prop *prop = &slave->prop;
556 int nval, i;
557 u32 bit;
558 unsigned long addr;
559 struct sdw_dpn_prop *dpn;
560
561 prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
562 SDW_SCP_INT1_PARITY;
563 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
564
565 prop->paging_support = false;
566
567
568 prop->source_ports = 0x4;
569 prop->sink_ports = 0x2;
570
571 nval = hweight32(prop->source_ports);
572 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
573 sizeof(*prop->src_dpn_prop),
574 GFP_KERNEL);
575 if (!prop->src_dpn_prop)
576 return -ENOMEM;
577
578 i = 0;
579 dpn = prop->src_dpn_prop;
580 addr = prop->source_ports;
581 for_each_set_bit(bit, &addr, 32) {
582 dpn[i].num = bit;
583 dpn[i].type = SDW_DPN_FULL;
584 dpn[i].simple_ch_prep_sm = true;
585 dpn[i].ch_prep_timeout = 10;
586 i++;
587 }
588
589
590 nval = hweight32(prop->sink_ports);
591 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
592 sizeof(*prop->sink_dpn_prop),
593 GFP_KERNEL);
594 if (!prop->sink_dpn_prop)
595 return -ENOMEM;
596
597 i = 0;
598 dpn = prop->sink_dpn_prop;
599 addr = prop->sink_ports;
600 for_each_set_bit(bit, &addr, 32) {
601 dpn[i].num = bit;
602 dpn[i].type = SDW_DPN_FULL;
603 dpn[i].simple_ch_prep_sm = true;
604 dpn[i].ch_prep_timeout = 10;
605 i++;
606 }
607
608
609 prop->clk_stop_timeout = 20;
610
611
612 prop->wake_capable = 1;
613
614 return 0;
615}
616
617
618#define RT5682_CLK_FREQ_9600000HZ 9600000
619#define RT5682_CLK_FREQ_12000000HZ 12000000
620#define RT5682_CLK_FREQ_6000000HZ 6000000
621#define RT5682_CLK_FREQ_4800000HZ 4800000
622#define RT5682_CLK_FREQ_2400000HZ 2400000
623#define RT5682_CLK_FREQ_12288000HZ 12288000
624
625static int rt5682_clock_config(struct device *dev)
626{
627 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
628 unsigned int clk_freq, value;
629
630 clk_freq = (rt5682->params.curr_dr_freq >> 1);
631
632 switch (clk_freq) {
633 case RT5682_CLK_FREQ_12000000HZ:
634 value = 0x0;
635 break;
636 case RT5682_CLK_FREQ_6000000HZ:
637 value = 0x1;
638 break;
639 case RT5682_CLK_FREQ_9600000HZ:
640 value = 0x2;
641 break;
642 case RT5682_CLK_FREQ_4800000HZ:
643 value = 0x3;
644 break;
645 case RT5682_CLK_FREQ_2400000HZ:
646 value = 0x4;
647 break;
648 case RT5682_CLK_FREQ_12288000HZ:
649 value = 0x5;
650 break;
651 default:
652 return -EINVAL;
653 }
654
655 regmap_write(rt5682->sdw_regmap, 0xe0, value);
656 regmap_write(rt5682->sdw_regmap, 0xf0, value);
657
658 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
659
660 return 0;
661}
662
663static int rt5682_bus_config(struct sdw_slave *slave,
664 struct sdw_bus_params *params)
665{
666 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
667 int ret;
668
669 memcpy(&rt5682->params, params, sizeof(*params));
670
671 ret = rt5682_clock_config(&slave->dev);
672 if (ret < 0)
673 dev_err(&slave->dev, "Invalid clk config");
674
675 return ret;
676}
677
678static int rt5682_interrupt_callback(struct sdw_slave *slave,
679 struct sdw_slave_intr_status *status)
680{
681 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
682
683 dev_dbg(&slave->dev,
684 "%s control_port_stat=%x", __func__, status->control_port);
685
686 mutex_lock(&rt5682->disable_irq_lock);
687 if (status->control_port & 0x4 && !rt5682->disable_irq) {
688 mod_delayed_work(system_power_efficient_wq,
689 &rt5682->jack_detect_work, msecs_to_jiffies(rt5682->irq_work_delay_time));
690 }
691 mutex_unlock(&rt5682->disable_irq_lock);
692
693 return 0;
694}
695
696static const struct sdw_slave_ops rt5682_slave_ops = {
697 .read_prop = rt5682_read_prop,
698 .interrupt_callback = rt5682_interrupt_callback,
699 .update_status = rt5682_update_status,
700 .bus_config = rt5682_bus_config,
701};
702
703static int rt5682_sdw_probe(struct sdw_slave *slave,
704 const struct sdw_device_id *id)
705{
706 struct regmap *regmap;
707
708
709 regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
710 if (IS_ERR(regmap))
711 return -EINVAL;
712
713 rt5682_sdw_init(&slave->dev, regmap, slave);
714
715 return 0;
716}
717
718static int rt5682_sdw_remove(struct sdw_slave *slave)
719{
720 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
721
722 if (rt5682 && rt5682->hw_init)
723 cancel_delayed_work_sync(&rt5682->jack_detect_work);
724
725 return 0;
726}
727
728static const struct sdw_device_id rt5682_id[] = {
729 SDW_SLAVE_ENTRY_EXT(0x025d, 0x5682, 0x2, 0, 0),
730 {},
731};
732MODULE_DEVICE_TABLE(sdw, rt5682_id);
733
734static int __maybe_unused rt5682_dev_suspend(struct device *dev)
735{
736 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
737
738 if (!rt5682->hw_init)
739 return 0;
740
741 cancel_delayed_work_sync(&rt5682->jack_detect_work);
742
743 regcache_cache_only(rt5682->regmap, true);
744 regcache_mark_dirty(rt5682->regmap);
745
746 return 0;
747}
748
749static int __maybe_unused rt5682_dev_system_suspend(struct device *dev)
750{
751 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
752 struct sdw_slave *slave = dev_to_sdw_dev(dev);
753 int ret;
754
755 if (!rt5682->hw_init)
756 return 0;
757
758
759
760
761
762
763 mutex_lock(&rt5682->disable_irq_lock);
764 rt5682->disable_irq = true;
765 ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1,
766 SDW_SCP_INT1_IMPL_DEF, 0);
767 mutex_unlock(&rt5682->disable_irq_lock);
768
769 if (ret < 0) {
770
771 dev_dbg(&slave->dev, "%s: could not disable imp-def interrupts\n:", __func__);
772 }
773
774 return rt5682_dev_suspend(dev);
775}
776
777static int __maybe_unused rt5682_dev_resume(struct device *dev)
778{
779 struct sdw_slave *slave = dev_to_sdw_dev(dev);
780 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
781 unsigned long time;
782
783 if (!rt5682->first_hw_init)
784 return 0;
785
786 if (!slave->unattach_request)
787 goto regmap_sync;
788
789 time = wait_for_completion_timeout(&slave->initialization_complete,
790 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
791 if (!time) {
792 dev_err(&slave->dev, "Initialization not complete, timed out\n");
793 return -ETIMEDOUT;
794 }
795
796regmap_sync:
797 slave->unattach_request = 0;
798 regcache_cache_only(rt5682->regmap, false);
799 regcache_sync(rt5682->regmap);
800
801 return 0;
802}
803
804static const struct dev_pm_ops rt5682_pm = {
805 SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_system_suspend, rt5682_dev_resume)
806 SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
807};
808
809static struct sdw_driver rt5682_sdw_driver = {
810 .driver = {
811 .name = "rt5682",
812 .owner = THIS_MODULE,
813 .pm = &rt5682_pm,
814 },
815 .probe = rt5682_sdw_probe,
816 .remove = rt5682_sdw_remove,
817 .ops = &rt5682_slave_ops,
818 .id_table = rt5682_id,
819};
820module_sdw_driver(rt5682_sdw_driver);
821
822MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
823MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
824MODULE_LICENSE("GPL v2");
825
