1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14/* x86-64 specific MSRs */ 15#define MSR_EFER 0xc0000080 /* extended feature register */ 16#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25/* EFER bits: */ 26#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27#define _EFER_LME 8 /* Long mode enable */ 28#define _EFER_LMA 10 /* Long mode active (read-only) */ 29#define _EFER_NX 11 /* No execute enable */ 30#define _EFER_SVME 12 /* Enable virtualization */ 31#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34#define EFER_SCE (1<<_EFER_SCE) 35#define EFER_LME (1<<_EFER_LME) 36#define EFER_LMA (1<<_EFER_LMA) 37#define EFER_NX (1<<_EFER_NX) 38#define EFER_SVME (1<<_EFER_SVME) 39#define EFER_LMSLE (1<<_EFER_LMSLE) 40#define EFER_FFXSR (1<<_EFER_FFXSR) 41 42/* Intel MSRs. Some also available on other CPUs */ 43 44#define MSR_TEST_CTRL 0x00000033 45#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 55#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57 58#define MSR_PPIN_CTL 0x0000004e 59#define MSR_PPIN 0x0000004f 60 61#define MSR_IA32_PERFCTR0 0x000000c1 62#define MSR_IA32_PERFCTR1 0x000000c2 63#define MSR_FSB_FREQ 0x000000cd 64#define MSR_PLATFORM_INFO 0x000000ce 65#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67 68#define MSR_IA32_UMWAIT_CONTROL 0xe1 69#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71/* 72 * The time field is bit[31:2], but representing a 32bit value with 73 * bit[1:0] zero. 74 */ 75#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76 77/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78#define MSR_IA32_CORE_CAPS 0x000000cf 79#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 80#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 81 82#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83#define NHM_C3_AUTO_DEMOTE (1UL << 25) 84#define NHM_C1_AUTO_DEMOTE (1UL << 26) 85#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88 89#define MSR_MTRRcap 0x000000fe 90 91#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95#define ARCH_CAP_SSB_NO BIT(4) /* 96 * Not susceptible to Speculative Store Bypass 97 * attack, so no Speculative Store Bypass 98 * control required. 99 */ 100#define ARCH_CAP_MDS_NO BIT(5) /* 101 * Not susceptible to 102 * Microarchitectural Data 103 * Sampling (MDS) vulnerabilities. 104 */ 105#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 106 * The processor is not susceptible to a 107 * machine check error due to modifying the 108 * code page size along with either the 109 * physical address or cache type 110 * without TLB invalidation. 111 */ 112#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 113#define ARCH_CAP_TAA_NO BIT(8) /* 114 * Not susceptible to 115 * TSX Async Abort (TAA) vulnerabilities. 116 */ 117 118#define MSR_IA32_FLUSH_CMD 0x0000010b 119#define L1D_FLUSH BIT(0) /* 120 * Writeback and invalidate the 121 * L1 data cache. 122 */ 123 124#define MSR_IA32_BBL_CR_CTL 0x00000119 125#define MSR_IA32_BBL_CR_CTL3 0x0000011e 126 127#define MSR_IA32_TSX_CTRL 0x00000122 128#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 129#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 130 131#define MSR_IA32_SYSENTER_CS 0x00000174 132#define MSR_IA32_SYSENTER_ESP 0x00000175 133#define MSR_IA32_SYSENTER_EIP 0x00000176 134 135#define MSR_IA32_MCG_CAP 0x00000179 136#define MSR_IA32_MCG_STATUS 0x0000017a 137#define MSR_IA32_MCG_CTL 0x0000017b 138#define MSR_IA32_MCG_EXT_CTL 0x000004d0 139 140#define MSR_OFFCORE_RSP_0 0x000001a6 141#define MSR_OFFCORE_RSP_1 0x000001a7 142#define MSR_TURBO_RATIO_LIMIT 0x000001ad 143#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 144#define MSR_TURBO_RATIO_LIMIT2 0x000001af 145 146#define MSR_LBR_SELECT 0x000001c8 147#define MSR_LBR_TOS 0x000001c9 148 149#define MSR_IA32_POWER_CTL 0x000001fc 150#define MSR_IA32_POWER_CTL_BIT_EE 19 151 152#define MSR_LBR_NHM_FROM 0x00000680 153#define MSR_LBR_NHM_TO 0x000006c0 154#define MSR_LBR_CORE_FROM 0x00000040 155#define MSR_LBR_CORE_TO 0x00000060 156 157#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 158#define LBR_INFO_MISPRED BIT_ULL(63) 159#define LBR_INFO_IN_TX BIT_ULL(62) 160#define LBR_INFO_ABORT BIT_ULL(61) 161#define LBR_INFO_CYCLES 0xffff 162 163#define MSR_IA32_PEBS_ENABLE 0x000003f1 164#define MSR_PEBS_DATA_CFG 0x000003f2 165#define MSR_IA32_DS_AREA 0x00000600 166#define MSR_IA32_PERF_CAPABILITIES 0x00000345 167#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 168 169#define MSR_IA32_RTIT_CTL 0x00000570 170#define RTIT_CTL_TRACEEN BIT(0) 171#define RTIT_CTL_CYCLEACC BIT(1) 172#define RTIT_CTL_OS BIT(2) 173#define RTIT_CTL_USR BIT(3) 174#define RTIT_CTL_PWR_EVT_EN BIT(4) 175#define RTIT_CTL_FUP_ON_PTW BIT(5) 176#define RTIT_CTL_FABRIC_EN BIT(6) 177#define RTIT_CTL_CR3EN BIT(7) 178#define RTIT_CTL_TOPA BIT(8) 179#define RTIT_CTL_MTC_EN BIT(9) 180#define RTIT_CTL_TSC_EN BIT(10) 181#define RTIT_CTL_DISRETC BIT(11) 182#define RTIT_CTL_PTW_EN BIT(12) 183#define RTIT_CTL_BRANCH_EN BIT(13) 184#define RTIT_CTL_MTC_RANGE_OFFSET 14 185#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 186#define RTIT_CTL_CYC_THRESH_OFFSET 19 187#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 188#define RTIT_CTL_PSB_FREQ_OFFSET 24 189#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 190#define RTIT_CTL_ADDR0_OFFSET 32 191#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 192#define RTIT_CTL_ADDR1_OFFSET 36 193#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 194#define RTIT_CTL_ADDR2_OFFSET 40 195#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 196#define RTIT_CTL_ADDR3_OFFSET 44 197#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 198#define MSR_IA32_RTIT_STATUS 0x00000571 199#define RTIT_STATUS_FILTEREN BIT(0) 200#define RTIT_STATUS_CONTEXTEN BIT(1) 201#define RTIT_STATUS_TRIGGEREN BIT(2) 202#define RTIT_STATUS_BUFFOVF BIT(3) 203#define RTIT_STATUS_ERROR BIT(4) 204#define RTIT_STATUS_STOPPED BIT(5) 205#define RTIT_STATUS_BYTECNT_OFFSET 32 206#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 207#define MSR_IA32_RTIT_ADDR0_A 0x00000580 208#define MSR_IA32_RTIT_ADDR0_B 0x00000581 209#define MSR_IA32_RTIT_ADDR1_A 0x00000582 210#define MSR_IA32_RTIT_ADDR1_B 0x00000583 211#define MSR_IA32_RTIT_ADDR2_A 0x00000584 212#define MSR_IA32_RTIT_ADDR2_B 0x00000585 213#define MSR_IA32_RTIT_ADDR3_A 0x00000586 214#define MSR_IA32_RTIT_ADDR3_B 0x00000587 215#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 216#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 217#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 218 219#define MSR_MTRRfix64K_00000 0x00000250 220#define MSR_MTRRfix16K_80000 0x00000258 221#define MSR_MTRRfix16K_A0000 0x00000259 222#define MSR_MTRRfix4K_C0000 0x00000268 223#define MSR_MTRRfix4K_C8000 0x00000269 224#define MSR_MTRRfix4K_D0000 0x0000026a 225#define MSR_MTRRfix4K_D8000 0x0000026b 226#define MSR_MTRRfix4K_E0000 0x0000026c 227#define MSR_MTRRfix4K_E8000 0x0000026d 228#define MSR_MTRRfix4K_F0000 0x0000026e 229#define MSR_MTRRfix4K_F8000 0x0000026f 230#define MSR_MTRRdefType 0x000002ff 231 232#define MSR_IA32_CR_PAT 0x00000277 233 234#define MSR_IA32_DEBUGCTLMSR 0x000001d9 235#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 236#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 237#define MSR_IA32_LASTINTFROMIP 0x000001dd 238#define MSR_IA32_LASTINTTOIP 0x000001de 239 240/* DEBUGCTLMSR bits (others vary by model): */ 241#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 242#define DEBUGCTLMSR_BTF_SHIFT 1 243#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 244#define DEBUGCTLMSR_TR (1UL << 6) 245#define DEBUGCTLMSR_BTS (1UL << 7) 246#define DEBUGCTLMSR_BTINT (1UL << 8) 247#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 248#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 249#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 250#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 251#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 252#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 253 254#define MSR_PEBS_FRONTEND 0x000003f7 255 256#define MSR_IA32_MC0_CTL 0x00000400 257#define MSR_IA32_MC0_STATUS 0x00000401 258#define MSR_IA32_MC0_ADDR 0x00000402 259#define MSR_IA32_MC0_MISC 0x00000403 260 261/* C-state Residency Counters */ 262#define MSR_PKG_C3_RESIDENCY 0x000003f8 263#define MSR_PKG_C6_RESIDENCY 0x000003f9 264#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 265#define MSR_PKG_C7_RESIDENCY 0x000003fa 266#define MSR_CORE_C3_RESIDENCY 0x000003fc 267#define MSR_CORE_C6_RESIDENCY 0x000003fd 268#define MSR_CORE_C7_RESIDENCY 0x000003fe 269#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 270#define MSR_PKG_C2_RESIDENCY 0x0000060d 271#define MSR_PKG_C8_RESIDENCY 0x00000630 272#define MSR_PKG_C9_RESIDENCY 0x00000631 273#define MSR_PKG_C10_RESIDENCY 0x00000632 274 275/* Interrupt Response Limit */ 276#define MSR_PKGC3_IRTL 0x0000060a 277#define MSR_PKGC6_IRTL 0x0000060b 278#define MSR_PKGC7_IRTL 0x0000060c 279#define MSR_PKGC8_IRTL 0x00000633 280#define MSR_PKGC9_IRTL 0x00000634 281#define MSR_PKGC10_IRTL 0x00000635 282 283/* Run Time Average Power Limiting (RAPL) Interface */ 284 285#define MSR_RAPL_POWER_UNIT 0x00000606 286 287#define MSR_PKG_POWER_LIMIT 0x00000610 288#define MSR_PKG_ENERGY_STATUS 0x00000611 289#define MSR_PKG_PERF_STATUS 0x00000613 290#define MSR_PKG_POWER_INFO 0x00000614 291 292#define MSR_DRAM_POWER_LIMIT 0x00000618 293#define MSR_DRAM_ENERGY_STATUS 0x00000619 294#define MSR_DRAM_PERF_STATUS 0x0000061b 295#define MSR_DRAM_POWER_INFO 0x0000061c 296 297#define MSR_PP0_POWER_LIMIT 0x00000638 298#define MSR_PP0_ENERGY_STATUS 0x00000639 299#define MSR_PP0_POLICY 0x0000063a 300#define MSR_PP0_PERF_STATUS 0x0000063b 301 302#define MSR_PP1_POWER_LIMIT 0x00000640 303#define MSR_PP1_ENERGY_STATUS 0x00000641 304#define MSR_PP1_POLICY 0x00000642 305 306#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 307#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 308#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 309 310/* Config TDP MSRs */ 311#define MSR_CONFIG_TDP_NOMINAL 0x00000648 312#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 313#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 314#define MSR_CONFIG_TDP_CONTROL 0x0000064B 315#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 316 317#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 318 319#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 320#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 321#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 322#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 323 324#define MSR_CORE_C1_RES 0x00000660 325#define MSR_MODULE_C6_RES_MS 0x00000664 326 327#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 328#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 329 330#define MSR_ATOM_CORE_RATIOS 0x0000066a 331#define MSR_ATOM_CORE_VIDS 0x0000066b 332#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 333#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 334 335 336#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 337#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 338#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 339 340/* Hardware P state interface */ 341#define MSR_PPERF 0x0000064e 342#define MSR_PERF_LIMIT_REASONS 0x0000064f 343#define MSR_PM_ENABLE 0x00000770 344#define MSR_HWP_CAPABILITIES 0x00000771 345#define MSR_HWP_REQUEST_PKG 0x00000772 346#define MSR_HWP_INTERRUPT 0x00000773 347#define MSR_HWP_REQUEST 0x00000774 348#define MSR_HWP_STATUS 0x00000777 349 350/* CPUID.6.EAX */ 351#define HWP_BASE_BIT (1<<7) 352#define HWP_NOTIFICATIONS_BIT (1<<8) 353#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 354#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 355#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 356 357/* IA32_HWP_CAPABILITIES */ 358#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 359#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 360#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 361#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 362 363/* IA32_HWP_REQUEST */ 364#define HWP_MIN_PERF(x) (x & 0xff) 365#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 366#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 367#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 368#define HWP_EPP_PERFORMANCE 0x00 369#define HWP_EPP_BALANCE_PERFORMANCE 0x80 370#define HWP_EPP_BALANCE_POWERSAVE 0xC0 371#define HWP_EPP_POWERSAVE 0xFF 372#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 373#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 374 375/* IA32_HWP_STATUS */ 376#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 377#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 378 379/* IA32_HWP_INTERRUPT */ 380#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 381#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 382 383#define MSR_AMD64_MC0_MASK 0xc0010044 384 385#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 386#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 387#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 388#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 389 390#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 391 392/* These are consecutive and not in the normal 4er MCE bank block */ 393#define MSR_IA32_MC0_CTL2 0x00000280 394#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 395 396#define MSR_P6_PERFCTR0 0x000000c1 397#define MSR_P6_PERFCTR1 0x000000c2 398#define MSR_P6_EVNTSEL0 0x00000186 399#define MSR_P6_EVNTSEL1 0x00000187 400 401#define MSR_KNC_PERFCTR0 0x00000020 402#define MSR_KNC_PERFCTR1 0x00000021 403#define MSR_KNC_EVNTSEL0 0x00000028 404#define MSR_KNC_EVNTSEL1 0x00000029 405 406/* Alternative perfctr range with full access. */ 407#define MSR_IA32_PMC0 0x000004c1 408 409/* Auto-reload via MSR instead of DS area */ 410#define MSR_RELOAD_PMC0 0x000014c1 411#define MSR_RELOAD_FIXED_CTR0 0x00001309 412 413/* AMD64 MSRs. Not complete. See the architecture manual for a more 414 complete list. */ 415 416#define MSR_AMD64_PATCH_LEVEL 0x0000008b 417#define MSR_AMD64_TSC_RATIO 0xc0000104 418#define MSR_AMD64_NB_CFG 0xc001001f 419#define MSR_AMD64_PATCH_LOADER 0xc0010020 420#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 421#define MSR_AMD64_OSVW_STATUS 0xc0010141 422#define MSR_AMD64_LS_CFG 0xc0011020 423#define MSR_AMD64_DC_CFG 0xc0011022 424#define MSR_AMD64_BU_CFG2 0xc001102a 425#define MSR_AMD64_IBSFETCHCTL 0xc0011030 426#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 427#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 428#define MSR_AMD64_IBSFETCH_REG_COUNT 3 429#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 430#define MSR_AMD64_IBSOPCTL 0xc0011033 431#define MSR_AMD64_IBSOPRIP 0xc0011034 432#define MSR_AMD64_IBSOPDATA 0xc0011035 433#define MSR_AMD64_IBSOPDATA2 0xc0011036 434#define MSR_AMD64_IBSOPDATA3 0xc0011037 435#define MSR_AMD64_IBSDCLINAD 0xc0011038 436#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 437#define MSR_AMD64_IBSOP_REG_COUNT 7 438#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 439#define MSR_AMD64_IBSCTL 0xc001103a 440#define MSR_AMD64_IBSBRTARGET 0xc001103b 441#define MSR_AMD64_IBSOPDATA4 0xc001103d 442#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 443#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 444#define MSR_AMD64_SEV 0xc0010131 445#define MSR_AMD64_SEV_ENABLED_BIT 0 446#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 447 448#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 449 450/* Fam 17h MSRs */ 451#define MSR_F17H_IRPERF 0xc00000e9 452 453/* Fam 16h MSRs */ 454#define MSR_F16H_L2I_PERF_CTL 0xc0010230 455#define MSR_F16H_L2I_PERF_CTR 0xc0010231 456#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 457#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 458#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 459#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 460 461/* Fam 15h MSRs */ 462#define MSR_F15H_PERF_CTL 0xc0010200 463#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 464#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 465#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 466#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 467#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 468#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 469 470#define MSR_F15H_PERF_CTR 0xc0010201 471#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 472#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 473#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 474#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 475#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 476#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 477 478#define MSR_F15H_NB_PERF_CTL 0xc0010240 479#define MSR_F15H_NB_PERF_CTR 0xc0010241 480#define MSR_F15H_PTSC 0xc0010280 481#define MSR_F15H_IC_CFG 0xc0011021 482#define MSR_F15H_EX_CFG 0xc001102c 483 484/* Fam 10h MSRs */ 485#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 486#define FAM10H_MMIO_CONF_ENABLE (1<<0) 487#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 488#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 489#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 490#define FAM10H_MMIO_CONF_BASE_SHIFT 20 491#define MSR_FAM10H_NODE_ID 0xc001100c 492#define MSR_F10H_DECFG 0xc0011029 493#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 494#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 495 496/* K8 MSRs */ 497#define MSR_K8_TOP_MEM1 0xc001001a 498#define MSR_K8_TOP_MEM2 0xc001001d 499#define MSR_AMD64_SYSCFG 0xc0010010 500#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 501#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 502#define MSR_K8_INT_PENDING_MSG 0xc0010055 503/* C1E active bits in int pending message */ 504#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 505#define MSR_K8_TSEG_ADDR 0xc0010112 506#define MSR_K8_TSEG_MASK 0xc0010113 507#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 508#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 509#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 510 511/* K7 MSRs */ 512#define MSR_K7_EVNTSEL0 0xc0010000 513#define MSR_K7_PERFCTR0 0xc0010004 514#define MSR_K7_EVNTSEL1 0xc0010001 515#define MSR_K7_PERFCTR1 0xc0010005 516#define MSR_K7_EVNTSEL2 0xc0010002 517#define MSR_K7_PERFCTR2 0xc0010006 518#define MSR_K7_EVNTSEL3 0xc0010003 519#define MSR_K7_PERFCTR3 0xc0010007 520#define MSR_K7_CLK_CTL 0xc001001b 521#define MSR_K7_HWCR 0xc0010015 522#define MSR_K7_HWCR_SMMLOCK_BIT 0 523#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 524#define MSR_K7_FID_VID_CTL 0xc0010041 525#define MSR_K7_FID_VID_STATUS 0xc0010042 526 527/* K6 MSRs */ 528#define MSR_K6_WHCR 0xc0000082 529#define MSR_K6_UWCCR 0xc0000085 530#define MSR_K6_EPMR 0xc0000086 531#define MSR_K6_PSOR 0xc0000087 532#define MSR_K6_PFIR 0xc0000088 533 534/* Centaur-Hauls/IDT defined MSRs. */ 535#define MSR_IDT_FCR1 0x00000107 536#define MSR_IDT_FCR2 0x00000108 537#define MSR_IDT_FCR3 0x00000109 538#define MSR_IDT_FCR4 0x0000010a 539 540#define MSR_IDT_MCR0 0x00000110 541#define MSR_IDT_MCR1 0x00000111 542#define MSR_IDT_MCR2 0x00000112 543#define MSR_IDT_MCR3 0x00000113 544#define MSR_IDT_MCR4 0x00000114 545#define MSR_IDT_MCR5 0x00000115 546#define MSR_IDT_MCR6 0x00000116 547#define MSR_IDT_MCR7 0x00000117 548#define MSR_IDT_MCR_CTRL 0x00000120 549 550/* VIA Cyrix defined MSRs*/ 551#define MSR_VIA_FCR 0x00001107 552#define MSR_VIA_LONGHAUL 0x0000110a 553#define MSR_VIA_RNG 0x0000110b 554#define MSR_VIA_BCR2 0x00001147 555 556/* Transmeta defined MSRs */ 557#define MSR_TMTA_LONGRUN_CTRL 0x80868010 558#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 559#define MSR_TMTA_LRTI_READOUT 0x80868018 560#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 561 562/* Intel defined MSRs. */ 563#define MSR_IA32_P5_MC_ADDR 0x00000000 564#define MSR_IA32_P5_MC_TYPE 0x00000001 565#define MSR_IA32_TSC 0x00000010 566#define MSR_IA32_PLATFORM_ID 0x00000017 567#define MSR_IA32_EBL_CR_POWERON 0x0000002a 568#define MSR_EBC_FREQUENCY_ID 0x0000002c 569#define MSR_SMI_COUNT 0x00000034 570 571/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 572#define MSR_IA32_FEAT_CTL 0x0000003a 573#define FEAT_CTL_LOCKED BIT(0) 574#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 575#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 576#define FEAT_CTL_SGX_LC_ENABLED BIT(17) 577#define FEAT_CTL_SGX_ENABLED BIT(18) 578#define FEAT_CTL_LMCE_ENABLED BIT(20) 579 580#define MSR_IA32_TSC_ADJUST 0x0000003b 581#define MSR_IA32_BNDCFGS 0x00000d90 582 583#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 584 585#define MSR_IA32_XSS 0x00000da0 586 587#define MSR_IA32_APICBASE 0x0000001b 588#define MSR_IA32_APICBASE_BSP (1<<8) 589#define MSR_IA32_APICBASE_ENABLE (1<<11) 590#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 591 592#define MSR_IA32_UCODE_WRITE 0x00000079 593#define MSR_IA32_UCODE_REV 0x0000008b 594 595/* Intel SGX Launch Enclave Public Key Hash MSRs */ 596#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 597#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 598#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 599#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 600 601#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 602#define MSR_IA32_SMBASE 0x0000009e 603 604#define MSR_IA32_PERF_STATUS 0x00000198 605#define MSR_IA32_PERF_CTL 0x00000199 606#define INTEL_PERF_CTL_MASK 0xffff 607#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 608#define MSR_AMD_PERF_STATUS 0xc0010063 609#define MSR_AMD_PERF_CTL 0xc0010062 610 611#define MSR_IA32_MPERF 0x000000e7 612#define MSR_IA32_APERF 0x000000e8 613 614#define MSR_IA32_THERM_CONTROL 0x0000019a 615#define MSR_IA32_THERM_INTERRUPT 0x0000019b 616 617#define THERM_INT_HIGH_ENABLE (1 << 0) 618#define THERM_INT_LOW_ENABLE (1 << 1) 619#define THERM_INT_PLN_ENABLE (1 << 24) 620 621#define MSR_IA32_THERM_STATUS 0x0000019c 622 623#define THERM_STATUS_PROCHOT (1 << 0) 624#define THERM_STATUS_POWER_LIMIT (1 << 10) 625 626#define MSR_THERM2_CTL 0x0000019d 627 628#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 629 630#define MSR_IA32_MISC_ENABLE 0x000001a0 631 632#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 633 634#define MSR_MISC_FEATURE_CONTROL 0x000001a4 635#define MSR_MISC_PWR_MGMT 0x000001aa 636 637#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 638#define ENERGY_PERF_BIAS_PERFORMANCE 0 639#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 640#define ENERGY_PERF_BIAS_NORMAL 6 641#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 642#define ENERGY_PERF_BIAS_POWERSAVE 15 643 644#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 645 646#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 647#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 648 649#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 650 651#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 652#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 653#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 654 655/* Thermal Thresholds Support */ 656#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 657#define THERM_SHIFT_THRESHOLD0 8 658#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 659#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 660#define THERM_SHIFT_THRESHOLD1 16 661#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 662#define THERM_STATUS_THRESHOLD0 (1 << 6) 663#define THERM_LOG_THRESHOLD0 (1 << 7) 664#define THERM_STATUS_THRESHOLD1 (1 << 8) 665#define THERM_LOG_THRESHOLD1 (1 << 9) 666 667/* MISC_ENABLE bits: architectural */ 668#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 669#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 670#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 671#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 672#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 673#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 674#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 675#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 676#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 677#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 678#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 679#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 680#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 681#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 682#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 683#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 684#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 685#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 686#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 687#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 688 689/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 690#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 691#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 692#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 693#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 694#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 695#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 696#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 697#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 698#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 699#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 700#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 701#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 702#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 703#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 704#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 705#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 706#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 707#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 708#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 709#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 710#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 711#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 712#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 713#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 714#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 715#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 716#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 717#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 718#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 719#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 720 721/* MISC_FEATURES_ENABLES non-architectural features */ 722#define MSR_MISC_FEATURES_ENABLES 0x00000140 723 724#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 725#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 726#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 727 728#define MSR_IA32_TSC_DEADLINE 0x000006E0 729 730 731#define MSR_TSX_FORCE_ABORT 0x0000010F 732 733#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 734#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 735 736/* P4/Xeon+ specific */ 737#define MSR_IA32_MCG_EAX 0x00000180 738#define MSR_IA32_MCG_EBX 0x00000181 739#define MSR_IA32_MCG_ECX 0x00000182 740#define MSR_IA32_MCG_EDX 0x00000183 741#define MSR_IA32_MCG_ESI 0x00000184 742#define MSR_IA32_MCG_EDI 0x00000185 743#define MSR_IA32_MCG_EBP 0x00000186 744#define MSR_IA32_MCG_ESP 0x00000187 745#define MSR_IA32_MCG_EFLAGS 0x00000188 746#define MSR_IA32_MCG_EIP 0x00000189 747#define MSR_IA32_MCG_RESERVED 0x0000018a 748 749/* Pentium IV performance counter MSRs */ 750#define MSR_P4_BPU_PERFCTR0 0x00000300 751#define MSR_P4_BPU_PERFCTR1 0x00000301 752#define MSR_P4_BPU_PERFCTR2 0x00000302 753#define MSR_P4_BPU_PERFCTR3 0x00000303 754#define MSR_P4_MS_PERFCTR0 0x00000304 755#define MSR_P4_MS_PERFCTR1 0x00000305 756#define MSR_P4_MS_PERFCTR2 0x00000306 757#define MSR_P4_MS_PERFCTR3 0x00000307 758#define MSR_P4_FLAME_PERFCTR0 0x00000308 759#define MSR_P4_FLAME_PERFCTR1 0x00000309 760#define MSR_P4_FLAME_PERFCTR2 0x0000030a 761#define MSR_P4_FLAME_PERFCTR3 0x0000030b 762#define MSR_P4_IQ_PERFCTR0 0x0000030c 763#define MSR_P4_IQ_PERFCTR1 0x0000030d 764#define MSR_P4_IQ_PERFCTR2 0x0000030e 765#define MSR_P4_IQ_PERFCTR3 0x0000030f 766#define MSR_P4_IQ_PERFCTR4 0x00000310 767#define MSR_P4_IQ_PERFCTR5 0x00000311 768#define MSR_P4_BPU_CCCR0 0x00000360 769#define MSR_P4_BPU_CCCR1 0x00000361 770#define MSR_P4_BPU_CCCR2 0x00000362 771#define MSR_P4_BPU_CCCR3 0x00000363 772#define MSR_P4_MS_CCCR0 0x00000364 773#define MSR_P4_MS_CCCR1 0x00000365 774#define MSR_P4_MS_CCCR2 0x00000366 775#define MSR_P4_MS_CCCR3 0x00000367 776#define MSR_P4_FLAME_CCCR0 0x00000368 777#define MSR_P4_FLAME_CCCR1 0x00000369 778#define MSR_P4_FLAME_CCCR2 0x0000036a 779#define MSR_P4_FLAME_CCCR3 0x0000036b 780#define MSR_P4_IQ_CCCR0 0x0000036c 781#define MSR_P4_IQ_CCCR1 0x0000036d 782#define MSR_P4_IQ_CCCR2 0x0000036e 783#define MSR_P4_IQ_CCCR3 0x0000036f 784#define MSR_P4_IQ_CCCR4 0x00000370 785#define MSR_P4_IQ_CCCR5 0x00000371 786#define MSR_P4_ALF_ESCR0 0x000003ca 787#define MSR_P4_ALF_ESCR1 0x000003cb 788#define MSR_P4_BPU_ESCR0 0x000003b2 789#define MSR_P4_BPU_ESCR1 0x000003b3 790#define MSR_P4_BSU_ESCR0 0x000003a0 791#define MSR_P4_BSU_ESCR1 0x000003a1 792#define MSR_P4_CRU_ESCR0 0x000003b8 793#define MSR_P4_CRU_ESCR1 0x000003b9 794#define MSR_P4_CRU_ESCR2 0x000003cc 795#define MSR_P4_CRU_ESCR3 0x000003cd 796#define MSR_P4_CRU_ESCR4 0x000003e0 797#define MSR_P4_CRU_ESCR5 0x000003e1 798#define MSR_P4_DAC_ESCR0 0x000003a8 799#define MSR_P4_DAC_ESCR1 0x000003a9 800#define MSR_P4_FIRM_ESCR0 0x000003a4 801#define MSR_P4_FIRM_ESCR1 0x000003a5 802#define MSR_P4_FLAME_ESCR0 0x000003a6 803#define MSR_P4_FLAME_ESCR1 0x000003a7 804#define MSR_P4_FSB_ESCR0 0x000003a2 805#define MSR_P4_FSB_ESCR1 0x000003a3 806#define MSR_P4_IQ_ESCR0 0x000003ba 807#define MSR_P4_IQ_ESCR1 0x000003bb 808#define MSR_P4_IS_ESCR0 0x000003b4 809#define MSR_P4_IS_ESCR1 0x000003b5 810#define MSR_P4_ITLB_ESCR0 0x000003b6 811#define MSR_P4_ITLB_ESCR1 0x000003b7 812#define MSR_P4_IX_ESCR0 0x000003c8 813#define MSR_P4_IX_ESCR1 0x000003c9 814#define MSR_P4_MOB_ESCR0 0x000003aa 815#define MSR_P4_MOB_ESCR1 0x000003ab 816#define MSR_P4_MS_ESCR0 0x000003c0 817#define MSR_P4_MS_ESCR1 0x000003c1 818#define MSR_P4_PMH_ESCR0 0x000003ac 819#define MSR_P4_PMH_ESCR1 0x000003ad 820#define MSR_P4_RAT_ESCR0 0x000003bc 821#define MSR_P4_RAT_ESCR1 0x000003bd 822#define MSR_P4_SAAT_ESCR0 0x000003ae 823#define MSR_P4_SAAT_ESCR1 0x000003af 824#define MSR_P4_SSU_ESCR0 0x000003be 825#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 826 827#define MSR_P4_TBPU_ESCR0 0x000003c2 828#define MSR_P4_TBPU_ESCR1 0x000003c3 829#define MSR_P4_TC_ESCR0 0x000003c4 830#define MSR_P4_TC_ESCR1 0x000003c5 831#define MSR_P4_U2L_ESCR0 0x000003b0 832#define MSR_P4_U2L_ESCR1 0x000003b1 833 834#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 835 836/* Intel Core-based CPU performance counters */ 837#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 838#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 839#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 840#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 841#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 842#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 843#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 844 845/* PERF_GLOBAL_OVF_CTL bits */ 846#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 847#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 848#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 849#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 850#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 851#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 852 853/* Geode defined MSRs */ 854#define MSR_GEODE_BUSCONT_CONF0 0x00001900 855 856/* Intel VT MSRs */ 857#define MSR_IA32_VMX_BASIC 0x00000480 858#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 859#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 860#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 861#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 862#define MSR_IA32_VMX_MISC 0x00000485 863#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 864#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 865#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 866#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 867#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 868#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 869#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 870#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 871#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 872#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 873#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 874#define MSR_IA32_VMX_VMFUNC 0x00000491 875 876/* VMX_BASIC bits and bitmasks */ 877#define VMX_BASIC_VMCS_SIZE_SHIFT 32 878#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 879#define VMX_BASIC_64 0x0001000000000000LLU 880#define VMX_BASIC_MEM_TYPE_SHIFT 50 881#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 882#define VMX_BASIC_MEM_TYPE_WB 6LLU 883#define VMX_BASIC_INOUT 0x0040000000000000LLU 884 885/* MSR_IA32_VMX_MISC bits */ 886#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 887#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 888#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 889/* AMD-V MSRs */ 890 891#define MSR_VM_CR 0xc0010114 892#define MSR_VM_IGNNE 0xc0010115 893#define MSR_VM_HSAVE_PA 0xc0010117 894 895#endif /* _ASM_X86_MSR_INDEX_H */ 896