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31#define _FP_W_TYPE_SIZE 32
32#define _FP_W_TYPE unsigned int
33#define _FP_WS_TYPE signed int
34#define _FP_I_TYPE int
35
36#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
38#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
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82#define _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
83#define _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
84
85#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y)
86#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
87
88
89
90
91#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
92#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
93#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
94#define _FP_NANSIGN_S 0
95#define _FP_NANSIGN_D 0
96#define _FP_NANSIGN_Q 0
97
98#define _FP_KEEPNANFRACP 1
99
100#ifdef FP_EX_BOOKE_E500_SPE
101#define FP_EX_INEXACT (1 << 21)
102#define FP_EX_INVALID (1 << 20)
103#define FP_EX_DIVZERO (1 << 19)
104#define FP_EX_UNDERFLOW (1 << 18)
105#define FP_EX_OVERFLOW (1 << 17)
106#define FP_INHIBIT_RESULTS 0
107
108#define __FPU_FPSCR (current->thread.spefscr)
109#define __FPU_ENABLED_EXC \
110({ \
111 (__FPU_FPSCR >> 2) & 0x1f; \
112})
113#else
114
115
116
117#define FP_EX_INVALID (1 << (31 - 2))
118#define FP_EX_INVALID_SNAN EFLAG_VXSNAN
119#define FP_EX_INVALID_ISI EFLAG_VXISI
120#define FP_EX_INVALID_IDI EFLAG_VXIDI
121#define FP_EX_INVALID_ZDZ EFLAG_VXZDZ
122#define FP_EX_INVALID_IMZ EFLAG_VXIMZ
123#define FP_EX_OVERFLOW (1 << (31 - 3))
124#define FP_EX_UNDERFLOW (1 << (31 - 4))
125#define FP_EX_DIVZERO (1 << (31 - 5))
126#define FP_EX_INEXACT (1 << (31 - 6))
127
128#define __FPU_FPSCR (current->thread.fp_state.fpscr)
129
130
131
132
133#define __FPU_ENABLED_EXC \
134({ \
135 (__FPU_FPSCR >> 3) & 0x1f; \
136})
137
138#endif
139
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143
144#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
145 do { \
146 if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
147 && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
148 { \
149 R##_s = X##_s; \
150 _FP_FRAC_COPY_##wc(R,X); \
151 } \
152 else \
153 { \
154 R##_s = Y##_s; \
155 _FP_FRAC_COPY_##wc(R,Y); \
156 } \
157 R##_c = FP_CLS_NAN; \
158 } while (0)
159
160
161#include <linux/kernel.h>
162#include <linux/sched.h>
163
164#define __FPU_TRAP_P(bits) \
165 ((__FPU_ENABLED_EXC & (bits)) != 0)
166
167#define __FP_PACK_S(val,X) \
168({ int __exc = _FP_PACK_CANONICAL(S,1,X); \
169 if(!__exc || !__FPU_TRAP_P(__exc)) \
170 _FP_PACK_RAW_1_P(S,val,X); \
171 __exc; \
172})
173
174#define __FP_PACK_D(val,X) \
175 do { \
176 _FP_PACK_CANONICAL(D, 2, X); \
177 if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) \
178 _FP_PACK_RAW_2_P(D, val, X); \
179 } while (0)
180
181#define __FP_PACK_DS(val,X) \
182 do { \
183 FP_DECL_S(__X); \
184 FP_CONV(S, D, 1, 2, __X, X); \
185 _FP_PACK_CANONICAL(S, 1, __X); \
186 if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) { \
187 _FP_UNPACK_CANONICAL(S, 1, __X); \
188 FP_CONV(D, S, 2, 1, X, __X); \
189 _FP_PACK_CANONICAL(D, 2, X); \
190 if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) \
191 _FP_PACK_RAW_2_P(D, val, X); \
192 } \
193 } while (0)
194
195
196#define FP_ROUNDMODE \
197({ \
198 __FPU_FPSCR & 0x3; \
199})
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204
205#include <linux/types.h>
206#include <asm/byteorder.h>
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215
216#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
217 do { \
218 if (__builtin_constant_p (bh) && (bh) == 0) \
219 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
220 : "=r" ((USItype)(sh)), \
221 "=&r" ((USItype)(sl)) \
222 : "%r" ((USItype)(ah)), \
223 "%r" ((USItype)(al)), \
224 "rI" ((USItype)(bl))); \
225 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
226 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
227 : "=r" ((USItype)(sh)), \
228 "=&r" ((USItype)(sl)) \
229 : "%r" ((USItype)(ah)), \
230 "%r" ((USItype)(al)), \
231 "rI" ((USItype)(bl))); \
232 else \
233 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
234 : "=r" ((USItype)(sh)), \
235 "=&r" ((USItype)(sl)) \
236 : "%r" ((USItype)(ah)), \
237 "r" ((USItype)(bh)), \
238 "%r" ((USItype)(al)), \
239 "rI" ((USItype)(bl))); \
240 } while (0)
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251#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
252 do { \
253 if (__builtin_constant_p (ah) && (ah) == 0) \
254 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
255 : "=r" ((USItype)(sh)), \
256 "=&r" ((USItype)(sl)) \
257 : "r" ((USItype)(bh)), \
258 "rI" ((USItype)(al)), \
259 "r" ((USItype)(bl))); \
260 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
261 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
262 : "=r" ((USItype)(sh)), \
263 "=&r" ((USItype)(sl)) \
264 : "r" ((USItype)(bh)), \
265 "rI" ((USItype)(al)), \
266 "r" ((USItype)(bl))); \
267 else if (__builtin_constant_p (bh) && (bh) == 0) \
268 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
269 : "=r" ((USItype)(sh)), \
270 "=&r" ((USItype)(sl)) \
271 : "r" ((USItype)(ah)), \
272 "rI" ((USItype)(al)), \
273 "r" ((USItype)(bl))); \
274 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
275 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
276 : "=r" ((USItype)(sh)), \
277 "=&r" ((USItype)(sl)) \
278 : "r" ((USItype)(ah)), \
279 "rI" ((USItype)(al)), \
280 "r" ((USItype)(bl))); \
281 else \
282 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
283 : "=r" ((USItype)(sh)), \
284 "=&r" ((USItype)(sl)) \
285 : "r" ((USItype)(ah)), \
286 "r" ((USItype)(bh)), \
287 "rI" ((USItype)(al)), \
288 "r" ((USItype)(bl))); \
289 } while (0)
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296
297#define umul_ppmm(ph, pl, m0, m1) \
298 do { \
299 USItype __m0 = (m0), __m1 = (m1); \
300 __asm__ ("mulhwu %0,%1,%2" \
301 : "=r" ((USItype)(ph)) \
302 : "%r" (__m0), \
303 "r" (__m1)); \
304 (pl) = __m0 * __m1; \
305 } while (0)
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314
315#define udiv_qrnnd(q, r, n1, n0, d) \
316 do { \
317 UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
318 __d1 = __ll_highpart (d); \
319 __d0 = __ll_lowpart (d); \
320 \
321 __r1 = (n1) % __d1; \
322 __q1 = (n1) / __d1; \
323 __m = (UWtype) __q1 * __d0; \
324 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
325 if (__r1 < __m) \
326 { \
327 __q1--, __r1 += (d); \
328 if (__r1 >= (d)) \
329 if (__r1 < __m) \
330 __q1--, __r1 += (d); \
331 } \
332 __r1 -= __m; \
333 \
334 __r0 = __r1 % __d1; \
335 __q0 = __r1 / __d1; \
336 __m = (UWtype) __q0 * __d0; \
337 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
338 if (__r0 < __m) \
339 { \
340 __q0--, __r0 += (d); \
341 if (__r0 >= (d)) \
342 if (__r0 < __m) \
343 __q0--, __r0 += (d); \
344 } \
345 __r0 -= __m; \
346 \
347 (q) = (UWtype) __q1 * __ll_B | __q0; \
348 (r) = __r0; \
349 } while (0)
350
351#define UDIV_NEEDS_NORMALIZATION 1
352
353#define abort() \
354 return 0
355
356#ifdef __BIG_ENDIAN
357#define __BYTE_ORDER __BIG_ENDIAN
358#else
359#define __BYTE_ORDER __LITTLE_ENDIAN
360#endif
361
362
363#define EFLAG_INVALID (1 << (31 - 2))
364#define EFLAG_OVERFLOW (1 << (31 - 3))
365#define EFLAG_UNDERFLOW (1 << (31 - 4))
366#define EFLAG_DIVZERO (1 << (31 - 5))
367#define EFLAG_INEXACT (1 << (31 - 6))
368
369#define EFLAG_VXSNAN (1 << (31 - 7))
370#define EFLAG_VXISI (1 << (31 - 8))
371#define EFLAG_VXIDI (1 << (31 - 9))
372#define EFLAG_VXZDZ (1 << (31 - 10))
373#define EFLAG_VXIMZ (1 << (31 - 11))
374#define EFLAG_VXVC (1 << (31 - 12))
375#define EFLAG_VXSOFT (1 << (31 - 21))
376#define EFLAG_VXSQRT (1 << (31 - 22))
377#define EFLAG_VXCVI (1 << (31 - 23))
378