LXR linux/arch/xtensa/mm/mmu.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xtensa mmu stuff
   4 *
   5 * Extracted from init.c
   6 */
   7#include <linux/bootmem.h>
   8#include <linux/percpu.h>
   9#include <linux/init.h>
  10#include <linux/string.h>
  11#include <linux/slab.h>
  12#include <linux/cache.h>
  13
  14#include <asm/tlb.h>
  15#include <asm/tlbflush.h>
  16#include <asm/mmu_context.h>
  17#include <asm/page.h>
  18#include <asm/initialize_mmu.h>
  19#include <asm/io.h>
  20
  21#if defined(CONFIG_HIGHMEM)
  22static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
  23{
  24        pgd_t *pgd = pgd_offset_k(vaddr);
  25        pmd_t *pmd = pmd_offset(pgd, vaddr);
  26        pte_t *pte;
  27        unsigned long i;
  28
  29        n_pages = ALIGN(n_pages, PTRS_PER_PTE);
  30
  31        pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
  32                 __func__, vaddr, n_pages);
  33
  34        pte = alloc_bootmem_low_pages(n_pages * sizeof(pte_t));
  35
  36        for (i = 0; i < n_pages; ++i)
  37                pte_clear(NULL, 0, pte + i);
  38
  39        for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
  40                pte_t *cur_pte = pte + i;
  41
  42                BUG_ON(!pmd_none(*pmd));
  43                set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
  44                BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
  45                pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
  46                         __func__, pmd, cur_pte);
  47        }
  48        return pte;
  49}
  50
  51static void __init fixedrange_init(void)
  52{
  53        init_pmd(__fix_to_virt(0), __end_of_fixed_addresses);
  54}
  55#endif
  56
  57void __init paging_init(void)
  58{
  59#ifdef CONFIG_HIGHMEM
  60        fixedrange_init();
  61        pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
  62        kmap_init();
  63#endif
  64}
  65
  66/*
  67 * Flush the mmu and reset associated register to default values.
  68 */
  69void init_mmu(void)
  70{
  71#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
  72        /*
  73         * Writing zeros to the instruction and data TLBCFG special
  74         * registers ensure that valid values exist in the register.
  75         *
  76         * For existing PGSZID<w> fields, zero selects the first element
  77         * of the page-size array.  For nonexistent PGSZID<w> fields,
  78         * zero is the best value to write.  Also, when changing PGSZID<w>
  79         * fields, the corresponding TLB must be flushed.
  80         */
  81        set_itlbcfg_register(0);
  82        set_dtlbcfg_register(0);
  83#endif
  84        init_kio();
  85        local_flush_tlb_all();
  86
  87        /* Set rasid register to a known value. */
  88
  89        set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
  90
  91        /* Set PTEVADDR special register to the start of the page
  92         * table, which is in kernel mappable space (ie. not
  93         * statically mapped).  This register's value is undefined on
  94         * reset.
  95         */
  96        set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR);
  97}
  98
  99void init_kio(void)
 100{
 101#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
 102        /*
 103         * Update the IO area mapping in case xtensa_kio_paddr has changed
 104         */
 105        write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
 106                        XCHAL_KIO_CACHED_VADDR + 6);
 107        write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
 108                        XCHAL_KIO_CACHED_VADDR + 6);
 109        write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
 110                        XCHAL_KIO_BYPASS_VADDR + 6);
 111        write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
 112                        XCHAL_KIO_BYPASS_VADDR + 6);
 113#endif
 114}
 115